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Isolation process for VLSI
   
Document Number
US Patent 5236863
Issued Date
August 17, 1993
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Abstract
A process for forming an IC isolation trench pattern wherein the trenches have varying widths and are filled with near intrinsic single crystal silicon. Thus, the wiring that passes over the trenches has low capacitance and active circuit devices having improved high frequency performance can be fabricated into the silicon in the trenches. This increases the utilization of surface area thereby increasing active device density for VLSI applications.
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Isolation process for VLSI - US Patent 5236863 Drawing
Drawing from US Patent 5236863
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Number of Claims:
8
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Published
August 17, 1993
Application Number
07/891,886
Filed
June 1, 1992
US Classification
438/429   148/DIG.50 257/E21.364 257/E21.571 257/E21.572 257/E27.048
Int'l Classification
H01L   21/02   (20060101)   H01L   21/763   (20060101)   H01L   21/70   (20060101)   H01L   21/762   (20060101)   H01L   27/08   (20060101)   H01L   21/329   (20060101)  
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Assistant Examiner
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USPTO Field of Search
437/72   437/73   437/89   437/90   437/33   437/78   148/DIG.50  
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