A solid-state imaging device includes a semiconductor substrate, an array of cells on the substrate, a plurality of vertical charge transfer sections extending in a first direction on the substrate, and a horizontal charge transfer section extending in a second direction transverse to the first direction on the substrate and being coupled to the vertical charge transfer section. The cell array includes a plurality of columns of cells that are associated with a corresponding one of the vertical transfer sections. The cell columns include a predetermined number of spaced-part cells that are series-connected along the second direction to constitute a NAND type cell structure. At least one cell-to-cell charge transfer electrode overlies a channel region as defined between adjacent ones of the NAND cells in the substrate.

A color linear charge coupled device for an image pickup apparatus includes red, green, and blue photo diode arrays. First, second, third and fourth transfer gates formed in the device move signal charges generated at the photo diode arrays toward first, second and third horizontal charge coupled device (HCCD) shift registers. By controlling the transfer gates, the red and green signal charges are first transferred to their HCCD shift registers. The blue signal charge is then transferred to its HCCD shift register. Only three HCCD shift registers are required, thus, the device dimension and configuration is considerably simplified compared to prior art configurations. Also, the color resolution of the device is greatly improved because the distance between the respective photo diode arrays is substantially decreased.

A color linear image sensor includes first, second and third photosensitive pixel trains disposed in parallel in a manner close to each other, wherein an interpixel transfer section (10) for holding signal charges produced at the second photosensitive pixel train is provided between the second and third photosensitive pixel trains (12, 13). Since read-out operation from the second photosensitive pixel train is carried out by CCD register via the third photosensitive pixel train in the state where holding time is controlled by the interpixel transfer section, it is possible to freely adjust the integral time and the read-out timing.

An image sensor having a plurality of pixels arranged in a series of row and columns comprising: a semiconductor substrate having a plurality of pixels formed in rows and columns with at least two row adjacent pixels and at least two column adjacent pixels formed within the substrate; and at least one electrical function integrated within the adjacent pixels that is shared between the adjacent pixels. The electrical function can be either a contact region or an electrical circuit used in implementing either a photogate, a transfer gate, a reset gate, a row select gate, an amplifier drain, an output node, a floating diffusion contact, a reset drain, a lateral overflow gate, an overflow drain or an amplifier.

An image sensor having a plurality of pixels arranged in a series of row and columns comprising: a semiconductor substrate having a plurality of pixels formed in rows and columns with at least two row adjacent pixels and at least two column adjacent pixels formed within the substrate; and at least one electrical function integrated within the adjacent pixels that is shared between the adjacent pixels. The electrical function can be either a contact region or an electrical circuit used in implementing either a photogate, a transfer gate, a reset gate, a row select gate, an amplifier drain, an output node, a floating diffusion contact, a reset drain, a lateral overflow gate, an overflow drain or an amplifier.