A first (receiver), for example, pseudo random binary sequence (PRBS) generator (6) is synchronized with a second identical PRBS generator (2) at a tramsitter by adding a PRBS (u(x)) to a data stream (w(x)). The data stream includes a known value at periodic intervals. The received data is framed (5) and thus the position of the known data values determined. The received data is sampled at these positions to produce a sequence of samples (s(x)) comprising a sampled version of the transmitter PRBS. The phase of the transmitter generator (2) is determined for the samples and the phase of the receiver generator (6) adjusted to correspond. (FIG. 1). Implementation with sequence generators other than binary sequence generators are also discussed.
An improved method and computer to parse a data stream comprising a series of command strings is disclosed. The method provides superior performance in terms of balance between processor cycle usage, memory usage and portability across platforms.
A method for automatic power vector generation for sequential circuits produces input vectors for a power simulation required for accurate calculation of power dissipation of logic elements. More particularly, a worst-case-power-consumption logic vector pair for a sequential circuit is automatically generated by determining the worst-case-power-consumption logic vector pair, the second worst-case-power-consumption logic vector pair, up to the Nth worst-case-power-consumption logic vector pair in the combinational logic portion of the sequential circuit. The following is determined with respect to each of the N vector pairs: whether a feedback portion of a second logic vector in the logic vector pair is consistent with a feedback portion of a first logic vector output signal of the sequential circuit produced in response to a first logic vector in the logic vector pair, signifying that the second logic vector can be produced from the first logic vector; and, a setup vector sequence, for the first logic vector, of one or more logic vectors that when applied to the sequential circuit causes the feedback portion of the first logic vector to be produced, if such a setup sequence can be found. This procedure continues until for a particular logic vector pair the second logic vector can be produced from the first logic vector, and a setup sequence for the first logic vector has been found. The particular logic vector pair is then the worst-case-power-consumption logic vector pair. The worst-case-power-consumption logic vector pair and corresponding set-up vector sequence can then be used with a power simulation to find worst-case-power-consumption of the sequential circuit.
A data sequence is transmitted from a transmitter to a receiver, being scrambled at the transmitter by adding a pseudo random sequence (PRS) thereto. At the receiver the received data is unscrambled by subtraction of the same PRS. The receiver PRS generator is synchronised to the transmitter PRS generator by means of samples conveyed from the transmitter to the receiver. The transmitter includes a PRS sample mapping block, the receiver includes a functionally complementary sample mapping block and the time of transmission of the conveyed samples is decoupled from the points in the PRS for which they were selected, the conveyed samples being skewed with respect to the PRS.
A method and system for serially communicating a stream of data characters having bit-interleaved framing information. One embodiment discloses a method for interleaving a single bit of a frame marker sequence to each data character to demarcate each of the data characters and then serializing the data. The transmitting device serially transmits the data characters with bit-interleaved framing at a high transmission bit rate, over a single communication link. The receiving device captures the data stream and de-serializes the data. It then locates the bit position of the character boundary by detecting a predetermined frame marker sequence located in the same bit position over consecutive data characters. The offset is used to frame the data. A character rate greater than 70 MHz can be realized and a bit transmission rate of greater than 1 Gbit/second can be achieved.
A method for synchronizing interconnects in a link system according to various embodiments can include receiving input data at a transmit side, the transmit side including at least one pseudo-random bit sequence scrambler; scrambling the input data at the transmit side via the pseudo-random bit scrambler with dual tap sequences resulting in scrambled data; transmitting the scrambled data with the dual tap sequences along all lanes of a plurality of lanes to a receive side via a bus interconnecting the plurality of lanes, the receive side including at least one pseudo-random bit sequence descrambler; synchronizing the at least one pseudo-random bit sequence scrambler to the at least one pseudo-random bit sequence descrambler; using an edge detection or transition detection device for synchronization of the descrambler to the scrambler; and de-scrambling the transmitted scrambled data at the receive side resulting in the input data.
