A massively parallel processing system comprising a plurality of processing nodes controlled in parallel by a controller. The processing nodes are interconnected by a plurality of communications links. Each processing node comprises a memory, a transposer module and a router node. The memory stores data in slice format. The transposer module is connected to the memory and generates transpose data words of selected ones of the data slices from the memory. The router node is connected to the transposer module and to the communications links and transfers transpose data words over the communications links to thereby transfer the data slices between processing nodes. Finally, the controller controls the memories, transposer modules and router nodes of the processing nodes in parallel, to facilitate transfer of data slices among the processing nodes in unison.
A digital computer includes a plurality of processing elements, a command processor, a diagnostic processor and a communications network. The processing elements each performs data processing and data communications operations in connection with commands. The processing elements also performing diagnostic operations in response to diagnostic operation requests and providing diagnostic results in response thereto. The command processor generates commands for the processing elements, and also performs diagnostic operations in response to diagnostic operation requests and providing diagnostic results in response thereto. The diagnostic processor generates diagnostic requests. The communication network includes three elements, including a data router, a control network and a diagnostic network. The data router is connected to the processing elements for facilitating the transfer of data among them during a data communications operation. The control network is connected to the processing elements and the command processor for transferring commands from the command processor to the processing elements. The diagnostic network connected to the processing elements, the command processor and the diagnostic processor for transferring diagnostic requests from the diagnostic processor to the processing elements and the command processor and for transferring diagnostic results from the processing elements and the command processor to the diagnostic processor.
A method of transposing data. Either eight bit or sixteen bit data is placed in a buffer. Each buffer is defined to contain one or more sub-buffers. Rows of the sub-buffer are selectively interleaved with the results of the selective interleaving being again interleaved in a specific order. Successive interleavings create the transpose of the original sub-buffer.
A method of effecting a matrix transpose operation in a computer is described. The method uses a computer instruction which restructures a data string by retaining first and last sub-strings of the data string in unchanged positions and interchanges the position of at least two intermediate sub-strings. The data string is formed from sub-strings each representing one or more data value in a matrix. The computer instruction can be effected in a single register store having a predetermined bit capacity addressable by a single address, or in a pair of such register stores. The data restructuring instructions include "flip", "zip" and "unzip" instructions.
A massively parallel computer system including a plurality of processing nodes under control of a system controller. The processing nodes are interconnected by a plurality of communications links. Each processing node comprises at least one processor, a memory, and a router node connected to the communications links for transferring in a series of message transfer cycles messages over the communications links. The controller enables each processing node to establish a message queue in its memory. The controller further enables storage of messages received by the processing nodes for their respective processors during a message transfer cycle to be stored in the message queue.
A data processing system having a plurality of processing units (C1, C2), a plurality of memory units (M1, M2) and a communication system providing communication between the processing units and the memory units. The processing units each have a plurality of register sets (R1, R2) allowing them to run a plurality of processes. When a process requires data from memory, which it receives over the communication system, its respective processing unit processes another of its processes until that requires data. Data is transmitted over the communication system, which may be configured as a grid, in the form of packets. The grid is configured from routing devices which include first-in-first-out devices for the buffering of packets. The system facilitates the construction of circuits integrated onto a singel wafter of semiconducting material. Furthermore the grid structure may also be employed as a local area network and computers having a similar architecture may be connected to the network providing a processing facility of considerable power.
