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Claims  |
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What is claimed is:
1. Electrical current source circuitry for a bus, comprising:
(A) transistor means coupled between the bus and ground for controlling bus
current;
(B) control circuitry coupled to the transistor means;
(C) a controller coupled to the control circuitry for controlling the
transistor means, wherein the controller comprises:
(1) a variable level circuit comprising
(a) setting means for setting a desired current for the bus; and
(b) transistor reference means coupled to the setting means, wherein the
variable level circuit provides a first voltage;
(2) voltage reference means for providing a reference voltage;
(3) comparison means coupled to the voltage reference means and the
variable level circuit for comparing the first voltage with the reference
voltage;
(4) logic means responsive to a trigger signal from the comparison means,
wherein an output of the logic means is coupled to the control circuitry
in order to turn on the transistor means in a manner dependent upon the
output of the logic means.
2. The electrical current source circuitry of claim 1, wherein
(A) the transistor means comprises a plurality of transistors;
(B) the control circuitry comprises logic circuitry coupled to the gates of
the plurality of transistors.
3. The electrical current source circuitry of claim 1, wherein the
transistor means comprises a transistor.
4. The electrical current source circuitry of claim 2, wherein the logic
means comprises a counter for counting until receiving a trigger signal
from the comparison means, wherein the output of the counter is coupled to
the logic circuitry in order to turn on a particular combination of the
plurality of transistors in a manner dependent upon a count of the
counter.
5. The electrical current source circuitry of claim 4, wherein the counter
is set to a final count upon receiving the trigger signal from the
comparison means, wherein the final count is latched, and wherein the
output of the counter coupled to the logic circuitry is the latched final
count of the counter.
6. The electrical current source circuitry of claim 2, wherein the setting
means is an external resistor.
7. The electrical current source circuitry of claim 2, wherein respective
widths of the plurality of transistors coupled between the bus and ground
are binary multiples of one another.
8. The electrical current source circuitry of claim 1, wherein the
transistor reference means comprises a plurality of transistors.
9. The electrical current source circuitry of claim 8, wherein respective
widths of the plurality of transistors of the transistor reference means
are substantially smaller than the respective widths of the plurality of
transistors coupled between the bus and ground.
10. The electrical current source circuitry of claim 1, wherein the setting
means comprises a plurality of capacitors.
11. The electrical current source circuitry of claim 10, wherein the
transistor reference means is a current mirror circuit.
12. The electrical current source circuitry of claim 10, wherein respective
capacitances of the plurality of capacitors are binary multiples of one
another.
13. The electrical current source circuitry of claim 10, wherein the
plurality of capacitors are coupled to the transistor reference means in a
user-settable manner.
14. The electrical current source circuitry of claim 1, wherein the
settable desired current is substantially independent of a power supply
variation, a process variation, and a temperature variation.
15. An output driver for an electronic device coupled to a bus, wherein the
bus is coupled to a voltage supply via a termination resistor, wherein the
output driver comprises:
(A) a plurality of transistors coupled between the bus and ground for
controlling bus current;
(B) control circuitry coupled to gates of the plurality of transistors;
(C) a controller coupled to the control circuitry for controlling the
plurality of transistors, wherein the controller comprises:
(1) resistor means coupled to the voltage supply for setting a desired
current;
(2) transistor reference means comprising a plurality of transistors
coupled between the resistor means and ground, wherein the plurality of
transistors of the transistor reference means are selectively turned on to
provide a variable voltage;
(3) comparison means coupled to receive the variable voltage for comparing
the variable voltage with a reference voltage;
(4) a counter; and
(5) control logic coupled to (i) the comparison means and (ii) the counter
for causing the counter to count until a particular combination of the
plurality of transistors of the transistor reference means is turned on by
an output of the counter such that the variable voltage is approximately
equal to the reference voltage, wherein the output of the counter is also
coupled to the control circuitry in order to turn on a particular
combination of the plurality of transistors coupled between the bus and
ground.
16. The output driver of claim 15, wherein the control circuitry comprises
logic circuitry.
17. The output driver for an electronic device of claim 15, wherein the
plurality of transistors coupled between the bus and ground comprise five
N-channel metal-oxide semiconductor (NMOS) transistors, wherein respective
widths of the five NMOS transistor are binary multiples of one another.
18. The output driver of claim 17, wherein the plurality of transistors of
the transistor reference means comprise five NMOS transistors, wherein
respective widths of the five NMOS transistors of the transistor reference
means are substantially smaller than the widths of the respective five
NMOS transistors of the plurality of transistors coupled between the bus
and ground.
19. The output driver of claim 15, wherein the resistor means comprises a
resistor with a resistance five times a resistance of the termination
resistor.
20. The output driver of claim 15, wherein the electronic device is a
microprocessor.
21. The output driver of claim 15, wherein the electronic device is a
dynamic random access memory (DRAM).
22. The output driver of claim 15, wherein the voltage supply is
approximately 2.5 volts and the reference voltage is approximately 2.2
volts.
23. The output driver of claim 15, wherein the control circuitry comprises
a plurality of logic gates, wherein each logic gate is coupled to a gate
of a respective one of the plurality of transistors.
24. The output driver of claim 15, further comprising a latch coupled to
the counter for latching the count of the counter and for supplying the
count to the control circuitry.
25. The output driver of claim 15, wherein the settable desired current is
substantially independent of a power supply variation, a process
variation, and temperature variation.
26. An output driver for an electronic device coupled to a bus, wherein the
bus is coupled to a voltage supply via a termination resistor, wherein the
output driver comprises:
(A) a plurality of transistors coupled between the bus and ground for
controlling bus current;
(B) control circuitry coupled to gates of the plurality of transistors;
(C) a controller coupled to the control circuitry for controlling the
plurality of transistors, wherein the controller comprises:
(1) current mirror means coupled to a voltage supply and ground, wherein
the current mirror means has an output supplying a current with a
predetermined value proportional to a desired current;
(2) capacitor means having a plurality of capacitors selectively coupled to
the output of the current mirror means, wherein the capacitor means
receives the current from the current mirror means, wherein the capacitor
means provides a variable voltage when charged by the current;
(3) comparison means coupled to receive the variable voltage for comparing
the variable voltage with a reference voltage;
(4) a counter; and
(5) control logic coupled to (i) the counter, (ii) the comparison means,
and (iii) the output of the current mirror means for causing the capacitor
means to be charged to the variable voltage and for causing the counter to
start counting when the capacitor means is charged, wherein the control
logic causes the counter to count until receiving a trigger signal from
the comparison means that indicates that the variable voltage is
approximately equal to the reference voltage, wherein an output of the
counter is coupled to the control circuitry in order to turn on a
particular combination of the plurality of transistors in a manner
dependent upon a count of the counter.
27. The output driver of claim 26, wherein the control circuitry comprises
logic circuitry.
28. The output driver of claim 26, wherein the electronic device is a DRAM.
29. The output driver of claim 26, wherein the electronic device is a
microprocessor.
30. The output driver of claim 26, wherein the plurality of transistors
comprise five NMOS transistors, wherein respective widths of the five NMOS
transistors are binary multiples of one another.
31. The output driver of claim 26, wherein the current mirror means
comprises a first P-channel transistor, a second P-channel transistor, and
a first N-channel transistor, wherein a width of the first N-channel
transistor is equal to that of one of the plurality of transistors,
wherein a width of the first P-channel transistor is approximately twenty
times of that of the second P-channel transistor.
32. The output driver of claim 26, wherein the plurality of the capacitors
have capacitances that are binary multiples of one another.
33. The output driver of claim 26, wherein the plurality of capacitors are
coupled to the output of the current mirror means in a user-settable
manner.
34. The output driver of claim 26, wherein the reference voltage is
approximately 2.2 volts and the voltage supply is equal to approximately
2.5 volts.
35. The output driver of claim 27, wherein the logic circuitry comprises a
plurality of logic gates, wherein each logic gate coupled to a gate of a
respective one of the plurality of transistors.
36. The output driver of claim 26, wherein the settable desired current is
substantially independent of a power supply variation, a process
variation, and a temperature variation.
37. The output driver of claim 26, further comprising a latch coupled to
the counter for latching the count of the counter and for supplying the
count to the control circuitry.
38. The output driver of claim 26, wherein the electronic device is a
slave, wherein a master is coupled to the bus, and wherein the master
causes selective ones of the plurality of capacitors to be coupled to the
output of the current mirror means.
39. In a bus system comprising a bus, a master, and a slave with an output
driver, a method for setting a current of the output driver for the bus of
the slave comprising the steps of:
(A) setting a register setting to a first value;
(B) having the master send the register setting to the output driver of the
slave;
(C) having the slave couple selective ones of a plurality of capacitors to
an output of a current mirror means of the output driver based upon the
register setting received from the master;
(D) causing the plurality of capacitors that are coupled to the output of
the current means to charge to a variable voltage while a counter counts;
(E) comparing the variable voltage to a reference voltage;
(F) when the variable voltage approximately equals the variable voltage,
then stopping the counter from counting and latching a final count of the
counter;
(G) turning on a particular combination of a plurality of transistors
coupled between the bus and ground based upon the final count of the
counter in order to generate a first voltage level on the bus;
(H) sensing within the master the first voltage on the bus;
(I) comparing within the master the first voltage with the reference
voltage;
(J) if the register setting does not approximately equal the reference
voltage, then changing the register setting and repeating steps B through
J;
(K) if the register setting does approximately equal the reference voltage,
then:
(1) setting the register setting to a value that is double a present value
of the register setting;
(2) having the master send the register setting to the output driver of the
slave;
(3) having the slave couple selective ones of the plurality of capacitors
to the output of the current mirror means of the output driver based upon
the register setting received from the master. |
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Claims |
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Description |
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FIELD OF THE INVENTION
The present invention pertains to the field of electrical buses. More
particularly, the present invention relates to current source driver
circuitry for a high speed bus system.
BACKGROUND OF THE INVENTION
Computer systems and other electronic systems typically use buses for
interconnecting integrated circuit components so that the integrated
circuit components can communicate with one another. Prior buses typically
connect masters such as microprocessors and controllers and slaves such as
memories and bus transceivers.
Certain prior buses employ relatively large voltage swings. For example,
one prior bus has rail to rail voltage swings between a high level voltage
of 3.5 to 5 volts and a low level voltage of approximately zero volts.
One disadvantage of large voltage swing buses is the relatively high level
of power dissipation. Another disadvantage of large voltage swing buses is
the relatively high level of induced noise. The problems of high power
dissipation and a high level of induced noise become ever more severe when
buses are run at higher and higher frequencies.
Another typical disadvantage of large voltage swing buses is a speed
limitation caused by the high slew rate of the bus driver.
Buses with relatively low rail-to-rail voltage swings have been developed
to minimize power dissipation and noise, especially at high bus
frequencies. Certain buses with low voltage swings also typically permit
higher frequencies.
Each master and slave coupled to a prior bus typically includes output
driver circuitry for driving signals onto the bus. Some prior bus systems
have output drivers that use transistor-transistor logic ("TTL")
circuitry. Other prior bus systems have output drivers that include
emitter-coupled logical ("ECL") circuitry. Other output drivers use CMOS
or N-channel metal oxide semiconductor ("NMOS") circuitry. Gunning
transistor logic ("GTL") has also been used in other prior output drivers.
Many prior buses are driven by voltage level signals. It has become
advantageous, however, to provide buses that are driven by a current mode
output driver. One benefit to a current mode driver is a reduction of peak
switching current. For a voltage mode driver the output transistor of the
driver must be sized to drive the maximum specified current under worst
case operating conditions. Under nominal conditions with less than maximum
load, the current transient when the output is switched, but before it
reaches the rail, can be very large. The current mode driver, on the other
hand, draws a known current regardless of load and operating conditions.
In addition, for a voltage mode driver impedance discontinuities occur
when the driving device is characterized by a low output impedance when in
a sending state. These discontinuities cause reflections which dictate
extra bus settling time. Current mode drivers, however, are characterized
by a high output impedance so that a signal propagating on the bus
encounters no significant discontinuity in line impedance due to a driver
in a sending state. Thus, reflections are typically avoided and the
required bus settling time is decreased.
An example of a current mode bus is disclosed in U.S. Pat. No. 4,481,625,
issued Nov. 6, 1984, entitled High Speed Data Bus System. An NMOS current
mode driver for a low voltage swing bus is disclosed in PCT international
patent application number PCT/US91/02590 filed Apr. 16, 1991, published
Oct. 31, 1991, and entitled Integrated Circuit I/O Using a High
Perforamnce Bus Interface.
One disadvantage of certain prior current mode drivers is that current
sometimes varies from driver to driver. Variations can also happen over
time. Temperature variations, process variations, and power supply
variations sometimes cause such variations. Current variations in turn
lead to voltage level variations on the bus. Bus voltage level variations
can in turn lead to the erroneous reading of bus levels, which can reuslt
in the loss of data or other errors. In addition, attempts to design
around these variations by raising voltage levels sometimes leads to
higher power dissipations, especially in extreme cases. In any event,
variations in bus voltage levels are typically more problematic for buses
with low voltage swings.
Certain prior feedback techniques have been used to control current. An
article by H. Schumacher, J. Dikken, and E. Seevinck entitled CMOS
Subnanosecond True-ECL output Buffer, J. Solid State Circuits, Vol. 25,
No. 1, pages 150-54 (February 1990) includes a disclosure of the use of
feedback.
SUMMARY AND OBJECTS OF THE INVENTION
One object of the present invention is to provide an improved current mode
driver for a bus.
Another object of the present invention is to provide a current mode driver
that provides a relatively accurate current.
Another object of the present invention is to provide a current mode driver
that minimizes current variations when there are variations in supply
voltage, temperature, and processing.
Another object of the present invention is to provide a current mode driver
with a performance that is relatively independent of voltage supply
variations, temperature variations, and processing variations.
Another object of the present invention is to provide a current mode driver
having a user-settable current.
Another object of the present invention is to provide a current mode driver
that minimizes space.
Electrical current source circuitry for a bus is described. The circuitry
includes transistor circuitry coupled between the bus and ground for
controlling bus current, control circuitry coupled to the transistor
circuitry, and a controller coupled to the control circuitry for
controlling the transistor circuitry. The controller comprises a variable
level circuit comprising setting means for setting a desired current for
the bus and transistor reference means coupled to the setting means. The
variable level circuit provides a first voltage. A voltage reference means
provides a reference voltage. A comparison means is coupled to the voltage
reference means and to the variable level circuit for comparing the first
voltage with the reference voltage. Logic circuitry is responsive to a
trigger signal from the comparison means. An output of the logic circuitry
is coupled to the control circuitry in order to turn on the transistor
circuitry in a manner dependent upon an output of the logic circuitry.
Other objects, features, and advantages of the present invention will be
apparent from the accompanying drawings and from the detailed description
that follows below.
BRIEF DESCRIPTION OF THE DRAWINGS
The present invention is illustrated by way of example and not limitation
in the figures of the accompanying drawings, in which like references
indicate similar elements and in which:
FIG. 1 is a block diagram of a bus system, including a master, a plurality
of slaves, and a bus;
FIG. 2 is a block diagram of a master and a slave coupled to the bus,
wherein the master and slave each includes an interface circuit;
FIG. 3 is a voltage level diagram illustrating the voltage levels of the
logic one and logic zero signals of the bus system of FIG. 1;
FIG. 4 is a circuit diagram of a current mode driver, including a current
controller and an NMOS transistor array;
FIG. 5 is a current-voltage diagram of an NMOS transistor, illustrating the
drain current with respect to the drain-to-source voltage and the
gate-to-source voltage;
FIG. 6 is a circuit diagram of one embodiment of the current controller of
FIG. 4;
FIG. 7 is a circuit diagram of another embodiment of the current controller
of FIG. 4;
FIG. 8 is a flow chart that shows the process of calibrating the
capacitance of the current controller of FIG. 7;
FIG. 9 is a circuit diagram of another current mode driver;
FIG. 10 is a circuit diagram of yet another current mode driver.
DETAILED DESCRIPTION
FIG. 1 is a block diagram of a bus system 10. Bus system 10 includes a bus
30 that is coupled to master 11 and a plurality of slaves 12a-12n for
transferring data between the masters and the slaves. Bus 30 is a high
speed, low voltage swing bus that comprises a total of eleven lines.
Master 11 and each of the slaves 12a-12n includes an interface circuit for
coupling its respective master or slave to bus 30. The interface circuit
includes a plurality of current mode drivers for driving bus 30. For each
master and slave, there is one output driver for each transmission line of
bus 30. Each of the current mode drivers accurately provides a desired
current for the respective line of bus 30.
As described in more detail below, each of the current mode drivers
includes a plurality of transistors coupled in parallel between a
respective line of the bus and ground. A logic circuit is coupled to the
gates of the plurality of transistors. The widths of the transistors are
binary multiples of one another. A current controller is coupled to the
logic circuit for controlling the logic circuit in order to turn on or off
a particular combination of the plurality of transistors such that the
desired current can be selected for the line of the bus. The desired
current for the line of the bus in turn becomes a desired voltage for the
line of bus 30. The controller includes a variable level circuit, a
comparator, a counter, and a control logic. Once selected, the desired
current is relatively independent of power supply, process, and
temperature variations.
Within bus system 10, a master can communicate with another master (not
shown) and with slaves. In contrast, slaves only communicate with masters.
Master 11 of FIG. 1 contains intelligence and generates requests. In one
embodiment, master 11 is a microprocessor. In another embodiment, master
11 is a digital signal processor. In yet another embodiment, master 11 is
a graphics processor. In alternative embodiments, other types of
processors or controllers can be employed as master 11. For example,
master 11 may be peripheral controller, an input/output ("I/O) controller,
a DMA controller, a graphics controller, a DRAM controller, a
communications device, or another type of intelligent controller.
Slaves only require a low level of intelligence. In one embodiment, slaves
12a-12n comprise DRAMs. In other embodiments, slaves 12a-12n may include
other types of memories, such as electical programmable read only memories
("EPROMs"), flash EPROMs, RAMs, static RAMs ("SRAMs"), and video RAMs
("VRAMs"). For another embodiment, slaves 12a-12n are bus transceivers.
Master 11 and slaves 12a-12n each includes BusData [8:0]pins, a BusCtrl
pin, a BusEnable pin, a ClkToMaster pin, a ClkFromMaster pin, and a
V.sub.ref pin. These pins receive and transmit low voltage swing signals.
The BusData pins are used for data transfer. In one embodiment, the
BusData pins comprise nine data pins. The BusCtrl and BusEnable pins are
used for transferring bus control signals for controlling communication on
bus 30. The ClkToMaster and ClkFromMaster pins receive clock signals. The
ClkToMaster pin receives a "clock-to-master" signal. The ClkFromMaster pin
receives a "clock-from-master" signal The V.sub.ref pin receives a
reference voltage V.sub.ref.
Master 11 and each of the slaves 12a-12n also includes an SIn pin and an
SOut pin. The SIn pin and SOut pins are coupled to form a daisy chain for
device initialization. Master 11 and each of the slaves 12a-12n also
includes Gnd and GndA ground pins (coupled to lines 18) and Vdd and VddA
power supply pins (coupled to lines 19). For one embodiment, power supply
voltages Vdd and VddA are each five volts.
Bus 30 includes BusData data transmission lines 32, a BusCtrl line 14, and
a BusEnable line 15. Bus 30 carries low voltage swing signals that are
described in more detail below.
Data transmission lines 32 comprise a data bus for transferring data
between master 11 and slaves 12a-12n. For one embodiment, data
transmission lines 32 are capable of transferring data at rates up to 500
Megabytes per second.
Data transmission lines 32 comprise nine transmission lines. These
transmission lines are matched transmission lines and have controlled
impedances. Each line of data transmission lines 32 is terminated at one
end by a termination resistor. As shown in FIG. 1, there are nine
termination resistors, each connected to a respective one of data
transmission lines 32. These termination resistors are collectively
referred to as termination resistors 20. Termination resistors 20 are
coupled to termination voltage V.sub.term.
The resistance value of each of termination resistors 20 is R, which is
equal to the line impedance of each transmission line of data transmission
lines 32. In one embodiment, the termination voltage V.sub.term is
approximately 2.5 volts. Each of the termination resistors 20 is matched
to the respective transmission line impedance. This helps to prevent
reflections.
BusCtrl line 14 transfers the bus control signal among master 11 and slaves
12a-12n. BusEnable line 15 transfers the bus enable signal among master 11
and slaves 12a-12n. BusCtrl line 14 is terminated at one end by
termination resistor 23. BusEnable line 15 is terminated at one end by
termination resistor 21. Termination resistors 21 and 23 are each coupled
to the termination voltage V.sub.term. Each of the termination resistors
21 and 23 is matched to the respective line impedance. This helps to
prevent reflections.
Bus system 10 also includes daisy chain line 13 and clock line 16. Daisy
chain line 13 couples the SOut pin of one device to the SIn pin of another
device (i.e., chained) for transferring TTL signals for device
initialization. Line 16 is terminated by termination resistor 22.
Clock line 16 is coupled to a clock 35 at one end. In one embodiment, clock
35 is external to and independent of master 11 and slaves 12a-12n. The
clock signal generated by clock 35 travels only in one direction. Clock
line 16 carries the clock signal to master 11 and slaves 12a-12n. Clock
line 16 is folded back to include two segments 16a and 16b. Segment 16a
carries a "clock-to-master" signal and segment 16b carries a
"clock-from-master" signal.
Bus system 10 also includes a reference voltage line 17 that couples the
reference voltage V.sub.ref to each of master 11 and slaves 12a-12n. As
shown in FIG. 2, the V.sub.ref voltage is generated by a voltage divider
formed by resistors 25 and 26, with the termination voltage V.sub.term
being coupled to resistor 25. In one embodiment, the reference voltage
V.sub.ref is approximately 2.20 volts. In another embodiment, the
reference voltage V.sub.ref is approximately 2.25 volts.
Data driven by master 11 propagates past slaves 12a-12n along bus 30 and
slaves 12a-12n can correctly sense the data provided by master 11. Slaves
12a-12n can also send data to master 11.
In an alternative embodiment, bus system 10 may include two masters coupled
to the end of bus 30 that is opposite termination resistors 20, 21, and
23.
Master 11 initiates an exchange of data by broadcasting an access request
packet. Each of slaves 12a-12n decodes the access request packet and
determines whether that slave is the selected slave and the type of access
requested. The selected slave then responds appropriately.
As described in more detail below, master 11 is coupled to the termination
voltage V.sub.term via a resistor 31. Resistor 31 is used to set a desired
current for bus 30. Resistor 31 is located external to master 11. The
resistance of resistor 31 is 5R--i.e., five times that of each of
termination resistors 20. For other embodiments, other resistance values
may be used for resistor 31 and resistors 20.
FIG. 2 is a block diagram of master 11 and slave 12a. In FIG. 2, slave 12a
is a DRAM.
Master 11 includes an engine 70 and peripheral circuitry 71. For one
embodiment of the present invention, engine 70 is a microprocessor.
Peripheral circuitry 71 includes clock circuitry, control circuitry,
registers, counters, and status logic. Master 11 is coupled to bus 30 via
an interface circuit 81.
Similarly, slave 12a includes DRAM circuitry 72 and peripheral circuitry
73. DRAM circuitry 72 includes a memory array and sense circuitry. Like
peripheral circuitry 71, peripheral circuitry 73 also includes clock
circuitry, control circuitry, registers, counters, and status logic. Slave
12a is coupled to bus 30 via interface circuit 82.
Interface circuits 81 and 82 each converts between low-swing voltage levels
used by bus 30 and ordinary CMOS logic levels used by much of the
circuitry of master 11 and slave 12a.
Interface circuits 81 and 82 each includes a plurality of current mode
drivers for driving the data onto bus 30. The current mode drivers are
also referred to as electrical current sources. Bus 30 is a current mode
bus that is driven by the current source output drivers. Each of the
current mode drivers in interface circuit 81 is coupled to a respective
transmission line of bus 30. That is also true with respect to each of the
current mode drivers in interface circuit 82.
Slaves 12b-12n have similar circuitry to that of slave 12a. It is to be
appreciated that master 11 and slaves 12a-12n each include current mode
output drivers for bus 30.
Even though the drivers for bus 30 are current mode drivers, bus 30 carries
low voltage swing signals. The current mode drivers of master 11 and
slaves 12a-12n control the voltage levels of bus 30. When a current mode
driver is in an "off" state, the respective bus line either stays at or
rises to a high voltage level. When the current mode driver is in an "off"
state, there is approximately zero voltage drop across the respective
termination resistor of resistors 20 because the current mode driver is
not providing a path to ground for current. The high voltage level for bus
30 is the termination voltage V.sub.term.
When a current mode driver is in an "on" state, the current mode driver
provides a path to ground for current for the respective bus line. In
other words, when the current mode driver is in an "on" state, pull down
current flows through the current driver. The low voltage level of bus 30,
is accordingly, determined by the pull down current. The pull down current
flows through the respective resistor of termination resistor of resistors
20. A voltage drop appears across the respective termination resistors 20,
and a low voltage level appears on the respective line of bus 30. The pull
down current (flowing through the output driver and the respective
termination resistor) is referred to as the desired current. The magnitude
of the desired current can be set or selected by the user to allow for
different bus impedance, noise immunity, and power dissipation
requirements. Circuitry described below permits the desired current to be
substantially independent of processing variations, power supply
variations, and temperature variations.
FIG. 3 illustrates preferred voltage levels V.sub.OH (i.e., V.sub.term) and
V.sub.OL for bus system 10. V.sub.OH --the high voltage level--is
approximately 2.5 volts. V.sub.OL --the low voltage level--is
approximately 1.9 volts. The reference voltage is 2.2 volts. The voltage
swing is approximately 0.6 volts. For one embodiment, the V.sub.OH voltage
represents a logical zero state and the V.sub.OL voltage represents a
logical one state.
For an alternative embodiment, the V.sub.OH voltage is approximately 2.5
volts, the V.sub.OL voltage is approximately 2.0 volts, the voltage swing
is approximately 0.5 volts, and the reference voltage is 2.25 volts.
As discussed in more detail below, the termination voltage V.sub.term can
be changed and the low voltage V.sub.OL can be selected or set by the user
by selecting a desired current.
Given that V.sub.OH is a logical zero state, this means that a current mode
driver is placed into the "off" (i.e., nonconducting) state when the
respective master or slave wants to drive a logical zero signal onto the
respective line of bus 30. Given that V.sub.OL is a logical one state,
this means that a current mode driver is placed into the "on" (i.e.,
conducting) state when the respective master or slave wants to drive a
logical one signal onto the respective line of bus 30.
FIG. 4 is a block diagram of a current mode driver 100. Driver 100
represents one of the plurality of current mode drivers found in master 11
and slaves 12a-12n.
In FIG. 4, driver 100 is coupled to data transmission line 111 via output
pad 110. Data transmission line 111 is one of the data transmission lines
32 of bus 30. Transmission line 111 is coupled to the termination voltage
V.sub.term via termination resistor 112 that resides at one end.
Termination resistor 112 is one of resistors 20.
Driver 100 includes an output transistor array 101. Transistor array 101 is
comprised of five transistors 101a through 101e. For alternative
embodiments, transistor array 101 can include more or fewer than five
transistors. For example, transistor array 101 may include eight
transistors.
For one embodiment, transistors 101a-101e of transistor array 101 are
N-channel MOS transistors.
Transistors 101a-101e of transistor array 101 are coupled in parallel
between ground and output pad 110. Each of transistor 101a-101e has a
different width. The widths of transistors 101a-101e are governed by a
binary relationship. This is shown by the designations 1X, 2X, 4X, 8X, and
16X in FIG. 4. The symbol "x" means "times." For example, the width of
transistor 101b is twice that of transistor 101a. The width of transistor
101c is twice that of transistor 101b.
Transistors 101a-101e are used to provide a path to ground for current.
When one or more of transistors 101a-101e is turned on, current flows
through each transistor that is turned on. The current flow results in a
voltage drop across resistor 112. This results in the lowering of the
voltage on line 111 of bus 30. When transistors 101a-101e are all turned
off, then | | |
