A video system is disclosed which is capable of receiving digital data from a source such as a video camera, and subsequently transferring the received data into a main frame buffer for display on a video display, where the data from the source can overlay a primary image stored in the main frame buffer. An auxiliary frame buffer, consisting of a bank of dual-port RAMs, receives the data of the overlay image via its serial port and transfers this data into the randomly accessible array therein. A direct-memory-access (DMA) operation performs the transfer from the auxiliary frame buffer into the main frame buffer, with the source and destination positions in the auxiliary and main frame buffers, respectively, independently selectable. The performance of the DMA operation can be enhanced by simultaneously performing a page mode read of the auxiliary frame buffer with a page mode write to the main frame buffer.
This application is a continuation of U.S. patent application Ser. No. 07/486,339 filed Feb. 28, 1990, now U.S. Pat. No. 5,099,331, which is a continuation of U.S. patent application Ser. No. 07/093,462 filed Sep. 4, 1987, now U.S. Pat. No. 4,907,086.
Systems and methods for compositing an image directly from multiple source image data for reducing system memory footprint and bandwidth and for improving color quality of the image. The image is divided into spans, lines, and slices. Each line includes at least one span and each slice includes at least one line. All lines in a slice have spans associated with identical sources. An image is composited by reading the image data directly from one or more sources of each span. If necessary, the sources are blended. A control structure is used to provide the image context and identifies the sources of the spans. The control structure includes headers for each data stream from each source of each span. Also, the color quality of the image is improved by reducing the number of color space conversions that occur as the image is composited. All sources in the same color space are blended before being blended with sources from other color spaces. Preferably, no more than a single color conversion is required.
A memory efficient method and apparatus for displaying large overlaid camera images. According to one aspect of the invention, overlay image data are stored in a memory, fetched, up-scaled, and then combined with main image data to form composite image data for rendering on a graphics display device. According to another aspect of the invention, the overlay image data are stored in a memory, fetched, and then combined with main image data streamed from a source of the main image data.
This is a dual film and digital camera with an internal EPROM which holds a full graphics editor and a full communications program. The communications program auto senses which external port is active and uploads itself and the graphics program and any digital images which have been taken by the camera to the remote cite.
A method and apparatus for quickly copying a first frame region into a second frame region. A video memory array comprising a plurality of video random access memory devices is divided into at least two frame regions. A background image is rendered by a central processing unit into a background frame region within the video memory array. The central processing unit then requests the background image in the background frame region to be copied into a new frame region in the video memory array. A dedicated circuit copies the entire background image in the background frame region into the new frame region. The dedicated circuit operates by using a serial data register within each video random access memory device during the vertical retrace period of a video timing signal. The dedicated circuit performs the background frame copy without requiring any processing resources from the central processing unit.
A shared memory graphics accelerator system that provides graphics display data to a display includes a central processing unit for generating graphics display data and graphics commands for processing the display data. An integrated graphics display memory element includes both a graphics accelerator connected to receive display data and graphics commands from the central processing unit and an on-chip frame buffer memory element. The on-chip frame buffer memory element is connected to receive display data from the graphics accelerator via a display data distribution bus. An off-chip frame buffer memory element is also connected to the display data distribution bus to receive display data from the graphics accelerator. The graphics accelerator selectively distributes display data to the on-chip frame buffer memory element and to the off-chip frame buffer memory element based on predetermined display data distribution criteria.
