Several hybrid CMOS circuit configurations that include both static CMOS logic and Domino CMOS logic are described. Each circuit configuration includes two registers that surround the Domino logic to allow that logic to be tested. One of the registers receives an input test vector that can either be loaded directly through a primary set of inputs or by a serial scan chain if the inputs to the register are not directly accessible. The second register is used to latch the results of the test vector application. The contents of this register can then either be read directly through a primary set of outputs if there is no static CMOS logic between the outputs of the register and a primary set of outputs of the circuit, or scanned out of the second register using a serial scan chain. A Domino scan flip-flop is also described that produces significant transistor count reduction over conventional static scan flip-flops. These Domino scan flip-flops can be used in the Domino logic as sequential elements to allow a multiplicity of logic functions to be implemented using Domino logic. These scan flip-flops can then be serially connected either as part of a separate scan chain or integrated into a single scan chain with the registers and any other static scan flip-flops in the circuit. These Domino scan flip flops allow all of the nominal logic to be tested in conjunction with the two registers. A relationship between a Domino clock that is used to drive the Domino logic in a system clock that is used to drive the static CMOS logic is described which ensures that a correct test data is applied and read out from the hybrid circuit.

A design for test focused tester has a single printed circuit board tester architecture. By focusing on design for test testing and eliminating functional testing, the design for test focused tester reduces or eliminates requirements for high speed, precision signal formatting and timing circuitry that require a multiple board architecture interconnected via a high speed backplane. The single board architecture places a vector sequencer and vector memory close to the device under test, which provides short, consistent signal paths to the device and eliminates the need for dead cycles and synchronization between tester boards.

Wrapper cells (16 and 18) are coupled to inputs and outputs of an embedded core (14) within an integrated circuit (10). The wrapper cells (16 and 18) are used to test timing specifications of the embedded core after the embedded core has been integrated on-chip with other peripheral logic (12). In order to accurately measure the timing specifications, test circuits (FIGS. 6-8) are formed on chip with the wrapper where the test circuits are used to measure clock skew a like internal integrated circuit (IC) parameters. The clock skew and other measured internal IC parameters are used to accurately test the timing specification of the embedded core with reduced uncertainty.

A boundary scan test circuit comprises a plurality of register cells correspondingly to external pins of a semiconductor device, the register cells being coupled together to form a shift register during a test operation mode. The register cells includes a first selector for selecting one of a parallel input data, serial input data and a code signal, a first register for latching the output of the first selector to output a serial data to be input to a succeeding register cell, a second register for latching the output of the first selector, a second selector for selecting the parallel data or the output of the second register to output parallel data. The code signal is determined based on corresponding one of bits of ID code of the semiconductor device. The ID code is output from the register cells without providing an ID code register, resulting in a simple construction of the register cells and a reduced chip area for the semiconductor device.

Switching circuits are connected between data input lines to and data output lines to connect switch paths between them. A two-input selector is connected to each of the data input lines to supply a data input signal or a test signal to the switching circuits. The selection of the two signals depends on whether the data input line is being used or not. The switch path connections in the switching circuits are controlled by the switching control circuits. Normally, a particular switch path is connected, but while testing, all the switch paths of an unoperated switching circuit which is not normally selected, are connected by a test address signal. The outputs of the switching circuits are detected by an error detector and compared with an expected data sequence, which indicates which output of the switching circuits is detected by the error detector.