A shared bus system having a bus and a set of client modules coupled to the bus. Each client module is capable of sending transactions on the bus to other client modules and receiving transactions on the bus from other client modules for processing. Each module has a queue for storing transactions received by the module for processing. A bus controller limits the types of transactions that can be sent on the bus to prevent any module's queue from overflowing.

Recovery of data from a store-to cache in a malfunctioning CPU, is accomplished without exercising the hardware of the malfunctioning CPU. A data path which is independent of the normal operating paths of the computer, such as a scan facility, is used to move data out of the cache into the mainstore while the malfunctioning CPU's clocks are off. A system controller controls normal transfer of data between the cache memory of the processing unit and the mainstore. A service processor is coupled to the processing unit, the mainstore, and the system controller, and is responsive to the detection of errors in the processing unit, for stopping the processing unit and moving data out of the cache memory to the mainstore through the scan facility separate from the system controller. Logic in the system controller flushes the move out queue or other storage locations in the system controller. After the data in the system controller has been flushed, the service processor moves the data from the cache memory into the mainstore. This prevents data moved out of the cache in the mainstore from being overwritten by move outs which were pending in the system controller at the time that the CPU was stopped.

A fast tag cache is an array to cache a limited set of identifiers specifying the residency and access rights to memory blocks and cache blocks contained in a node within a distributed memory system built using a cache coherent non-uniform memory access architecture. The purpose of the fast tag array is to ensure peak processor-memory bus throughput each node and minimize the amount of memory required to hold cache state information.

The bandwidth of the data transfer among a main memory and snoopy caches is improved by solving the bus bottleneck in a multiprocessor system using a snoopy cache technique. Shared bus coupling is employed for an address/command bus requiring bus snoop whereas multiple data paths coupled by an interconnection network are used for the data bus not requiring bus snoop. The multiple data paths reflect the order of the snoopy operations on the order of data transfer such as to maintain data consistency among the caches.

A predictive arbitration system for interfacing a plurality of peripheral component interconnect (PCI) agents coupled to a first PCI bus with a second PCI bus. In one embodiment, the present predictive arbitration system includes a first PCI bus adapted to transmit data signals. A plurality of PCI agents are coupled to the first PCI bus. A predictive arbiter is coupled to both the first PCI bus and a second PCI bus. The predictive arbiter is also coupled to the plurality of PCI agents. The predictive arbiter is configured to receive requests for access to the first or second PCI bus from any of the plurality of PCI agents. The predictive arbiter, upon receiving requests for access, transmits one of the requests to a second arbiter coupled to the second PCI bus, wherein the selected and transmitted request originates from a selected one of the plurality of PCI agents. The predictive arbiter is also adapted to receive a grant signal from the second arbiter in response to the selected and transmitted request. The predictive arbiter further comprises a predictive arbitration system for enabling a grant line coupled to the selected one of the plurality of PCI agents before the grant signal is received from the second arbiter.