A 2/N mode clock generator that generates bus clock signals through the use of bus clock enable signals selecting bus clock pulses that are in phase and out of phase with a core clock signal. The clock generator maintains synchronization between the bus clock signal and the core clock signal so that they are always in a predetermined phase relationship.

This is a PLL frequency synthesizer having a reference divider for dividing a reference source signal, and an RF divider for dividing the output of a voltage controlled oscillator, wherein when changing over the frequency, first the division value of the RF divider changes periodically to become a fractional division value in average, and after the frequency is nearly changed over, the RF divider is set in a conventional integer division operation, therefore, the frequency can be changed over at high speed by the fractional division operation high in reference frequency, and after the changing, a low spurious signal characteristic may be realized.

An apparatus for adjusting bandwidth for a receiver includes: (a) a receiver clock operating according to receiver clock parameters related to received signals for sampling received signals; (b) a local clock; (c) a tracker receiving an indicator related to the receiver clock parameter and generating a tracking parameter for comparing the receiver clock parameter and periodicity of the local clock; (d) a counter for counting events associated with the tracking parameter and generating an event count relating to the received signals; (e) a decision unit for reckoning the event count and generate a decision parameter relating to the reckoning; and (f) output logic coupled with the decision unit, the tracker and the receiver clock for evaluating the decision parameter and the tracking parameter by a logical routine for determining a need for changing operation of the receiver clock and for generating a change signal when the need exists.

A method and an apparatus relating to a fine frequency synchronization compensating for a carrier frequency deviation from an oscillator frequency in a multi-carrier demodulation system of the type capable of carrying out a differential phase decoding of multi-carrier modulated signals, the signals comprising a plurality of symbols, each symbol being defined by phase differences between simultaneous carriers having different frequencies. A phase difference between phases of the same carrier in different symbols is determined. Thereafter, a frequency offset is determined by eliminating phase shift uncertainties related to the transmitted information from the phase difference making use of a M-PSK decision device. Finally, a feedback correction of the carrier frequency deviation is performed based on the determined frequency offset. Alternatively, an averaged frequency offset can be determined by averaging determined frequency offsets of a plurality of carriers. Then, the feedback correction of the frequency deviation is performed based on the averaged frequency offset.

An apparatus for and method of generating a clock signal having a desired frequency that is derived from a clock source having any arbitrary,frequency. The mechanism of the present invention generates an average rate, very close to the optimal rate desired, by `swallowing` or absorbing clock cycles of the available frequency source. Precise timing is achieved by adding correcting time intervals, which are based on counting pulses from the higher rate clock source. The clock frequency generator comprises a standby mode state machine and a jitter calculation processor. Timing calculations are performed by the jitter calculation processor and the standby mode state machine functions to generate the desired standby mode clock frequency. The state machine utilizes counters to track the number of cycles of the available clock and the number of generated cycles of the standby clock.