A DRAM comprising a silicon substrate with a field oxide layer 2, gate oxide layer 3, gate electrode and gate electrode lines 4A, 4B, oxide spacers 5 and drain and source electrodes on the silicon substrate 1 to define a MOSFET 25 is disclosed. A first insulating layer 7 covers the MOSFET 25 except for a portion of said source electrode 6B. A charge storage electrode 11A, with at least one tunnel space 9B having walls formed therein, overlies the source electrode 6B and is in electrical contact with the source electrode 6B. A capacitive dielectric layer 13 covers the charge storage electrode 11A and the walls 9C of each the tunnel space 9B. A plate electrode 14A is formed on the capacitive dielectric layer 13 and covers the charge storage electrode 11A and on the walls of each tunnel space 9B to define a stack capacitor having an increased area for the charge storage electrode 11A which results in an increased capacitance of the stack capacitor. A third insulating layer 15 covers at least the plate electrode 14A, except for a portion of the drain electrode 6A; and a bit line electrode 17 formed on the third insulating layer 15 is electrically connected to the drain of the MOSFET. A method of manufacturing the DRAM having at least one tunnel plate electrode is also disclosed.
There is disclosed a method for fabricating a capacitor of semiconductor memory device, capable of securing an electrostatic capacity useful to high integration of semiconductor device. In accordance with the method, a contact pad, a first polysilicon film, a second polysilicon film and a third polysilicon film are utilized as a charge storage electrode, so that the charge storage electrode's surface area comes to be enlarged, bringing about increasing the capacity. In addition, a plate electrode is made by forming an empty region within the charge storage electrode, so that the resulting charge storage electrode can be maximized in capacity by the method. Consequently, a highly integrated DRAM cell can be fabricated and the memory device reliability can be improved, in accordnce with the present invention.
A process for production of a stacked capacitor of a semiconductor device. This process achieves security of a sufficient capacitance of the capacitor of the semiconductor device having a high integration degree as well as a desired reliability of the semiconductor device. In accordance with this process, first and second mask polysilicon layers, which are used in opening of a storage node contact, are used in forming of a contact and also used as conductive layers for charge storage electrodes. The process of this invention provides the capacitor of the semiconductor device with a larger storage node capacitance in a relatively smaller cell area, using the characteristic of a higher etching selection ratio (about 30:1) of an oxide layer to a polysilicon layer and of a higher etching selection ratio (not less than 30:1) of the polysilicon layer to a nitride layer.
A charge storage electrode structure and the manufacturing method therefor. The present invention features forming two oxide patterns having viscous property at certain temperatures on a barrier layer as rectangular bar-shaped patterns and applying heat to two oxide patterns to transform the two oxide patterns to cylindrical oxide patterns; depositing polysilicon layer on the cylindrical oxide patterns; etching each end of the portions of the polysilicon layer and removing the two oxide patterns; so as to provide a charge storage electrode structure having at least two conduits which is formed with a polysilicon. The charge storage electrode structure according to the present invention has an increased effective surface area and is manufactured by a relatively simple method facilitating the manufacture of highly integrated semiconductor device.
Semiconductor memory device and method for fabricating the same for increasing the capacity of a capacitor by minimizing the capacitor area lost for a storage contact. The method includes steps of forming a transistor on a semiconductor substrate, forming a first insulation film over the entire surface of the substrate having the transistor formed thereon, forming a contact region exposing a designated part of the substrate by subjecting the first insulation film to a selective etching for forming a storage node contact, forming a first conductive layer, a second insulation film, and a second conductive layer successively over the entire surface of the substrate, forming a first mask pattern on the second conductive layer within the contact region spaces for a certain distance from the first insulation film pattern at least in one direction, subjecting the second conductive layer to an etching with the first mask pattern as a mask, forming a second mask pattern for forming a storage node contact on the second insulation film and the second conductive layer, subjecting the second insulation film with the second mask pattern as a mask, and forming a third conductive layer over the entire surface of the substrate so as to connect the first conductive layer and the second conductive layer.
This invention relates to a semiconductor memory having stacked storage node, which comprises a semiconductor substrate, a memory cell transistor having gate pole and source and drain area formed on the semiconductor substrate, a capacitor storage node having an insulation film formed over the memory cell having a contact hole exposing a certain part of the source and drain area of the memory cell transistor, and a conductive side wall formed on the insulation film of the edge part on the upper part of the contact hole, multi-layer conductive stacked films horizontally extended to outer side of the contact hole and connected with one side of the conductive side wall, and an upper conduction layer formed along the inside surface of the contact hole and the conductive side wall to be connected to the source and drain of the transistor.
