A frame rate conversion system synchronizes data transfers to and from a VRAM frame buffer which are concurrent, continuous, and asynchronous. The system comprises a frame buffer having a split memory for communicating data to a split output shift register. A frame buffer control supervises writing operations to the split memory at a first frame rate. A display control supervises reading operations from the shift register at a second frame rate which is slower than the first frame rate. The frame buffer control and the display control communicate control signals through double synchronizers. The display control has a counter for counting frames of data which have been read from the VRAM frame buffer. The display control prevents the writing of a frame into the split memory after a particular number of frames has been counted so as to prevent the frame buffer control from writing over and destroying existing data which has not yet been read from the split memory by the display control. Moreover, the display control synchronizes the writing and reading operations by the frame buffer control and the display control, respectively, each time that a frame has been skipped. Furthermore, the frame buffer control causes the VRAM frame buffer to transfer data from the split memory to the shift register when the horizontal blank is deasserted within the incoming analog video signal.

An architecture for a memory with a wide word, e.g. n-byte, width particularly suited for use as a high definition video frame store memory (80), and an accompanying organization for storing pixel data therein to facilitate efficient block and raster access therefrom. Specifically, the memory relies on storing n-byte wide words (n=(m.sub.1 .times.m.sub.2)) across m.sub.2 independent m.sub.1 -byte wide memory segments, with pre-defined positional offsets between respective m.sub.1 -byte words (203)("nibbles") stored in successive memory segments. All these segments are simultaneously accessed on a read or write basis. During a memory write operation, all the nibbles in an n-byte wide input word are appropriately shuffled to yield the proper inter-segment offsets prior to being written into the memory as a collective n-byte memory write word. During a read operation, all the nibbles read from memory in a collective n-byte memory read word are appropriately shuffled to yield an n-byte output word. Inasmuch as either a scan line or sub-block (210.sub.W, 210.sub.X, 210.sub.Y, 210.sub.Z) of a macroblock of pixel data is collectively written to or read from the memory during one memory write or read operation, with shuffling occurring on a pipelined basis therewith, each of these two widely differing forms of memory access can each occur at a very high efficiency and hence at essentially full memory bandwidth. This permits that memory to be fabricated from relatively inexpensive memory circuits.

A system for performing interlace scanning with plural light beams. The system includes a data source for supplying sequential lines of image data and a memory device for sequentially storing a plurality of the lines of image data, where the memory device has an input port for receiving the lines of image data from the data source. The memory device also has plural output ports where each of the plural output ports corresponds with one of the plural light beams. The system further includes addressing circuitry for addressing the memory device, where the addressing circuitry provides plural sets of slowscan output address signals corresponding to the plural output ports for providing an address value. The address value of each of the slowscan output address signals are offset from other of the address values by an offset amount provided by the addressing circuitry to enable interlacing of the plural light beams.

A linear address organization for physically storing mip maps and rip maps in memory is disclosed. The subsampled data arrays of the mip maps and rip maps are sequentially stored in continuous subsequences of a continuous sequence of memory addresses. The subsequences of addresses are assigned in order of level of subsampling of the data arrays which make up the mip map or rip map. In the case of a mip map, the subsequences are assigned to the data arrays in order of increasing level of subsampling. In the case of rip maps, the data arrays are segregated into groups according to a first one of the two subsampling directions, such that each array in a particular group has the same level of subsampling in the first direction. Subsequences are assigned to each group of data arrays. The addresses of the subsequences are assigned within each group on a span by span basis where a span includes the texture data in a particular direction of each data array in order of increasing level in the second one of the two subsampling directions. Address generators are also disclosed for assisting in generating linear addresses to texture data with specific coordinates (u,v) in arrays having particular levels of subsampling.

A process and apparatus are disclosed for obtaining a texture color value C.sub.r for an object surface point from two texture color values C.sub.ri and C.sub.rj (which themselves may be interpolated texture color values), of texture data points C.sub.i and C.sub.j, respectively. The object surface point is a distance W from the texture data point C.sub.i and a distance 1-W from the object surface point C.sub.j, where W is an n-bit value. The process includes the steps of multiplying each of the texture colors C.sub.ri and C.sub.rj by each integer from 0 to 2.sup.n-1 to produce 2.sup.n -1 products for each color. The product of C.sub.ri with 2.sup.n-1 -W' and the product of C.sub.rj with W' are selected from these produced products, where W' is the rounded product of W and 2.sup.n-1. The two selected products are added together to produce the sum (2.sup.n-1 -W').multidot.C.sub.ri +W'.multidot.C.sub.rj, and the sum thus produced is divided by 2.sup.n-1 to produce the interpolated color. The apparatus for producing the interpolated color uses integer arithmetic for producing the texture color and can operate in a pipelined fashion.