A partitioned boundary-scan interconnect test method for loaded printed wiring boards (PWB's) is disclosed which reduces testing-induced damage to electronic components. The method is adapted to expeditiously identify all short-circuits on a PWB. The partitioned boundary-scan interconnect test includes four sub-tests. A powered shorts boundary-scan sub-test searches for short-circuit faults between conventional nets and boundary-scan nets. A boundary-scan interconnect shorts sub-test searches for short-circuits between boundary-scan nets. The boundary-scan interconnect shorts sub-test is optimized by testing a single driver on each net. All other drivers are tested during a boundary-scan bus-wire sub-test. A boundary-scan in-circuit sub-test checks the connectivity of boundary-scan devices in partial boundary-scan nets (i.e., nets having a driver or receiver but not both). By partitioning the boundary-scan interconnect test into these sub-tests, the potential for testing-induced damage is reduced.
A boundary scan cell including a three-state output buffer, a test data scan flip-flop for providing an input to the three-state buffer, a control data scan flip-flop for receiving a serial control data input, independent clock signals for independently clocking the test data scan flip-flop and the control data scan flip-flop, and control circuitry for controllably providing the output of the control data scan flip-flop to the three-state output driver such that the enabled state of the three-state output buffer is controlled by the output of the control data scan flip-flop, whereby the enabled state of the three-state output driver is controlled independently of the test data in the test data scan flip-flop.
The invention provides a fault diagnosis apparatus which estimates a disconnection fault site intermediate of a branch wiring line in an LSI based on a result of an LSI test performed by using a test pattern. An indefinite value simulation narrowing down section uses a test pattern to perform, for each gate included in a suspected fault gate set, a simulation wherein the output value of the gate is set to an indefinite value, and removes any gate from which a definite value is outputted among those outputs which have been determined to be errors with error test patterns. An output value check narrowing down section removes any gate from the suspected fault gate set if the gate satisfies a condition that the output value thereof at least in one error test pattern is different from that in the other error test patterns. Finally, a branch destination fault simulation narrowing down section defines 0/1 stuck-at faults to output branch designations of each gate included in the suspected fault gate set and performs a logic simulation using the test pattern. Then, the branch destination fault simulation narrowing down section removes any gate from the suspected fault gate set if the gate does not have an output branch destination fault which is not detected at a normal output but is detected at an error output.
A method for testing a test architecture in a circuit is accomplished by receiving or generating, based on the topology information for the circuit, a Boundary Scan Description Language (BSDL) description of the test architecture which is then verified for correct syntax, consistency, and standard compliance. Next, one or more tests are selected from a predetermined set of test methodologies, based on the type of testing to be performed. Self-checking test parameters are generated based on the BSDL description and the selected tests. Using these test parameters, a logic simulation algorithm tests the test architecture of the circuit and generates a report detailing any errors that are discovered.
A complementary boundary-scan cell arrangement includes a plurality of system input terminals supplied with signals from the system side, a corresponding number of scan input terminals, a corresponding number of registers supplied with signals inputted to the system input terminals or the scan input terminals and adapted for holding them, a corresponding number of system output terminals supplied with the signals held by the registers and adapted for outputting them to the system side, and a corresponding number of scan output terminals supplied with the signals held by the registers and adapted for outputting them for scan. This complementary boundary-scan cell arrangement further includes a corresponding number of first to fourth multiplexers. The first and second multiplexers to permit switching the connection relationships between the respective input terminals and the registers. The third and fourth multiplexers to permit switching the connection relationships between the registers and the respective output terminals.
A system that restricts the damaging effects of software faults that interact with test and configuration circuitry. This test and configuration circuitry includes a scan chain in the form of a serial linkage between memory elements within a circuit, thereby allowing a test input to be serially shifted into the memory elements. The system operates by receiving a test disable signal at the circuit. In response to the test disable signal, the system moves the circuit into a test disable mode, which limits any damaging effects to the circuit caused by shifting the test input into the memory elements in the scan chain. Next, the system shifts the test input into the memory elements in the scan chain. T he system also determines whether the test input will cause damage to the circuit after the test input is completely shifted into the scan chain. If so, the system holds the circuit in the test disable mode so that the test input cannot damage the circuit. If not, the system moves the circuit out of test disable mode, and runs the circuit for at least one clock cycle in order to test the circuit.
