An integrator circuit is connected to a capacitor that is to be measured and the capacitor driven by a read pulse. A first switch grounds the integrator input between read pulses and a second switch applies a bias input to the integrator. The bias is selected so that the integrator is active and its output high. Then, during the read pulse interval, the integrator will hold its input close to ground so that the capacitor to be measured will transfer a maximum charge to the integrator feedback capacitor. Additionally, the stray capacitance at the integrator input has little effect and the output will be a strong function of the value of the capacitor to be measured. The circuit has application in capacitor measurement and is useful as a ferroelectric memory preamplifier which acts to amplify the difference in capacitance produced by the polarization state of a ferroelectric memory capacitor. A CMOS preferred embodiment is disclosed in the form of a memory sense preamplifier.
A ferroelectric memory device and method for reading such a device utilize capacitive coupling between a reference circuit and a sense amplifier. The amount of sneak charge canceled from a data bit line depends on the relative capacitances of a coupling capacitor and another capacitor used to integrate sneak charge from a reference bit line. The use of linear-responding components improves stability.
A data holding device is provided that is capable of holding data even if the power supply is shut off and reliability in holding data is high. The data holding device 1 is provided with a data latch circuit 3 and a ferroelectric memory section 5. Ferroelectric capacitors 17 and 19 are capable of storing data in non-volatile manner. One end of the ferroelectric capacitor 17 is connected to the input node 7a of an inverter circuit 7 through a transfer gate 11. The transfer gate 11 is in the off state when data are passed. Therefore, even if input data D changes when data are passed, the change is quickly transmitted to the input node 7a, so that reliability of latching operation does not lower even if the operation is made at usual speeds.
A semiconductor memory device capable of suppressing size increase and reducing the operating time is provided. This semiconductor memory device comprises storage portion, connected to a data read line, containing a material having a hysteresis property and data read portion connected to the data read line for reading data stored in the storage portion, for supplying prescribed energy capable of changing a storage state of the storage portion from an initial state supplying no prescribed energy and thereafter returning the intensity of the energy to a level not changing the storage state for reading the data with the data read portion on the basis of the current state of the data read line and the state of the data read line in the initial state in data reading.
A device and method of reading a ferroelectric memory, including providing a ferroelectric memory including a ferroelectric memory cell, a charge integrator, and a bit line connecting the ferroelectric memory cell and the charge integrator. Pulses are applied to the ferroelectric memory cell, where each of the pulses are of a value lower than that which will destroy data stored in the memory cell. Output voltage values from the ferroelectric memory cell are accumulated by the charge integrator in response to each pulse. The output of the charge integrator may be read to determine whether the datum value stored in the memory cell is a logic high or low value. In one embodiment, the output of the charge integrator is read at a predetermined time after starting the pulses.
A circuit configuration for reading a ferroelectric memory cell which has a ferroelectric capacitor is described. The memory cell is connected to a bit line. The circuit configuration provides a differential amplifier having a first differential amplifier input, a second differential amplifier input and a differential amplifier output. The first differential amplifier input is connected to the bit line, and the second differential amplifier input is connected to a reference signal. A first driver input of a first driver circuit is connected to the differential amplifier output, and a first driver output is connected to the bit line. The differential amplifier is fed back through the first driver circuit and regulates the bit line voltage to the voltage value of the reference signal.
