A self-routing crossbar switch interconnects a plurality of processors with a plurality of memory modules. In a self-routing crossbar switch connecting N processors and N memory modules, a processor is connected to each input port and a memory module is connected to each output port; each of the N processors can transmit a memory request simultaneously provided that there is no port contention and no bank contention. Port contention occurs if two or more processors attempt to access the same output port of the self-routing crossbar switch at the same time. The memory module consists of several memory banks that are connected in an interleaved manner. If the memory bank is accessed before it is ready to accept a new request, bank contention is said to have occurred. In the self-routing crossbar switch the requests directed to a port are first passed through an aligner and a conflict resolution logic. There is one aligner associated with each output port. The aligner inputs the requests directed at an output port and aligns them so that, at the output of the aligner, all the active requests appear in a consecutive fashion. The conflict resolution logic resolves the port and bank contention.

An invention is provided for a reactive placement controller for interfacing with a banked memory storage. The reactive placement controller includes a read/write module, which is coupled to a command control module for a banked memory device. A command queue is included that comprises a plurality of queue entries coupled in series, with a top queue entry coupled to the read/write module. Each queue entry is capable of storing a memory command. Each queue entry includes its own queue control logic that functions to control storage of new memory commands into the command queue to reduce latency of commands in the command queue.

An improved memory controller is disclosed for accessing a computer memory, which consists of a plurality of banks of page mode memory cells and is connected to a CPU via a split transaction bus with out-of-order completion capability. The improved memory controller comprises: (a) a unified command queue for receiving a memory access command; (b) a plurality of command queues equalling in number to the number of the memory banks; (c) a dispatch logic for dispatching the memory access command into one of the command queues in accordance with which memory bank the access command is to access; (d) a selection logic for selecting one of the command queues as an active command queue to execute a command, wherein all the non-selected command queues are placed on a standby status as standby command queues; and (e) switching logic provided in the selection logic for switching the command execution from the active command queue to a standby command queue, which is made active according to a predetermined criterion, when a page miss is detected or when the active command queue is empty. The switching logic also causes one of the standby command queues to perform a row address selection when the active command queue is accessing said computer memory. With the improved memory controller, penalties associated with row miss and/or page miss are eliminated. As a result, the average memory access latency is minimized and overall memory utilization efficiency is enhanced.

A queuing architecture within a RAID controller that manages a multi-threaded SCSI environment. The architecture resides within a RAID controller that communicates with a plurality of independent, SCSI disk drives (or other storage elements). The RAID controller accepts disk I/O requests from one or more host computers. The architecture dynamically allocates multiple disk I/O requests to various request queues until the disk drive that will handle the request is available for access. Multiple requests are executed in parallel on various ones of the disk drives.