A cache memory structure comprises a cache memory that has a plurality of ports for reading data from the cache memory and a plurality of ports for writing data into the cache memory. A switching network matrix having controllable switch elements for connecting of the cache memory ports to bus terminals is arranged between the bus terminals and processors, to an instruction unit of a processor, to a main memory, and to the cache memory. The switch elements of the switching network matrix are controlled by a cache memory controller such that the bus terminals can be selectively connected to the write or read ports of the cache memory. With the assistance of the switching network matrix, it becomes possible to select the number of ports of the cache memory to be less than the plurality of bus terminals that access the cache memory.
A data processing arrangement comprises a plurality of processors. These processors share a collective memory. The arrangement comprises private buses. A private bus enables data communication exclusively between a processor and the collective memory. A memory interface provides access to the collective memory in data bursts while it produces substantially steady data streams on the private buses.
A data processing system is disclosed utilizing a microprogram memory controller wherein the memory controller may be altered and/or upgraded to accommodate variations in memory systems while maintaining a compatible system-level interface. The memory controller includes a microprogram engine and a resident microprogram stored within nonvolatile memory coupled to the microprogram engine wherein the microprogram engine may utilize the resident microprogram to manage, configure and determine operational modes for a memory subsystem. A variable microprogram may also be loaded within Random Access Memory associated with the microprogram engine and utilized to extend or enhance the operation of the memory controller. The memory controller also preferably utilizes a control interface for providing an interface between the memory controller and the processor, which may be utilized to control the loading of the variable microprogram into the memory controller from an external source.
A virtual triple ported cache operates as a true triple ported array by using a pipelined array design. Multiple execution units can access the cache during the same cycle that the cache is updated from a main memory. The pipelined features of the cache allow for three separate sequential operations to occur within a single cycle, and thus give the appearance of a virtual triple ported array. This virtual triple port array architecture contains a data interface for dual execution units, which allows both units to access the same data array location. The array architecture allows for back-to-back read accesses occurring within a half cycle. The array architecture provides a bypassing function around the array for a write occurring on one port to the same address that a read is occurring on the other port. To allow for simultaneous cache reloads during execution unit access, a late write is done at the end of the cycle.
A shared cache in a computer system for caching both system memory information and alternative memory information. The present invention includes cache management logic, a cache memory with a plurality of cache lines and a and a cache tag memory. The cache tag memory comprises an address field and status bits for indicating a status of corresponding information in cache memory. The status bits, when interpreted as a group, indicate the status of the corresponding information in cache memory as well as whether the information in the corresponding cache line is related to the alternative memory or the system memory.
A method is described for buffering data transfers between components within a computer system. The method uses a buffer pool and translation table to translate virtual address pointers from calling computer components into physical address pointers within a line buffer array. The virtual address pointers are then held in a translation entry table that correlates the virtual and physical pointers.
