A set-associative cache-management method utilizes both parallel reads and single-cycle single-set reads. The parallel reads involve accessing data from all cache sets in parallel before a tag match is determined. Once a tag match is determined, it is used to select the one of the accessed cache memory locations to be coupled to the processor for the read operation. Single-cycle single-set reads occur when the line address of one read operation matches the line address of a immediately preceding read operation satisfied from the cache. In such a case, only the set from which the previous read request was satisfied is accessed in the present read operation. If a sequential read operation is indicated, the same-set can also be accessed to the exclusion of the other sets provided the requested address does not correspond to the beginning of a line address. (In that case, the sequential read crosses a cache-line boundary.) However, the invention further provides for comparing the tag at the same-set location with the successor index with the tag associated with a location from which a read request was satisfied. If the next read request matches the common tag and the index of the successor location, a single-set read is also used. The single-set reads save power relative to the parallel reads, while maintaining the speed advantages of the parallel reads over serial "tag-then-data" reads.

A set-associative cache-management method utilizes both parallel reads and single-cycle single-set reads. The parallel reads involve accessing data from all cache sets in parallel before a tag match is determined. Once a tag match is determined, it is used to select the one of the accessed cache memory locations to be coupled to the processor for the read operation. Single-cycle single-set reads occur when the line address of one read operation matches the line address of an immediately preceding read operation satisfied from the cache. In such a case, only the set from which the previous read request was satisfied is accessed in the present read operation. The single-set reads save power relative to the parallel reads, while maintaining the speed advantages of the parallel reads over serial "tag-then-data" reads.

A computer system including a central processing unit, a system input/output bus, an input/output device, and an input/output control unit joined to the system input/output bus for translating addresses on the system input/output bus to physical input/output device addresses.

A cache memory device including an input/output (ESRQ) for receiving a request (REQ) having a main address (AP) and optional data (D); an input/output (ESMP) to an addressable main memory (MP) or another addressable cache memory; a plurality of X memory banks (BCi) wherein i is lower than X and higher than 0, each having a number Li of lines for containing data, the lines being individually designated by a local address (AL) in each bank; an arrangement for answering a request (REQ) by connecting the main address (AP) in the request to a local address (AL) in the bank (BCi) in accordance with a predetermined la (fi) for each bank (BCi), whereby the line thus designated in the bank (BCi) is the only line to contain the datum referred to by the main address; and an arrangement (CHA) for loading the cache memory according to the received requests. At least two predetermined laws (fi) are substantially distinct depending on the banks in question, and the two banks in question are addressed separately, hereby the average cache memory data access hit rate is improved.

A local bus subtractive decode device that improves the speed of its subtractive decoding by storing or caching subtractively decoded addresses. At the start of subsequent address cycles, this cached subtractive decode device compares the address and command on the local bus with the stored addresses and commands, and if it finds a match, claims the transaction as would a positive decode device. It can do so without conflict because no positive decode device will be claiming the transaction.