A method and process for providing a memory dump of less than the entire contents of memory is provided. The memory locations to be dumped are selected on the basis of recency of use, so that there is a high probability that portions of memory needed for analysis or evaluation of the computer system will be included in the selective dump. Preferably, the select ion is made on the basis of information or hardware which is already provided in the computer system. In one preferred embodiment, memory to be dumped is selected on the basis of memory locations encoded for by a translation lookaside buffer.
In a computer system including a processor and a memory, a fast memory dump is conducted upon receiving an indication that the processor requires reloading. The fast memory dump is conducted by initially dumping a portion of the memory, then reloading the processor, and then conducting a post-reload dump of the remainder of the memory after reloading of the processor has commenced. As the post-reload dump continues, the remainder of the memory is gradually released for processor usage. This permits the processor to return as a resource more quickly than would be the case if a full memory dump was conducted before reloading the processor.
A structure and method for translating address buffer coordinates for a device under test having two or more similar repeatable units. The method comprises identifying a repeatable unit of the repeatable units, preparing a look up table for translating buffer coordinates of a reference unit of the repeatable units and displacing information from the look up table to correspond to the repeatable units.
The present invention relates to a method and apparatus for dumping memory. More particularly a computer-implemented method of saving at least some data within volatile storage to non-volatile storage when a computer system panics is described. The method includes the steps of: the computer system defining a specified portion of volatile storage (1) containing data to be saved as a dump device (2), rebooting (8) the computer system without affecting the data within the dump device, and the computer system copying (12) the data in the dump device to non-volatile storage (13). A reboot of the computer system after copying the data to non-volatile storage is not necessary for the computer system to begin (14) normal operation.
Disclosed is a printer which will carry out initialization or rewriting of data in a non-volatile memory in response to a control command sent from a host machine, and execute printer initialization, based on the initialized or rewritten data, by a control command sent from the host machine. Unlike the prior arts, therefore, it is possible to perform initialization of the printer based on the initialized or rewritten data, without involving a troublesome switching operation and without requiring an operation of powering off and then on the printer or resetting the host machine. A printer according to another aspect of this invention is designed to print out data in the non-volatile memory in response to a control command sent from the host machine. It is therefore possible to print out the contents of the non-volatile memory for confirmation without involving a troublesome switching operation in this case too. Further, if the structure of the second aspect is added to the structure of the first aspect, it is possible to easily check if the data in the non-volatile memory has been surely initialized or has been correctly rewritten.
A computing system has multiple instruction pipelines, wherein one or more pipelines require translating virtual addresses to real addresses. A TLB is provided for each pipeline requiring address translation services, and an adress translator is provided for each such pipeline for translating a virtual address recieved from its associated pipeline into corresponding real addresses. Each address translator comprises a translation buffer accessing circuit for accessing the TLB, a translation indicating circuit for indicating whether translation data for the virtual address is stored in the translation buffer, and an update control circuit for activating the direct address translation circuit when the translation data for the virtual address is not stored in the TLB. The update control circuit also stores the translation data retrieved from the main memory into the TLB. If it is desired to have the same translation information available for all the pipelines in a group, then the update control circuit also updates all the other TLB's in the group.
