Disclosed is a synchronous type flip-flop circuit of a semiconductor device including a first clock buffer unit for buffering a complement signal of a data signal input at a first potential level of a clock signal. A second clock buffer unit buffers a complement signal of a signal output from the first clock buffer unit at the first potential level of the clock signal. A precharge latch unit precharges a first node and a second node with a supply voltage at the first potential level of the clock signal, differentially amplifying respective potentials of the first and second nodes by output signals from the first and second clock buffer units at a second potential level of the clock signal, and outputting the amplified signals while latching the amplified signals. The synchronous type flip-flop circuit of the present invention has no requirement to take into consideration problems associated with a transistor ratio. This enables a reduced circuit area and an increased operating speed.

A remote delay regulator circuit measures the effects of intrinsic propagation delays experienced by a system clock signal propagating through an extended clock distribution path that encompasses a clock repeater chip, a module transmission network and a clock distribution network of an integrated circuit (IC) chip associated with a clock repeater chip. Circuits of the remote delay regulator are contained on the repeater chip and on the associated IC chip. Delay measurement of the remote IC clock distribution network is provided by sensing the clock signal at the beginning of the network using a BEFORE sense tap and at the end of the network using an AFTER sense tap. The BEFORE and AFTER sense taps are routed to a signal generation circuit on the repeater chip where measurement signals are generated that define the beginning and end of a measurement cycle. A clock delay path circuit on the repeater chip contains the logic circuitry required to measure and compensate for the intrinsic propagation delays of the repeater chip, the transmission network and the IC chip. The logic circuitry includes a measurement latch circuit and a measurement delay line having tapped outputs coupled to the latch circuit.

An internal clock pulse CKH is inputted via a delay circuit to the forward delay section FD of a synchronous adjustable delay circuit. An internal clock CK' is inputted as a control clock pulse to the synchronous adjustable delay circuit. The forward delay section FD of the synchronous adjustable delay circuit includes delay stages and delays a pulse FCL' for a time of .DELTA. equivalent to the time elapsed until the internal clock pulse CK' in the next cycle rises. The backward delay section HBD of the synchronous adjustable delay circuit including delay stages delays the internal clock CK' for a delay equivalent to a time of .DELTA./2. The output HCLQ of the backward delay section HBD is outputted as an internal clock pulse CKQ via another delay circuit.

A method and apparatus is disclosed for use in an implantable device that communicates with an external device through pulse position modulation. A timing generator is provided as part of the implantable device that determines the phase uncertainty between an external signal and an internal cock signal. The phase uncertainty then is added to the preset delay period to more precisely control the position of the response. The phase uncertainty is measured by a dual slope circuit that varies a state variable (which can be a digital timer, a capacitor voltage, or the like) at a fixed rate with either a positive or negative slope. When the external signal is detected, the stat variable is reset and then decreased at a fixed rate until the next positive edge of the clock signal. The state variable then is increased at the same rate until the subsequent positive clock edge. The resulting variable value is proportional to the phase uncertainty. When the delay timer reaches zero, the state variable is again decreased at the same fixed rate until the initial value is reached, at which the output response is generated.

A method and means for selectively stopping the internal clock of a microprocessor on any of 16 phases using functional components which include: a clock multiplier circuit, that receives a clock signal input from an external oscillator or other appropriate source, and outputs the internal clock signal for the microprocessor; control logic circuitry for processing and inputting stop signals to the clock multiplier; and a clock special purpose register, which provides control signals to the control logic circuitry to determine when stopping of the internal clock signal should occur.