An equalization and precharge circuit precharges and equalizes local input/output (LIO) signal lines between each memory access operation within a memory circuit. The equalization and precharge circuit includes a local voltage circuit which maintains the level of the LIO signal lines at a standby voltage level during standby periods. Preferably, the standby voltage level is approximately equal to half of the supply voltage VCC. Separate precharge and equalization circuits are included to precharge and equalize the LIO signal lines between memory access operations. During precharge periods, a precharge control signal LIOPC is preferably at a logical high voltage level for a predetermined period of time between memory access operations, thereby forming a fixed-width pulse and raising the LIO signals to a known precharge level. The LIO signal lines are charged to a known level equal to the standby voltage level plus a voltage V(t) during the precharge and equalization period. The voltage V(t) is dependent on the duration of the fixed-width pulse of the precharge control signal LIOPC.

A memory device design is provided. The memory device includes a memory core having a depth that defines a plurality of words, and a word width that is defined by multiple pairs of a global bitline and a global complementary bitline. The memory device further includes a core cell having a bitline and a complementary bitline, and a flipped core cell that has a flipped bitline and a flipped complementary bitline. The multiple pairs of the global bitline and the global complementary bitline have a plurality of core cells that are defined by alternating ones of the core cell and the flipped core.

A method of designing a memory device that has substantially reduced bitline voltage offsets is provided. The method includes providing a memory core having a depth that defines a plurality of words, and a word width that is defined by multiple pairs of a global bitline and a global complementary bitline. The method also includes designing a core cell having a bitline and a complementary bitline, and designing a flipped core cell that has a flipped bitline and a flipped complementary bitline. Further, the method includes arranging a core cell followed by a flipped core cell along each of the multiple pairs of the global bitline and the global complementary bitline. Preferably, the bitline of the core cell is coupled with the flipped complementary bitline of the flipped core cell, and the complementary bitline of the core cell is coupled to the flipped bitline of the flipped core cell.