A preformed planar structure is interposed between the chip(s) and the substrate in a flip-chip structure, and establishes a minimum gap between the chip(s) and the substrate. Liquid flux may be applied to the preformed planar structure in order that flux is selectively applied to the solder balls (pads) on the chip and the substrate. The preformed planar structure may be provided with through holes in registration with the solder balls on the chip(s) and the substrate. In this case, liquid flux selectively fills the through holes for delivery to the solder balls during soldering. The through holes also aid in maintaining registration of the chip(s) and the substrate. The through holes may be sized to establish a predetermined mechanical structure of solder joints formed by the solder balls when fused together. The preformed planar structure has a planar core and opposing planar faces. The core is formed of thermosetting organic resin, such as polyimide, or non-organic material such as alumina, polished sapphire, beryllium oxide, aluminum nitride or aluminum. The planar faces of the preformed planar structure are formed of thermoplastic resin or thermosetting material, such as polyacetal, epoxide resin or polystyrene. The preformed planar structure tends to draw the chip(s) together to the substrate, establishing a flip-chip structure of mechanical integrity. The preformed planar structure has a thickness of 5-50 microns, preferably on the order of 20-30 microns. Method and apparatus are disclosed.
CROSS REFERENCE TO RELATED APPLICATIONS
This is a division of copending, commonly-owned U.S. patent application Ser. No. 07/775,009, filed Oct. 11, 1991, now U.S. Pat. No. 5,168,346, which is a division of U.S. patent application Ser. No. 07/576,182 filed Aug. 30, 1990, now U.S. Pat. No. 5,111,279, which is a continuation of U.S. patent application Ser. No. 07/400,572 filed Aug. 28, 1989, now abandoned.
A method of forming a bond structure for use with integrated circuits and semiconductor electronics and carrier assemblies is disclosed. Metallurgical paste is screen printed through a stencil and the stencil is left in place during the reflow process. The melting point of the bond structure and the metallurgical paste is lower than the melting point of interconnects on the electronic components and less than the decomposition temperature of the carrier assemblies to which the electronic components are bonded.
A flip-chip structure and method connects a semiconductor chip (11) having conductive bumps (16) to a substrate (12) having vias (19) extending from a first side (21) to a second side (18) of the substrate (12). A filler material (22) is deposited into the vias (19), and the conductive bumps (16) are inserted into the vias (19) for connecting the semiconductor chip (11) to a conductive element (17) covering the vias (19) on the second side (18) of the substrate (12).
A method and device for attaching a module having a ball grid array or column grid array of solder material thereon arranged in a given pattern or footprint to a substrate having an array of connector pads arranged in the same pattern is provided. A preformed alignment device has an array of through holes therein aligned in the same pattern or footprint as the ball grid array or column pattern on the module and the pattern of contact pads on the substrate. The through holes in the preform are filled with a solder material which can be either a solder paste or a solid solder or with a curable conductive adhesive. The solder preferably is a lead-tin eutectic, but in any event has a melting point of less than about 240.degree. C. and in the case of the conduction adhesive, will cure below about 240.degree. C. In the case of solid solder, thin films of flux material can be applied to opposite faces of the preform to prevent the solder from dislodging therefrom and to act as a flux when the solder is reflowed.
A method of forming a bond structure for use with integrated circuits and semiconductor electronics and carrier assemblies is disclosed. Metallurgical paste is screen printed through a stencil and the stencil is left in place during the reflow process. The melting point of the bond structure and the metallurgical paste is lower than the melting point of interconnects on the electronic components and less than the decomposition temperature of the carrier assemblies to which the electronic components are bonded.
A method of solder bumping is provided which consists of: (1) applying a mask to a first substrate, (2) forming a well within the mask around a pad on the first substrate, (3) placing the solder within the well to from a depression, (4) mating a solder bump located on a second substrate with a solder depression in the well, and (5) reflowing the solder to form a pillar which interconnects the first and second substrates. Furthermore, the method may include the step of removing the mask.
