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Description  |
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FIELD OF THE INVENTION
This invention relates to a semiconductor random access memory device and,
more particularly, to a semiconductor random access memory device for
maintaining parts of data bits in the sense amplifier array.
DESCRIPTION OF THE RELATED ART
A typical example of the semiconductor random access memory device stores
data bits in the memory cells, and the data bits are selectively read out
from the memory cells through a sense amplifier circuit to the outside
thereof in accordance with address signals. Therefore, the read-out
sequence contains a selecting stage with a row address decoder, an
amplification stage for read-out data bits by sense amplifier circuits and
a selecting stage with a column address decoder, and such a serial stages
hardly achieve high-speed access.
However, a new technology is recently proposed for a random access memory
device, and is featured by data-hold in the sense amplifier circuits
incorporated therein. If an accessed data bit is held in the sense
amplifier circuits, the accessed data bit is directly supplied from one of
the sense amplifier circuits, and the access time is shrunk rather than
the read-out from the memory cell array.
FIG. 1 illustrates the random access memory device using sense amplifier
circuits as a temporary data storage. Memory cells incorporated in the
random access memory device are broken down into four memory blocks 1a,
1b, 1c and 1d, and row address decoders 2a, 2b, 2c and 2d are respectively
associated with the four memory blocks 1a to 1d. The memory blocks 1a and
1b share a column address decoder 3a, and another column address decoder
3b is shared between the other memory blocks 1c and 1d. Therefore, each of
the memory cells is addressable through the associated row and column
address decoders, and differential voltages indicative of data bits are
developed by sense amplifier arrays 4a, 4b, 4c and 4d respectively
associated with the four memory blocks 1a to 1d. In this instance, each of
the sense amplifier arrays 4a to 4d simultaneously develops differential
voltages indicative of data bits read out from a row of memory cells.
A block address decoder 5 is provided for the four memory blocks 1a to 1d,
and block address bits are decoded so as to selectively drive four block
address decoded signal lines 5a. The block address decoded signal lines 5a
are respectively coupled with the four memory blocks 1a to 1d, and enable
one of the row address decoders 2a to 2d. Row address signal lines 2e
distribute row address bits to each of the row address decoders 2a to 2d,
and the selected row address decoder is responsive to the row address bits
in the presence of an enable signal ENB1.
The block address decoded signal lines 5a are further coupled with a
selector 6, and the selector 6 is responsive to the block address decoded
signal. Four address registers 7a, 7b, 7c and 7d are respectively
associated with the four memory blocks 1a to 1d, and each of the address
registers 7a to 7d holds a row address of the associated memory block 1a,
1b, 1c or 1d used in the latest access. The four address registers 7a to
7d are coupled with the four input ports of the selector 6, and the output
port of the selector 6 is coupled with a comparator 8. The row address
signal lines 2e are coupled with the other input port of the comparator 8,
and the comparator compares the row address stored in the selected address
register with the row address indicated by the row address bits.
As described hereinbefore, each of the sense amplifier arrays 4a to 4d
stores data bits read out from a row of memory cells in the latest access.
If the row address stored in the selected address register is matched with
the row address indicated by the row address bits, the accessed data bit
is stored in the associated sense amplifier array, and the comparator 8
produces a hit signal so that the sense amplifier array directly supplies
the accessed data bit to the destination.
A write-in circuit 9 is provided for the address registers 7a to 7d, and is
coupled with the row address signal lines 2e and the selector 6. The
write-in circuit 9 is enabled with an internal write enable signal, and
writes the row address signal on the signal lines 2e into the address
register associated with the memory block assigned the block address
indicated by the block address decoded signals. The internal write enable
signal is produced in the presence of the high signal, and the row
addresses stored in the address registers 7a to 7d are updated every hit
FIGS. 2 and 3 show read-out operation of the prior art random access memory
device shown in FIG. 1. FIG. 2 illustrates the read-out operation on a
data bit held in one of the sense amplifier arrays 4a to 4d. Assuming now
that a chip select signal goes down to active low voltage level at time
t1, the prior art random access memory device is activated for access, and
block address bits and row address bits are respectively transferred to
the block address decoder 5 and the row address decoders 2a to 2d.
The block address decoder 5 selectively drives the block address decoded
signal lines 5a at time t2, and the block address decoded signal
indicative of one of the memory blocks 1a to 1d is supplied to the row
address decoders 2a to 2d as well as to the selector 6. However, the row
address bits are not decoded in this stage, because the enable signal ENB1
has not been produced yet.
The selector 6 is responsive to the block address decoded signal, and
transfers an output signal of the associated address register to the
comparator 8 at time t3. The comparator 8 compares the row address bits on
the row address signal lines 2e with the output signal of the associated
address register, and acknowledges consistence between the row addresses.
Then, the comparator 8 produces the hit signal. With the hit signal, the
enable signal ENB1 remains inactive low, and the internal write enable
signal is not produced. For this reason, the row address bits are not
decoded, and one of the column address decoders 3a to 3d allows a column
selector (not shown) to directly transfer a data bit held in the
associated sense amplifier array to an output data buffer circuit (not
shown). Then, the output data buffer circuit produces an output data
signal, and the output data signal indicative of the accessed data bit is
supplied to the destination.
If, on the other hand, an accessed data bit is not held in the sense
amplifier arrays 4a to 4d, the prior art random access memory device
traces the read-out sequence shown in FIG. 3. The read-out sequence starts
with shift of the chip select signal to the active low level at time t11,
and block address bits and row address bits are respectively transferred
to the block address decoder 5 and the row address decoders 2a to 2d.
The block address decoder 5 selectively drives the block address decoded
signal lines 5a at time t12, and the block address decoded signal
indicative of one of the memory blocks 1a to 1d is supplied to the row
address decoders 2a to 2d as well as to the selector 6. However, the row
address bits are not decoded in this stage, because the enable signal ENB1
has not been produced yet.
The selector 6 is responsive to the block address decoded signal, and
transfers an output signal of the associated address register to the
comparator 8 at time t13. The comparator 8 compares the row address bits
on the row address signal lines 2e with the output signal of the
associated address register. However, the comparator 8 does not produce
the hit signal, because the row addresses are inconsistent with one
another.
The enable signal ENB1 is shifted from the inactive low level to the active
high level at time t14, and the internal write enable signal is
concurrently produced. The write-in circuit 9 is enabled with the internal
write enable signal, and the row address bits on the signal lines 2e are
memorized in the address register associated with the memory block
indicated by the block address decoded signal.
On the other hand, one of the row address decoders 2a to 2d is enabled in
the concurrent presence of the block address decoded signal and the enable
signal ENB1, and data bits are read out from a row of memory cells
assigned the row address after precharging and equalization. The read-out
data bits are respectively represented by differential voltages, and the
differential voltages are developed by the associated sense amplifier
array. Thereafter, the sense amplifier array holds new data bits in the
form of differential voltage. The associated column address decoder causes
the column selector (not shown) to transfer one of the differential
voltages indicative of the accessed data bit to the output data buffer
circuit (not shown), and the output data signal becomes valid at time t15.
Thus, the prior art random access memory device uses the sense amplifier
arrays 4a to 4d as a cache memory, and shrinks the access time. However,
this technology is not available for shared sense amplifier arrays.
In detail, the prior art random access memory device is equipped with the
four sense amplifier arrays 4a to 4d exclusively used by the four memory
blocks, and such an exclusive usage allows the sense amplifier arrays to
serve as the cache memory. While the random access memory device is
relatively small in memory capacity, the exclusive usage is not problem.
However, the sense amplifier circuits are increased together with the
memory capacity, and such an advanced random access memory device is
hardly integrated on a relatively small semiconductor chip. One of the
attractive solution is shared sense amplifier circuits. In this instance,
the sense amplifier circuits are shared between two memory cell blocks,
and the sense amplifier circuits are decreased to a half. The shared sense
amplifier circuits are attractive in view of semiconductor chip size.
However, the shared sense amplifier circuits can not be used as a cache
memory, because the correspondence between data bits and memory blocks are
destroyed.
SUMMARY OF THE INVENTION
It is therefore an important object of the present invention to provide a
semiconductor random access memory device which has shared sense amplifier
circuits available as a cache memory.
To accomplish the object, the present invention proposes to memorize memory
blocks already supplied data bits to shared sense amplifier circuits.
In accordance with one aspect of the present invention, there is provided a
random access memory device fabricated on a single semiconductor chip,
comprising: a) a plurality of memory cell blocks each implemented by a
plurality of memory cells arranged in rows and columns, block addresses
being respectively assigned to the plurality of memory cell blocks, row
addresses being respectively assigned to the rows of memory cells of each
memory cell block, column addresses being respectively assigned to the
columns of memory cells of each memory cell block; b) a block selecting
means responsive to block address bits for producing a block address
decoded signal indicative of the block address assigned to one of the
plurality of memory cell blocks; c) a plurality of row selecting means
respectively associated with the plurality of memory cell blocks, and
selectively enabled in the concurrent presence of a first enable signal
and the block address decoded signal for producing a row address decoded
signal indicative of a row address assigned to one of the rows of memory
cells incorporated in the associated memory cell block; d) a plurality of
sense amplifier circuit arrays having sense amplifier circuits, each array
shared between two of the plurality of memory cell blocks, and each
operative to amplify data signals indicative of data bits read-out from a
row of memory cells of one of the plurality of memory cell blocks, the
plurality of sense amplifier circuit arrays holding the data signals until
data signals are newly supplied thereto; e) a column selecting means
responsive to column address bits for selecting one of the data signals
held in the sense amplifier circuit arrays associated with the memory cell
block indicated by the block address decoded signal; f) a plurality of
flag means respectively associated with the plurality of memory cell
blocks, and operative to produce flag signals each indicative of whether
or not the data bits stored in one of the plurality of sense amplifier
circuit arrays are read out from the associated memory cell block; g) a
block address discriminating means operative to compare the block address
decoded signal with the flag signals for producing a first hit signal when
the block address decoded signal is indicative of one of the plurality of
memory cell blocks which has already supplied data bits to the associated
sense amplifier circuit array; h) a plurality of address storage means
respectively associated with the plurality of memory cell blocks, and each
storing the row address assigned to one of the rows of memory cells
selected from the associated memory cell block in the latest access; i) a
row address discriminating means operative to compare the row address
indicated by the row address bits with the row address stored in each
address storage means for producing a second high signal when the row
addresses are consistent with each other; j) a control means operative to
keep the first enable signal in inactive level in the concurrent presence
of the first hit signal and the second hit signal for allowing the column
selecting means to transfer the one of the data signals without readout
from the memory cell block indicated by the block address decoded signal
and to produce the first enable signal and a second enable signal in the
absence of at least one of the first hit signal and the second high
signal; and k) a write-in means responsive to the second enable signal for
writing the row address indicated by the row address bits into the address
storage means associated with the memory cell block designated by the
block address decoded signal.
In accordance with another aspect of the present invention, there is
provided a random access memory device fabricated on a single
semiconductor chip, comprising: a) a plurality of memory cell blocks each
implemented by a plurality of memory cells arranged in rows and columns,
block addresses being respectively assigned to the plurality of memory
cell blocks, row addresses being respectively assigned to the rows of
memory cells of each memory cell block, column addresses being
respectively assigned to the columns of memory cells of each memory cell
block; b) a block selecting means responsive to block address bits for
producing a block address decoded signal indicative of the block address
assigned to one of the plurality of memory cell blocks; c) a plurality of
row selecting means respectively associated with the plurality of memory
cell blocks, and selectively enabled in the concurrent presence of a first
enable signal and the block address decoded signal for producing a row
address decoded signal indicative of a row address assigned to one of the
rows of memory cells incorporated in the associated memory cell block; d)
a plurality of sense amplifier circuit arrays having predetermined sense
amplifier circuits, each array shared between two of the plurality of
memory cell blocks, and each operative to amplify data signals indicative
of data bits read-out from a row of memory cells of one of the plurality
of memory cell blocks, the plurality of sense amplifier circuit arrays
holding the data signals until data signals are newly supplied thereto; e)
a column selecting means responsive to column address bits for selecting
one of the data signals held in the sense amplifier circuit arrays
associated with the memory cell block indicated by the block address
decoded signal; f) a plurality of data source memorizing means
respectively associated with the plurality of sense amplifier circuit
arrays, and storing respective row addresses assigned to rows of memory
cells each selected in the latest access to the associated memory cell
block and respective address codes indicative of memory cell blocks
respectively containing the rows of memory cells; g) a block address
discriminating means operative to compare the block address decoded signal
with the address codes to see whether or not the plurality of sense
amplifier circuit arrays store the data signals indicative of data bits
read out from the memory cell block indicated by the block address decoded
signal, the block address discriminating means producing a first hit
signal when the plurality of sense amplifier circuit arrays store the data
signals indicative of the data bits read out from the memory cell block
indicated by the block address decoded signal; h) a row address
discriminating means operative to compare the row address indicated by the
row address bits with the row address stored in two of the plurality of
data source memorizing means associated with the memory cell block
indicated by the block address decoded signal for producing a second high
signal when the row addresses are consistent with one another; i) a
control means operative to keep the first enable signal in inactive level
in the concurrent presence of the first hit signal and the second hit
signal for allowing the column selecting means to transfer the one of the
data signals without read-out from the memory cell block indicated by the
block address decoded signal and to produce the first enable signal and a
second enable signal in the absence of at least one of the first hit
signal and the second high signal; and k) a write-in means responsive to
the second enable signal for writing the row address indicated by the row
address bits into the data source memorizing means associated with the
memory cell block indicated by the block address decoded signal.
BRIEF DESCRIPTION OF THE DRAWINGS
The features and advantages of the semiconductor random access memory
device according to the present invention will be more clearly understood
from the following description taken in conjunction with the accompanying
drawings in which:
FIG. 1 is a block diagram showing the arrangement of the prior art random
access memory device;
FIG. 2 is a timing chart showing the read-out operation when the accessed
data bit is held in the sense amplifier array;
FIG. 3 is a timing chart showing the read-out operation when the sense
amplifier array does not hold the accessed data bit
FIG. 4 is a block diagram showing the arrangement of a random access memory
device according to the present invention;
FIG. 5 is a circuit diagram showing a flag control circuit incorporated in
the random access memory device according to the present invention;
FIG. 6 is a circuit diagram showing another random access memory device
according to the present invention;
FIG. 7 is a circuit diagram showing a combined circuit of selector and
comparator incorporated in the random access memory device shown in FIG.
6; and
FIG. 8 is a circuit diagram showing the arrangement of an address converter
incorporated in yet another random access memory device according to the
present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
First Embodiment
Referring to FIG. 4 of the drawings, a random access memory device
embodying the present invention is fabricated on a single semiconductor
chip 11. The random access memory device largely comprises a memory cell
array 12, an addressing system a data transferring system and a cache
controlling system 15. Although the random access memory device has other
component circuits such as an address buffer, a precharging circuit, a
write-in data amplifier and a timing controller, they are deleted from
FIG. 4 for the sake of simplicity.
The memory cell array 12 is implemented by four memory cell blocks 12a,
12b, 12c and 12d, and each of the memory cell blocks 12a to 12d has a
plurality of memory cells arranged in rows and columns. The memory cells
are of the random access type, and small bubbles are represented by small
bubbles, respectively. The four memory cell blocks 12a to 12d are
respectively assigned block addresses. Moreover, the rows of memory cells
of each memory cell block 12a, 12b, 12c or 12d are assigned row addresses,
and the row addresses are identical between the corresponding rows of the
four memory cell blocks 12a to 12d. Similarly, column addresses are
assigned to the columns of memory cells of each memory cell block 12a,
12b, 12c or 12d, and the column addresses are identical between the
corresponding columns of the four memory cell blocks 12a to 12d.
The addressing system 13 are broken down into a block selecting sub-system,
a row selecting sub-system and a column selecting sub-system, and the
block selecting sub-system, the row selecting sub-system and the column
selecting sub-system allow an external device such as, for example, a
microprocessor (not shown), to selectively access data bits stored in the
memory cell array 12 in a direct or indirect fashion.
The block selecting sub-system has a block address decoder 13a and four
block address decoded signal lines 13b. Block address bits are supplied to
the block address decoder 13a, and the block address decoder 13a decodes
the block address bits for selectively driving the block address decoded
signal lines 13b with a block address decoded signal. The block address
decoded signal is indicative of a memory cell block selected by the
external device.
The row selecting sub-system has four row address decoders 13c, 13d, 13e
and 13f and four sets of word lines WL1 to WLm. The four row address
decoders 13c to 13f and the four sets of word lines WL1 to WLm are
respectively associated with the four memory cell blocks 12a to 12d, and
the word lines WL1 to WLm of each memory cell block are coupled with the
rows of memory cells, respectively. The row address decoders 13c to 13f
are responsive to a first enable signal ENL1, and one of the row address
decoders 13c to 13f indicated by the block address decoded signal becomes
responsive to row address bits. In other words, the row address decoders
13c to 13f are selectively activated in the concurrent presence of the
first enable signal ENL1 and the block address decoded signal, and decode
the row address bits for selectively driving the word lines WL1 to WLm of
the associated memory cell blocks 12a to 12d. While a word line is driven
to active level, data bits are writeable from and readable into the
associated memory cells.
The column selecting sub-system has a column address decoder and a column
selector which are labeled with 13g in FIG. 4. The column address
decoder/selector 13g is responsive to column address bits, and selects one
of the columns of memory cells from the selected memory cell block.
The data transferring system 14 has four sets of bit line pairs BP1, BP2,
BPm and BPn, five sense amplifier circuit arrays 14a, 14b, 14c, 14d and
14e, a data bus 14f and a data output buffer 14g. The four sets of bit
line pairs BP1 to BPn are respectively associated with the four memory
cell blocks 12a to 12d. Each of the bit line pairs BP1 to BPn is
associated with two columns of memory cells, and propagates a data bit in
the form of differential voltage from one of the associated memory cells
to the associated sense amplifier circuit array.
A plurality of sense amplifier circuits are incorporated in each of the
sense amplifier circuit arrays 14a to 14e, and the sense amplifier
circuits of each array 14b, 14c or 14d are shared between two memory cell
blocks 12a/12b, 12b/12c or 12c/12d. The sense amplifier circuits of the
array 14a are coupled with every other bit line pair associated with the
memory cell block 12a, and the sense amplifier circuits of the array 14e
are coupled with every other bit line pair associated with the memory cell
block 12d. Each of the sense amplifier circuits of the array 14b is shared
between two bit line pairs of the associated two memory cell blocks. For
example, the leftmost sense amplifier circuit of the array 14b is coupled
between the bit line pair BP2 of the memory cell block 12a and the bit
line pair BP2 of the memory cell block 12b, and the rightmost sense
amplifier circuit of the array 14b is provided for the bit line pair BPm
of the memory cell block 12a and for the bit line pair BPm of the memory
cell block 12b. Similarly, the sense amplifier circuits of the array 14c
are shared between the bit line pairs of the memory cell block 12b and the
bit line pairs of the memory cell blocks 12c, and the sense amplifier
circuits of the array 14d are shared between the bit line pairs of the
memory cell block 12c and the bit line pairs of the memory cell block 12d.
For this reason, the sense amplifier circuits of the array 14b, 14c or
14d are coupled with the bit line pairs of one of the two memory cell
blocks, and develop differential voltages indicative of data bits on the
bit line pairs. The sense amplifier circuits holds the differential
voltages until small differential voltages are newly supplied thereto.
As described hereinbefore, the column address decoder/selector 13g selects
one of the columns of memory cells from the selected memory cell block.
One of the word lines WL1 to WLm allows a memory cell of the selected
memory cell block to supply a data bit through the associated bit line
pair to the sense amplifier circuit in so far as the sense amplifier
circuit holds a data bit read out from the other memory cell block, and
the sense amplifier circuit supplies the differential voltage indicative
of the data bit through the column address decoder/selector 13g to the
data output buffer 14g. However, if the sense amplifier circuit has
already held the data bit, the data bit is directly supplied from the
sense amplifier circuit through the column address decoder/selector 13g to
the data output buffer 14g without any precharging and selecting a row of
memory cells. The data output buffer 14g produces an output data signal
indicative of the data bit from the differential voltage, and supplies the
output data signal to the external device. The read-out from a memory cell
and the read-out from a sense amplifier circuit hereinbelow refer to as
"indirect data access" and "direct data access" , respectively.
The cache controlling system 15 largely comprises a flag unit 15a, a block
address discriminating unit 15b, a row address storage unit 15c and a
controlling unit 15d, and the cache controlling system 15 decides which
data access, i.e., the direct data access or the indirect data access to
take.
The flag unit 15a comprises a plurality of latch circuits 15e responsive to
a latch control signal CTL1, and a flag control circuit 15f coupled with
the latch circuits 15e for producing a flag signal indicative of directly
accessible memory cell block or blocks 12a to 12d. The latch control
signal CTL1 is produced at every access, and allows the latch circuits 15e
to store the block address decoded signal newly decoded by the block
address decoder 13a. FIG. 5 shows the circuit arrangement of the flag
control circuit 15f, and the flag control circuit 15f comprises four R-S
flip-flop circuits 15g, 15h, 15i and 15j and two OR gates 15k and 15m. The
output ports of the latch circuits 15e are respectively coupled with the
set nodes of the R-S flip-flop circuits 15g to 15j, and the reset nodes of
the R-S flip-flop circuits 15g and 15j are coupled with the set nodes of
the R-S flip-flop circuits 15h and 15i. The set nodes of the R-S flip-flop
circuits 15g and 15i and the set nodes of the R-S flip-flop circuits 15h
and 15j are respectively coupled with the input nodes of the OR gate 15k
and the input nodes of the OR gate 15m, and the R-S flip-flop circuits 15g
to 15j enter the set-state if either R-S flip-flop circuit 15g or 15i and
either R-S flip-flop circuit 15h or 15j are shifted to the set-state.
While the R-S flip flop circuit remains in the set-state, the associated
bit of the flag signal is indicative of the allowability of direct data
access to the associated memory cell block. For example, if a data bit was
read out from the memory cell block 12b, the bit of the block address
decoded signal indicative of the memory cell block 12b was latched by the
latch circuits 15e, and data bits concurrently read out from a row of
memory cells have been stored in the sense amplifier circuit arrays 14b
and 14c. The latch circuits 15e caused the R-S flip-flop circuit 15h to
enter the set state, and the adjacent R-S flip flop circuits 15g and 15i
were kept in or changed to the reset state. The bit of the flag signal
produced by the R-S flip flop circuit 15h is indicative of the
allowability of the direct data access, because the sense amplifier
circuit arrays 14b and 14c stores the data bits supplied from the memory
cell block 12b. However, the bits of the flag signal produced by the R-S
flip-flop circuits 15g and 15i are indicative of the prohibition or the
direct data access, because the sense amplifier circuit arrays 14b and 14c
are not available. Thus, the four-bit flag signal are indicative of the
allowability of the direct data access to the associated memory cell
blocks 12a to 12d. In the following description, the bit of logic "1"
level and the bit of logic "0" level are respectively indicative of the
allowability and the prohibition.
Turing back to FIG. 4 of the drawings, the block address discriminating
unit 15b comprises four AND gates 15n, 15o, 15p and 15q and an OR gate
15r, and the four AND gates have respective input nodes coupled with the
four R-S flip-flop circuits 15g to 15j. The other input nodes of the AND
gates are respectively coupled with the block address decoded signal
lines. The R-S flip-flop circuits 15g to 15j produce the bits of the flag
signals indicative of the allowability of the direct data access.
Therefore, if the block address decoded signal is indicative of the
allowable memory cell block again, the accessed data bit can be supplied
from the associated sense amplifier circuit array to the outside thereof,
and the access speed is improved. In case of the flag signal indicative of
the allowability of the direct data access to the memory cell block 12b,
the AND gate 15p is supplied with the bit of the flag signal of logic "1"
level, and the adjacent AND gates 15o and 15q are respectively supplied
with the bits of logic "0" level. If the block address decoded signal is
indicative of the memory cell block 12b, the block address decoded signal
lines supplies logic "1" to the AND gate 15p, and, accordingly, the OR
gate 15r produces a first hit signal HT1 of logic "1" level. However, if
the block address decoded signal is indicative of either memory cell block
12a or 12c, the block address decoded signal lines supplies logic "0" to
the AND gate 15p, and the AND gates 15o and 15q have already been supplied
with the bits of the flag signal of logic "0". Therefore, any AND gate can
not yield logic "1" level, and the OR gate does not produce the first hit
signal HT1 of logic "1" level.
The row address storage unit 15c comprises four address registers 15s, 15t,
15u and 15v and a write-in circuit 15w. The four address registers 15s to
15v are respectively associated with the four memory cell blocks 12a to
12d, and each of the four address registers 15s to 15v stores a row
address selected in the previous data access to the associated memory cell
block. Namely, the write-in circuit 15w writes or rewrites a row address
indicated by the row address bits in the address register indicated by the
block address decided signal.
The controlling unit 15d comprises a selector 15x, a comparator 15y, an AND
gate 15z and a signal generator SG. The selector 15x are responsive to the
block address decoded signal, and transfers the previous row address bit
from one of the address registers 15s to 15v indicated by the block
address decoded signal to the comparator 15y. The external row address
bits are further supplied to the comparator 15y, and are compared with the
previous row address supplied through the selector 15x. If the current row
address bits are consistent with the previous row address bits, the
comparator 15y produces a second hit signal HT2 of logic "1" level. The
first and second hit signals HT1 and HT2 are supplied to the AND gate 15z,
and the AND gate 15z yields a third hit signal HT3 of logic "1" level in
the concurrent presence of the first hit signal HT1 of logic "1" level and
the second hit signal HT2 of logic "1" level. The third hit signal HT3 of
logic "1" level is indicative of the permission of the direct data access,
and the third hit signal HT3 of logic "1" level triggers the signal
generator SG for producing a final hit signal HTf, and the column address
decoder/column selector 13g transfers an accessed data bit from one of the
sense amplifier circuit array 14a to 14e to the data output buffer circuit
14g. However, the signal generator SG does not produces the first enable
signal ENL1 and the internal write enable signal ENL2. On the other hand,
if the AND gate 15z keeps the third hit signal HT3 in logic "0" level, the
signal generator SG produces the first enable signal ENL1 and the internal
write enable signal ENL2 and | | |
