Memory mapping and special write detection in a system and method for simulating a CPU processor

What is claimed is:

1. A method for aiding in simulating a first instruction flow of control of an application, said flow of control having a plurality of first instructions of a first processor instruction set, by a plurality of second instructions of a second processor instruction set of a processing system, said method comprising:

creating a table having a plurality of locations corresponding to a plurality of second processor memory locations, each one of said second processor memory locations having contents the same as a respective first processor memory location, for indicating a type of contents for any one of said second processor memory locations;

storing, during a translation of an instruction of said first processor instruction set contained within any one of said second processor memory locations into an instruction of said second processor instruction set, a first indicator, in a location in said table corresponding to said second processor memory location, indicating that the type of contents of said second processor memory location is an instruction;

determining, during a modification to the contents of any one of said plurality of second processor memory locations, whether an instruction is being modified by checking the corresponding location in the table for said stored first indicator; and

determining whether translation is necessary for the contents in said second processor memory location being modified if said first indicator indicates an instruction is being modified.

2. A system for aiding in simulating a first instruction flow of control of an application, said flow of control having a plurality of first instructions of a first processor instruction set, by a plurality of second instructions of a second processor instruction set of a processing system, said system comprising:

means for creating a table having a plurality of locations corresponding to a plurality of second processor memory locations, each one of said second processor memory locations having contents the same as a respective first processor memory location, for indicating a type of contents for any one of said second processor memory locations;

means for storing, during a translation of an instruction of said first processor instruction set contained within any one of said second processor memory locations into an instruction of said second processor instruction set, a first indicator, in a location in said table corresponding to said second processor memory location, indicating that the type of contents of said second processor memory location is an instruction;

means for determining, during a modification to the contents of any one of said plurality of second processor memory locations, whether an instruction is being modified by checking the corresponding location in the table for said stored first indicator; and

determining whether translation is necessary for the contents in said second processor memory location being modified if said first indicator indicates an instruction is being modified.

3. A method for aiding in simulating a first instruction flow of control of an application, said flow of control having a plurality of first instructions of a first processor instruction set of a first processor, by a plurality of second instructions of a second processor instruction set of a second processor of a processing system, said method comprising:

correlating each one of a plurality of locations in memory with a corresponding indicator indicating a type of contents for the memory location;

determining, during a modification to the contents of any one of said plurality of memory locations of said processing system running said application, whether said application modified any one of said plurality of memory locations having one of said plurality of first instructions, said one of said plurality of first instructions having a translation sequence of said second instructions associated therewith, by checking if the corresponding indicator of said memory location indicates that the type of contents is an instruction; and

updating said translation sequence to a new translation sequence of said second instructions, if said one of said first instructions is modified, for simulating the modified first instruction by executing said new translation sequence by said second processor.

4. The method of claim 3 wherein the step of updating comprises the step of purging the translation sequence of one of said first instructions, and translating the modified instruction to a new sequence of said second instructions for execution by said second processor.

5. A detection method for aiding in simulating a first processor, having a first instruction set, of a first processing system, by a second processing system, said second processing system having a second processor having a second instruction set for running an application targeted for said first instruction set, said detection method comprising:

mapping memory of the first processing system into memory of said second processing system;

correlating each one of a plurality of locations of said memory of said second processing system mapped from said first processing system with a corresponding indicator indicating both a type of contents for the memory location and a type of action to take based on the type of contents for said memory location; and

determining, at a time of a store to the memory location by said second data processing system, if the store to memory requires simulation processing, depending upon the contents of the memory location, by checking the indicator to determine the type of action to take based on the indicator contents concurrently with the store to the memory location.

6. A detection system for aiding in simulating a first processor, having a first instruction set, of a first processing system, by a second processing system having a second processor having a second instruction set for running an application targeted for said first instruction set, said detection system comprising:

means for mapping a plurality of first address locations of memory of the first processing system into a second plurality of address locations of memory of said second processing system;

means for correlating each one of said second plurality of address locations of memory of said second processing system with a corresponding indicator indicating both a type of contents for each of said second plurality of address locations and a type of action to take based on the type of contents for each of said second plurality of address location; and

means for determining, at a time of a store to one of the second address locations of memory by said second data processing system, if the store to memory requires simulation processing, depending upon the contents of the memory location, by checking the indicator to determine the type of action to take based on the indicator contents concurrently with the store to the memory location.

7. A detection system for aiding in simulating a first processor, having a first instruction set, of a first processing system, by a second processing system having a second processor having a second instruction set for running an application targeted for said first instruction set, said detection system comprising:

means for translating a plurality of address locations of memory of the first processing system into (i) a first plurality of translated address locations of a first memory segment of said second processing system and (ii) a second plurality of translated address locations of a second memory segment of said second processing system, said second plurality of translated address locations corresponding to memory mapped I/O of an adapter;

means for correlating each one of said translated address locations in said first and second memory segments with a third memory segment address location, in said second processing system, containing an indication of both a type of contents for a corresponding location in said first and second memory segment and a type of action to take based on the type of contents for said corresponding location in said first and second memory segment;

means for performing an AND operation on one of said first and second plurality of translated address locations with a constant value and using this result to find the type of contents, of said one address location, from said corresponding third memory segment address location during a modification to the contents of said one address location by said second processing system; and

means for determining, concurrently with the modification to the contents of the one address location, whether simulation processing is necessary for the contents in memory being modified, depending upon the type of contents of said one address location, as indicated by said corresponding third memory segment address location.

8. The system of claim 7 wherein if said corresponding third memory segment address location contains a zero value, no simulation processing is required on said contents of said one address location.

9. The system of claim 7 wherein if said corresponding third memory segment address location indicates that the type of contents is a translated instruction in said memory of said second processing system, simulation processing is necessary if the contents of the one address location is modified.

10. The system of claim 7 wherein if said corresponding third memory segment address location indicates that there is an output device of said first processing system attached to said second processing system, no simulation processing is required on said modified contents of the one address location.

11. The system of claim 7 wherein if said corresponding third memory segment address location indicates that an output device of the first processing system is not attached to said second processing system, simulation processing is needed on said modified contents of the one address location.

12. A method of aiding in simulating a first processor, having a first instruction set, of a first processing system, by a second processing system, said second processing system having a second processor having a second instruction set for running an application targeted for said first instruction set, said method comprising:

translating a plurality of address locations of memory of the first processing system into a translated plurality of address locations of a first memory segment of said second processing system;

correlating each of said translated plurality of address locations of said first memory segment with a corresponding second memory segment address location containing an indication of both a type of contents of the corresponding translated address location of said first memory segment in said second processing system and a type of action to take based on the contents of the corresponding translated address location of said first memory segment in said second processing system;

performing an instruction sequence on each one of a plurality of translations, of a first processing system instruction, which is able to modify a content of said first memory segment address location of said second processing system, to determine the type of contents, of the corresponding translated address location of said first memory segment in said second processing system, as indicated by the corresponding second memory segment address location of said second processing system; and

determining if simulation processing is required on said content of said first memory segment address location depending on the type of action to take, based on the contents of said first memory segment address location, as indicated by said corresponding second memory segment location.

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CROSS-REFERENCES TO RELATED APPLICATIONS

Ser. No. 06/820,451, filed Jan. 17, 1986 for a VIRTUAL TERMINAL SUBSYSTEM, currently co-pending, and assigned to the same assignee as the present invention, now abandoned.

Ser. No. 07/151,136filed Feb. 1, 1988 for a CONDITION CODE GRAPH ANALYSIS FOR SIMULATING A CPU PROCESSOR, currently co-pending, and assigned to the same assignee as the present invention, which is hereby incorporated by reference now U.S. Pat. No. 4,951,195.

Ser. No. 07/151,123, filed Feb. 1, 1988 for a SYSTEM AND METHOD FOR SIMULATING THE I/0 OF A PROCESSING SYSTEM, currently co-pending, and assigned to the same assignee as the present invention, which is hereby incorporated by reference now U.S. Pat. No. 5,129,064.

Ser. No. 07/151,137, filed Feb. 1, 1988 for TRANSLATING A DYNAMIC TRANSFER CONTROL INSTRUCTION ADDRESS IN A SIMULATED CPU PROCESSOR, currently co-pending, and assigned to the same assignee as the present invention, which is hereby incorporated by reference now U.S. Pat. No. 5,167,023.

A portion of the Disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to data processing systems running applications written for a specific first processor of a first processing system, and more particularly to a system and method of simulating the first processor for running the applications on a second processing system having a second dissimilar processor.

2. Description of the Related Art

Current advances in computer technology have lead to ever changing processors, otherwise referred to herein as the central processing unit (CPU), of the processing system. Examples of the evolution of various processors are Intel's 8088 processor used in the IBM PC, Intel's 80286 processor used in the IBM PC AT1, Intel's 80386 processor used in the IBM Personal System/2.sup.2 model 80, and the IBM Research/ OPD Microprocessor (ROMP) which utilizes a Reduced Instruction Set Computer (RISC) architecture in the IBM RT PC.sup.3. Other processors include Motorola's 68000, 68020 among others.

The hardware of various processing systems changes rapidly to take advantage of the increased processing power of emerging processors. A disadvantage of changing hardware is that the software written for previous processors typically can not be used on the later hardware technology. In some cases where an application can be used on a different processing system other than the one it was originally written for, the performance of the application is not as good on the different processing system as it would have been on the processing system for which the application was originally written. As a result, software applications which may have had a long development cycle may become obsolete quickly. The demise of the earlier written software is all the more tragic when the function of the application as originally written is still very much pertinent and in demand on the new hardware processing systems.

As a result, there is typically only a limited amount of "new" software available that is specifically written for the "new" hardware design when the new hardware is initially released into the market place. This is due in part by the long development cycle of creating software application programs, and the confidentiality of the new hardware design by the manufacturer prior to releasing the hardware into the market place. The software manufacturer has to know certain facts about the hardware of a processing system before a software application program can be written for the processing system.

Ideally, a manufacturer of processing systems would like to have a vast amount of software available to run on the processing system as soon as the new hardware for the processing system is announced into the market place. A customer would more likely invest in a new processing system if the customer knows that an abundant supply of software is already available for use.

There have been several approaches in tapping the vast amount of software that has previously been written for "older" hardware designs. A previous hardware approach for being able to run applications originally written for another processor is to build the new processing system with a coprocessor. In this way, the processing system can run applications for both types of processors, the new processor and the old processor.

For example, the IBM RT PC contained an IBM PC AT coprocessor in order to use applications that were originally written for the IBM PC AT. However, since the coprocessor was supported at a low level in the operating system, the coprocessor could not take full advantage of the functions provided by the AIX.sup.4 operating system. One of the functions provided by the AIX operating system is multi-tasking as described in co-pending application Ser. No. 820,451, filed Jan. 17, 1986 for a VIRTUAL TERMINAL SUBSYSTEM and assigned to the same assignee as the present invention, which is herein incorporated by reference.

The coprocessor, however, limits the user to one session at a time, since the coprocessor included a hardware adapter for emulating the PC AT. In other words, once the coprocessor was started, no other instances of the coprocessor could be running.

The coprocessor is also limited to the speed of the processor of the first processing system and cannot take advantage of faster second processing systems as they evolve.

A second approach is to simulate the second processor through software. A software simulator provides a mechanism to run previously written software for one processor on a new processing system having a different processor. A software approach to simulation allows taking advantage of faster second processing systems as they evolve. It also allows the use of multitasking capabilities of the operating system to provide multiple instances of the first processor.

Some software simulators on the market today include SoftPC, by Insignia Solutions, and the Amiga Transformer by Simile Research Inc. for Commodore's Amiga (based on Motorola's 68000). Information on this system was published in the article "Amiga's Trump Card: IBM PC Emulation", AMIGA WORLD, Vol. 1, No. 2, November/December 1985. Phoenix Technologies also provided a simulator to simulate the Intel processor for the Apollo machine which has a Motorola 68000 processor.

Any specific CPU processor has a specific instruction set. When a software application program is developed for a specific CPU processor, it is compiled into object code. The object code is targeted to run on any CPU that supports the specific instruction set. A simulator takes object code that was written to run on a specific instruction set, and converts it to run on a different processor which may have a similar or different instruction set. The more the two instruction sets of the two processors are different, the more difficult it is to simulate the other processor.

For example, the Intel 80286 processor has a very rich instruction set in that it provides a wide variety of instructions. Each instruction is tailored specifically for a particular type of situation. Additionally, each instruction may be able to do several operations. In contrast, the ROMP processor in the RT PC has a reduced instruction set (RISC) processor which provides fewer instructions and less function per instruction. As each instruction in the Intel 80286 may be able to do several tasks, more instructions would be required with the ROMP RISC processor to accomplish the same tasks.

However, the speed of a processor can be increased by simplifying the instruction set. Although more instructions are required, no additional time is consumed on complicated instructions while executing the more common and simpler tasks.

Previous methods of software simulators created a subroutine that would simulate the effect of an instruction. Every time the machine being simulated needed to run that instruction, the subroutine would be called in order to decode and execute that instruction. The problem with this approach is that the overhead of decoding the instruction occurs every time the subroutine is called and executed. Consequently, the speed of the simulated processor is affected.

Instead of calling a subroutine each time an instruction needed to be executed, another software simulation approach compiled a shorter sequence of host machine instructions to simulate an instruction. As a result, the overhead of decoding and translating the instruction occurs only once, during the first time the instruction is encountered. This translation is then saved. From then on, every time that instruction is simulated, the translation is executed. This is often referred to as a second generation simulator. A first generation simulator will take an instruction one at a time and decode it in real time and execute it. The decoding is done for each instruction as each instruction is needed. A second generation simulator will go through the instructions one at a time, translate the instructions, and then reuse that translation instead of going back and translating again.

A previous second generation simulator was the simulator that simulated the IBM ROMP CPU on the IBM System/370 called RSIM. This simulator reserves a fixed amount of storage for each instruction (16 bytes for every half word) called cells. IBM 370 instructions would then be generated for each one of these cells for each RT instruction. If the amount of code generated is less than what would fit in one cell, which is usually the case, then it branches to the next boundary of the next cell. If the amount of code generated to simulate the instruction can not fit into one cell, then a subroutine call is generated that branches to a run time environment set of routines which performs the emulation and returns back to the cell to complete execution. Another simulator simulates the processor of the IBM System/370 on the IBM RT PC which is described in the following article: May, C. "Mimic: A Fast System/370 Simulator", presented Jun. 11, 1987 at the Association of Computing Machinery Symposium on Interpreters and Interpretive Techniques, and published in SIGPLAN, 1987 proceedings of ACM.

A first generation simulator runs 50 to 100 host machine instructions per simulated instruction. A second generation simulator runs an average of 10 host machine instructions per simulated instruction.

If a simulator takes either 50 or 10 instructions to simulate one instruction on the simulated machine, the second processor running the simulator must be either 50 or 10 times as fast respectively as the simulated machine to be comparable in performance. It is therefore desirable to further reduce the number of simulator instructions per each simulated or translated instruction than what has previously been accomplished in the art.

For example, if a simulator could be designed to use only 4 instructions per simulated instruction, and the simulator processor is more than 4 times faster than the simulated machine processor, the simulator will be faster than the original machine being simulated. A user would then observe increased performance by using the simulated machine to run an application program than by using the machine for which the application program was originally written.

Therefore, the overall problem to overcome in simulating another processor is to further reduce the number of simulator (host) instructions per simulated instruction in order to increase the processing speed of the simulator.

SUMMARY OF THE INVENTION

It is therefore an object of this invention to reduce the average host machine instructions per simulated machine instructions.

The simulator of this invention runs applications originally written for a different processor by means of software emulation. The software approach of simulation allows the flexibility of utilizing the functions of the operating system of the simulator machine. In the preferred embodiment of this invention, the simulator runs as an application on the AIX operating system of the RT PC. It therefore can take advantage of the multi-tasking, multi-user capabilities of the AIX operating system to allow multiple applications originally written for the PC AT to run concurrently without any change to the application itself.

The method of simulation of this invention provides faster processing capability of the simulated processor than the previous methods of processor simulation by reducing the number of host machine instructions per simulated machine instruction. This was achieved by identifying key processing areas that had used more instructions than desired, and then by creating new methods to achieve the processing tasks through fewer instructions.

To increase the CPU simulation, i.e., reduce the average number of host instructions per simulated instruction, several key processing areas were identified that were currently utilizing more instructions than desired.

First, the processing task of maintaining and keeping the correct values of the condition codes was identified as disclosed in Ser. No. 07/151,136, filed Feb. 1, 1988 for a CONDITION CODE GRAPH ANALYSIS FOR SIMULATING A CPU PROCESSOR, currently co-pending, and assigned to the same assignee as the present invention, which is hereby incorporated by reference. The method of this invention utilizes a graph analysis technique previously applied to compiler technology, and applies it to CPU simulator technology to dynamically determine whether condition codes will be needed by any subsequent instruction. The simulator saves sufficient information to generate those condition codes that may be needed. Otherwise, the number of translated instructions required are reduced for that instruction, if it is determined from the graph analysis that the condition codes are not needed.

Another area that was addressed to reduce the average number of instructions generated involves translating the addresses of instructions as disclosed in Ser. No. 07/151,137, filed Feb. 1, 1988 for TRANSLATING A DYNAMIC TRANSFER CONTROL INSTRUCTION ADDRESS IN A SIMULATED CPU PROCESSOR, currently co-pending, and assigned to the same assignee as the present invention, which is hereby incorporated by reference. The reference discloses a three tier approach in determining the address of the next instruction by using a compare in the case where the currently executing instruction returns to the same address as the last time it executed, by using a translate look-aside buffer if it returns to an address that was returned to at least once before, if not immediately before, and by using binary trees as a last resort if the preceding two cases fail. The return address is used in a general way to refer to an address of any instruction which transfers control by computing the next target address from a value in a register or memory.

A third prime processing area that was identified for reducing the average number of host instructions per simulated instruction was the processing task of being able to detect what happens when an instruction stores to memory. The contents of memory can be divided into three areas. The contents of memory are either instructions, or data used in computation, or memory mapped I/O. Memory mapped I/O are contents of memory (referred to herein as a video buffer) that are being interpreted by hardware and presented, as an example, on a display screen. A video buffer is part of a hardware adapter that is updated by an application to display information on a output display device. Of these three different types of contents of memory, only computational data can be stored without any further action by the simulator.

If there is a store into a section of memory which contains instructions, an instruction is being modified and therefore the translation for the instruction may no longer be valid. A check for instruction modification is performed to insure that the translated code is always correct. If an application performs instruction modification, the translated code for the original code instruction is purged, and the new instruction translated to a new sequence of instructions of the simulator's processor. Other steps could be taken to guarantee that the correct translation of the instruction will be executed.

Likewise, the check for video updates is necessary to determine if the output to an output device needs to be further processed by the simulator. This would occur in the case where the output device of the first processing system is not attached to the second processing system running the simulator, and the output device of the first processing system therefore must be simulated. In the case of memory mapped I/O, it must be detected at the time of a store whether the special hardware that is representing the output data is being modified. Previous simulators spend a lot of cycles calling subroutines after performing a store to memory to determine if these two types of contents of memory, instructions and memory mapped I/O, are being affected.

The simulator of this invention provides a method for checking any first processor instruction which updates memory, to determine if the instruction is modifying a subsequent instruction or performing a video buffer update. The method of this invention reduces the number of cycles, i.e. instructions, required to detect this modification. The amount of storage required for an application program to run on the simulator has increased, but the speed has increased. Essentially, an increase in performance is achieved at the cost of increased storage space that is needed.

The system and method of this invention comprises a table that contains a one to one byte correspondence between memory and a status that indicates what type of use is being given for that specific memory location. A zero indicates that computational data is being stored at that memory location. In this way, in a virtual memory system, pages that were not previously referenced indicate the most common occurrence, which as far as can be determined, is computational data. Next, when an instruction is translated, it is known at that time that the memory locations correspond to an instruction. An indication of this information is stored in the table.

At simulator start up time, a user configures the simulator by indicating if an output device, such as a display, of the first processing system is attached to the user's processing system which is running the simulator. If there is, no additional simulator processing needs to be done to the data that is directed to an output device. If an output device of the first processing system is not attached to the second processing system, additional simulator processing is performed on the data directed to the output device to simulate the same effect on a different output device. At simulator start up time and after configuration, it is indicated that the output device is not attached by storing a non-zero value in a status table indicating that the video buffer is a special memory location needing further simulator processing.

At execution time a check is made to convert the address of the memory location being modified to an address of the table. If the contents are