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Claims  |
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What is claimed is:
1. A semiconductor memory device storing data having a unit of N bits (N is
an integer), comprising:
M alternate memory elements having a plurality of memory cells (M is an
integer and larger than N), each of said alternate memory elements being
divided into a plurality of blocks, each of said memory blocks having a
plurality of said memory cells in at least one column, and each of said
memory cells storing one-bit data;
M first bus lines each carrying one-bit data and connected to a
corresponding one of said M alternate memory elements;
designating means, coupled to said M alternate memory elements, for
receiving an address signal from an external device and for designating
one of said plurality of blocks of each of said M alternate memory
elements so that at least M blocks are designated by said address signal;
memory means for storing information on whether or not each of said
plurality of blocks of each of said M alternate memory elements has a
defective memory cell and for outputting said information in accordance
with said address signal;
N second bus lines each carrying one-bit data; and
bus line switching means, provided between said M first bus lines and N
second bus lines and connected to said memory means, for determining
whether each of said at least M blocks designated by said designating
means has a defective memory cell by referring to said information from
said memory means and for selectively connecting N of said M first bus
lines to said N second bus lines so that one of said M blocks which has a
defective memory cell is prevented from being selected and so that an
alternate one of said M blocks of an alternate one of said M alternate
memory elements is selected,
said bus line switching means including N switches each connected between L
(L is an integer and L<N<M) internal bus lines among said M internal bus
lines and one of said N external bus lines, each of said N switches
connecting one of said L internal bus lines to said one of said N external
bus lines in accordance with said information supplied from said memory
means.
2. A semiconductor memory device storing data having a unit of N bits (N is
an integer), comprising:
M alternate memory elements having a plurality of memory cells (M is an
integer and larger than N), wherein each of said alternate memory elements
are divided into a plurality of blocks, wherein each of said blocks have a
plurality of said memory cells, and wherein each of said memory cells
stores one-bit data;
M first bus lines each carrying one-bit data and connected to a
corresponding one of said M alternate memory elements;
designating means, coupled to said M alternate memory elements, for
receiving an address signal from an external device and for designating
one of said plurality of blocks of each of said M alternate memory
elements so that at least M blocks are designated by said address signal;
memory means for storing information on whether or not each of said
plurality of blocks of each of said M alternate memory elements has a
defective memory cell and for outputting said information in accordance
with said address signal;
N second bus lines each carrying one-bit data; and
bus line switching means, provided between said M first bus lines and N
second bus lines and connected to said memory means, for determining
whether each of said M blocks designated by said designating means has a
defective memory cell by referring to said information from said memory
means and for selectively connecting N of said M first bus lines to said N
second bus lines so that one of said M blocks which has a defective memory
cell is prevented from being selected and so that an alternate one of said
M blocks of an alternate one of said M alternate memory elements is
selected; and
wherein each of said M alternate memory elements has said plurality of
blocks arranged into a matrix.
3. A semiconductor memory device storing data having a unit of N bits (N is
an integer), comprising:
M alternate memory elements having a plurality of memory cells (M is an
integer and larger than N), wherein each of said alternate memory elements
are divided into a plurality of blocks, wherein each of said blocks have a
plurality of said memory cells, and wherein each of said memory cells
stores one-bit data;
M first bus lines each carrying one-bit data and connected to a
corresponding one of said M alternate memory elements;
designating means, coupled to said M alternate memory elements, for
receiving an address signal from an external device and for designating
one of said plurality of blocks of each of said M alternate memory
elements so that at least M blocks are designated by said address signal;
memory means for storing information on whether or not each of said
plurality of blocks of each of said M alternate memory elements has a
defective memory cell and for outputting said information in accordance
with said address signal;
N second bus lines each carrying one-bit data; and
bus line switching means, provided between said M first bus lines and N
second bus lines and connected to said memory means, for determining
whether each of said M blocks designated by said designating means has a
defective memory cell by referring to said information from said memory
means and for selectively connecting N of said M first bus lines to said N
second bus lines so that one of said M blocks which has a defective memory
cell is prevented from being selected and so that an alternate one of said
M blocks of an alternate one of said M alternate memory elements is
selected; and
wherein each of said M alternate memory elements is formed of a memory
chip, and wherein said semiconductor memory device comprises a printed
circuit board on which said M alternate memory elements are mounted.
4. A semiconductor memory device storing data having a unit of N bits (N is
an integer), comprising:
M alternate memory elements having a plurality of memory cells (M is an
integer and larger than N), wherein each of said alternate memory elements
are divided into a plurality of blocks, wherein each of said blocks have a
plurality of said memory cells, and wherein each of said memory cells
stores one-bit data;
M first bus lines each carrying one-bit data and connected to a
corresponding one of said M alternate memory elements;
designating means, coupled to said M alternate memory elements, for
receiving an address signal from an external device and for designating
one of said plurality of blocks of each of said M alternate memory
elements so that at least M blocks are designated by said address signal;
memory means for storing information on whether or not each of said
plurality of blocks of each of said M alternate memory elements has a
defective memory cell and for outputting said information in accordance
with said address signal;
N second bus lines each carrying one-bit data; and
bus line switching means, provided between said M first bus lines and N
second bus lines and connected to said memory means, for determining
whether each of said M blocks designated by said designating means has a
defective memory cell by referring to said information from said memory
means and for selectively connecting N of said M first bus lines to said N
second bus lines so that one of said M blocks which has a defective memory
cell is prevented from being selected and so that an alternate one of said
M blocks of an alternate one of said M alternate memory elements is
selected; and
wherein each of said M alternate memory elements is formed of an integrated
circuit block, and wherein said semiconductor memory device comprises a
wafer-scale chip on which said M alternate memory elements are formed.
5. A semiconductor memory device storing data having a unit of N bits (N is
an integer), comprising:
n.times.M alternate memory elements each having a plurality of memory cells
(n being an integer, and M being an integer and larger than N), each of
said alternate memory elements being divided into a plurality of blocks,
each of said blocks having a plurality of said memory cells in at least
one column, and each of said memory cells storing one-bit data;
M first bus lines each carrying one-bit data and connected to corresponding
n memory elements among said n.times.M alternate memory elements so that
said n.times.M alternate memory elements are arranged into a matrix;
designating means, coupled to said n.times.M alternate memory elements, for
receiving an address signal from an external device and for designating
one of said plurality of blocks of each of said n.times.M alternate memory
elements so that at least M blocks are designated by said address signal;
memory means for storing information on whether or not each of said
plurality of blocks of each of said n.times.M alternate memory elements
has a defective memory cell and for outputting said information in
accordance with said address signal;
N second bus lines each carrying one-bit data; and
bus line switching means, provided between said M first bus lines and N
second bus lines and connected to said memory means, for determining
whether each of said at least M blocks designated by said designating
means has a defective memory cell by referring to said information from
said memory means and for selectively connecting N of said M first bus
lines to said N second bus lines so that one of said M blocks which has a
defective memory cell is prevented from being selected and so that an
alternate one of said M blocks of an alternate one of said n.times.M
alternate memory elements is selected,
said bus line switching means including N switches each connected between L
(L is an integer and L<N<M) internal bus lines among said M internal bus
lines and one of said N external bus lines, each of said N switches
connecting one of said L internal bus lines to said one of said N external
bus lines in accordance with said information supplied from said memory
means.
6. A semiconductor memory device storing data having a unit of N bits (N is
an integer), comprising:
n.times.M alternate memory elements (n being an integer, and M being an
integer and larger than N), wherein each of said alternate memory elements
are divided into a plurality of blocks, wherein each of said blocks have a
plurality of said memory cells, and wherein each of said memory cells
stores one-bit data;
M first bus lines each carrying one-bit data and connected to corresponding
n memory elements among said n.times.M alternate memory elements so that
said n.times.M alternate memory elements are arranged into a matrix;
designating means, coupled to said n.times.M alternate memory elements, for
receiving an address signal from an external device and for designating
one of said plurality of blocks of each of said n.times.M alternate memory
elements so that at least M blocks are designated by said address signal;
memory means for storing information on whether or not each of said
plurality of blocks of each of said n.times.M alternate memory elements
has a defective memory cell and for outputting said information in
accordance with said address signal;
N second bus lines each carrying one-bit data; and
bus line switching means, provided between said M first bus lines and N
second bus lines and connected to said memory means, for determining
whether each of said M blocks designated by said designating means has a
defective memory cell by referring to said information from said memory
means and for selectively connecting N of said M first bus lines to said N
second bus lines so that one of said M blocks which has a defective memory
cell is prevented from being selected and so that an alternate one of said
M blocks of an alternate one of said n.times.M alternate memory elements
is selected; and
wherein each of said n.times.M alternate memory elements has said plurality
of blocks arranged into a matrix.
7. A semiconductor memory device storing data having a unit of N bits (N is
an integer), comprising:
n.times.M alternate memory elements (n being an integer, and M being an
integer and larger than N), wherein each of said alternate memory elements
are divided into a plurality of blocks, wherein each of said memory blocks
have a plurality of said memory cells, and wherein each of said memory
cells stores one-bit data;
M first bus lines each carrying one-bit data and connected to corresponding
n memory elements among said n.times.M alternate memory elements so that
said n.times.M alternate memory elements are arranged into a matrix;
designating means, coupled to said n.times.M alternate memory elements, for
receiving an address signal from an external device and for designating
one of said plurality of blocks of each of said n.times.M alternate memory
elements so that at least M blocks are designated by said address signal;
determining means, connected to said memory means, for determining whether
each of said M blocks designated by said designating means has a defective
memory cell by referring to said information from said memory means and
for outputting a control signal indicative of the results of the
determination;
serial data inputting means, coupled to said determining means, for
receiving serial write data and for selectively outputting said serial
write data bit by bit to the blocks of said n.times.M alternate memory
elements not having a defective memory cell in the blocks designated by
said designating means in accordance with said control signal from said
determining means;
serial/parallel converting means, connected to said M first bus lines and
said serial data inputting means, for converting said serial write data
into parallel write data to be supplied to said M first bus lines and for
converting readout data from said M first bus lines into serial readout
data; and
serial data outputting means, coupled to said determining means and said
serial/parallel converting means, for selectively receiving said serial
readout data bit by bit in accordance with said control signal from said
determining means and for outputting said serial readout data to an second
bus line in serial form.
8. A semiconductor memory device as claimed in claim 7, wherein said serial
data inputting means outputs said serial write data until said control
signal shows that said serial write data is to be written into one of said
M blocks which has a defective memory cell, and wherein dummy data is
written into said one of the M blocks instead of said serial write data.
9. A semiconductor memory device as claimed in claim 7, wherein said serial
data outputting means stops outputting said serial readout data when said
control signal shows that said serial write data is read out from one of
said M blocks which has a defective memory cell.
10. A semiconductor memory device as claimed in claim 6, wherein each of
said n.times.M memory elements has said plurality of blocks arranged into
a matrix.
11. A semiconductor memory device storing data having a unit of N bits (N
is an integer), comprising:
M memory elements (M is an integer and larger than N) each divided into a
plurality of blocks each having a plurality of memory cells each storing
one-bit data;
M first bus lines each carrying one-bit data and connected to a
corresponding one of said M memory elements;
designating means, coupled to said M memory elements, for receiving an
address signal from an external device and for designating one of said
plurality of blocks of each of said M memory elements so that M blocks are
designated by said address signal;
memory means for storing information on whether or not each of said
plurality of blocks of each of said M memory elements has a defective
memory cell and for outputting said information in accordance with said
address signal, wherein said information stored in said memory means
includes control data indicating which one of L first bus lines among said
M first bus lines is to be selected on the basis of whether or not each of
said M memory blocks of said M memory elements has a defective memory
cell, wherein said control data includes N numerical data pieces provided
for every M blocks and corresponding to said N second bus lines, and each
of said N numerical data pieces related to a corresponding one of said N
second bus lines indicates which one of said L input terminals is to be
connected to said corresponding one of said N second bus lines;
N second bus lines each carrying one-bit data; and
bus line switching means, provided between said M first bus lines and N
second bus lines and connected to said memory means, for determining
whether each of said M blocks designated by said designating means has a
defective memory cell by referring to said information from said memory
means and for selectively connecting N first bus lines among said M first
bus lines to said N second bus lines so that one of said M blocks which
has a defective memory cell is prevented from being selected and another
one of said M blocks is selected, wherein said bus line switching means
comprises N switches each connected between L (L is an integer and L<N<M)
first bus lines among said M first bus lines and one of said N second bus
lines, wherein each of said switches has L input terminals to which said L
first bus lines are connected, each of said N switches connecting one of
said L first bus lines to said one of said N second bus lines in
accordance with said information supplied from said memory means; and
wherein said memory means has storage areas provided for said N numerical
data pieces and wherein when one of said storage areas of said memory
means corresponding to an i-th second bus line (i=1, 2, . . . ) of said N
second bus line indicates a j-th input terminal (j=0, 1, 2, . . . ) of
said L input terminals, an i-th switch of said N switches which is
connected to an i-th second bus line of said N second bus lines selects an
(i+j)-th first bus line of said M first bus lines.
12. A semiconductor memory device storing data having a unit of N bits (N
is an integer), comprising:
n.times.M memory elements (n being an integer, and M being an integer and
larger than N) each divided into a plurality of blocks each having a
plurality of memory cells each storing one-bit data;
M first bus lines each carrying one-bit data and connected to corresponding
n memory elements among said n.times.M memory elements so that said
n.times.M memory elements are arranged into a matrix;
designating means, coupled to said n.times.M memory elements, for receiving
an address signal from an external device and for designating one of said
plurality of blocks of each of said n.times.M memory elements so that M
blocks are designated by said address signal;
memory means for storing information on whether or not each of said
plurality of blocks of each of said n.times.M memory elements has a
defective memory cell and for outputting said information in accordance
with said address signal, wherein said information stored in said memory
means includes control data indicating which one of L first bus lines
among said M first bus lines is to be selected on the basis of whether or
not each of said M memory blocks of each of said n.times.M memory elements
has a defective memory cell, wherein said control data includes N
numerical data pieces provided for every M blocks and corresponding to
said N second bus lines, and each of said N numerical data pieces related
to a corresponding one of said N second bus lines indicates which one of
said L input terminals is to be connected to said corresponding one of
said N second bus lines;
N second bus lines each carrying one-bit data; and
bus lines switching means, provided between said M first bus lines and N
second bus lines and connected to said memory means, for determining
whether each of said M blocks designated by said designating means has a
defective memory cell by referring to said information from said memory
means and for selectively connecting N first bus lines among said M first
bus lines to said N second bus lines so that one of said M blocks which
has a defective memory cell is prevented from being selected and another
one of said M blocks is selected, wherein said bus line switching means
comprises N switches each connected between L (L is an integer and L<N<M)
first bus lines among said M first bus lines and one of said N second bus
lines, wherein each of said switches has L input terminals to which said L
first bus lines are connected, each of said N switches connecting one of
said L first bus lines to said one of said N second bus lines in
accordance with said information supplied from said memory means; and
wherein said memory means has storage areas provided for said N numerical
data pieces and wherein when one of said storage areas of said memory
means corresponding to an i-th second bus line (i=1, 2, . . . ) of said N
second bus lines indicates a j-th input terminal (j=0, 1, 2, . . . ) of
said L input terminals, an i-th switch of said N switches which is
connected to an i-th second bus line of said N second bus lines selects an
(i+j)-th first bus line of said M first bus lines.
13. A semiconductor memory device storing data having a unit of N bits (N
is an integer), comprising:
n.times.M memory elements (n being an integer, and M being an integer and
larger than N) each divided into a plurality of blocks each having a
plurality of memory cells each storing one-bit data;
M first bus lines each carrying one-bit data and connected to corresponding
n memory elements among said n.times.M memory elements so that said
n.times.M memory elements are arranged into a matrix;
designating means, coupled to said n.times.M memory elements, for receiving
an address signal from an external device and for designating one of said
plurality of blocks of each of said n.times.M memory elements so that M
blocks are designated by said address signal;
memory means for storing information on whether or not each of said
plurality of blocks of each of said n.times.M memory elements has a
defective memory cell and for outputting said information in accordance
with said address signal;
determining means, connected to said memory means, for determining whether
each of said M blocks designated by said designating means has a defective
memory cell by referring to said information from said memory means and
for outputting a control signal indicative of the results of the
determination;
serial data inputting means, coupled to said determining means, for
receiving serial write data and for selectively outputting said serial
write data bit by bit to the blocks of said n.times.M alternate memory
elements not having a defective memory cell in the blocks designated by
said designating means in accordance with said control signal from said
determining means by outputting said serial write data until said control
signal shows that said serial write data is to be written into one of said
M blocks which has a defective memory cell and by writing dummy data
instead of said serial data into said one of the M blocks which has the
defective memory cell;
serial parallel converting means, connected to said M first bus lines and
said serial data inputting means, for converting said serial write data
into parallel write data to be supplied to said M first bus lines and for
converting readout data from said M first bus lines into serial readout
data; and
serial data outputting means, coupled to said determining means and said
serial/parallel converting means, for selectively receiving said serial
readout data bit by bit in accordance with said control signal from said
determining means and for outputting said serial readout data to an second
bus line in serial form.
14. A semiconductor memory device storing data having a unit of N bits (N
is an integer), comprising:
M alternate memory elements having a plurality of memory cells (M is an
integer and larger than N), wherein each of said alternate memory elements
are divided into a plurality of blocks, wherein each of said memory blocks
have a plurality of said memory cells, and wherein each of said memory
cells stores one-bit data;
M first bus lines each carrying one-bit data and connected to a
corresponding one of said M alternate memory elements;
designating means, coupled to said M alternate memory elements, for
receiving an address signal from an external device and for designating
one of said plurality of blocks of each of said M alternate memory
elements so that M blocks are designated by said address signal;
memory means for storing information on whether or not each of said
plurality of blocks of each of said M alternate memory elements has a
defective memory cell and for outputting said information in accordance
with said address signal;
N second bus lines each carrying one-bit data;
bus line switching means, provided between said M first bus lines and N
second bus lines and connected to said memory means, for determining
whether each of said M blocks designated by said designating means has a
defective memory cell by referring to said information from said memory
means and for selectively connecting N of said M first bus lines to said N
second bus lines so that one of said M blocks which has a defective memory
cell is prevented from being selected and so that an alternate one of said
M blocks of an alternate one of said M alternate memory elements is
selected; and
wherein said bus line switching means comprises N switches each connected
between L (L is an integer and L<N<M) first bus lines among said M first
bus lines and one of said N second bus lines, each of said N switches
connecting one of said L first bus lines to said one of said N second bus
lines in accordance with said information supplied from said memory means.
15. A semiconductor memory device as claimed in claim 14, wherein said
information stored in said memory means includes control data indicating
which one of said L first bus lines is to be selected on the basis of
whether or not each of said M memory blocks of each of said M alternate
memory elements has a defective memory cell.
16. A semiconductor memory device as claimed in claim 14, wherein each of
said switches has L input terminals to which said L internal bus lines are
connected, and said L internal bus lines are adjacent to each other.
17. A semiconductor memory device as claimed in claim 16, wherein said
control data includes N numerical data pieces provided for every M blocks
and corresponding to said N external bus lines, and each of said N
numerical data pieces related to a corresponding one of said N external
bus lines indicates which one of said L input terminals is to be connected
to said corresponding one of said N external bus lines.
18. A semiconductor memory device as claimed in claim 17, wherein said
memory means has storage areas provided for said N numerical data pieces
and wherein when one of said storage areas of said memory means
corresponding to an i-th external bus line (i=1, 2, . . . ) of said N
external bus line indicates a j-th input terminal (i=0, 1, 2, . . . ) of
said L input terminal, an i-th switch of said N switches which is
connected to an i-th external bus line of said N external bus lines
selects an (i+j)-th internal bus line of said M internal bus lines.
19. A semiconductor memory device storing data having a unit of N bits (N
is an integer), comprising:
n.times.M alternate memory elements (n being an integer, and M being an
integer and larger than N), wherein each of said alternate memory elements
are divided into a plurality of blocks, wherein each of said memory blocks
have a plurality of said memory cells, and wherein each of said memory
cells stores one-bit data;
M first bus lines each carrying one-bit data and connected to corresponding
n memory elements among said n.times.M alternate memory elements so that
said n.times.M alternate memory elements are arranged into a matrix;
designating means, coupled to said n.times.M alternate memory elements, for
receiving an address signal from an external device and for designating
one of said plurality of blocks of each of said n.times.M alternate memory
elements so that at least M blocks are designated by said address signal;
memory means for storing information on whether or not each of said
plurality of blocks of each of said n.times.M alternate memory elements
has a defective memory cell and for outputting said information in
accordance with said address signal;
N second bus lines each carrying one-bit data;
bus line switching means, provided between said M first bus lines and N
second bus lines and connected to said memory means, for determining
whether each of said M blocks designated by said designating means has a
defective memory cell by referring to said information from said memory
means and for selectively connecting N of said M first bus lines to said N
second bus lines so that one of said M blocks which has a defective memory
cell is prevented from being selected and so that an alternate one of said
M blocks of an alternate one of said n.times.M alternate memory elements
is selected; and
wherein said bus line switching means comprises N switches each connected
between L (L is an integer and L<N<N) first bus lines among said M first
bus lines and one of said N second bus lines, each of said N switches
connecting one of said L first bus lines to said one of said N second bus
lines in accordance with said information supplied from said memory means.
20. A semiconductor memory device as claimed in claim 19, wherein said
information stored in said memory means includes control data indicating
which one of said L first bus lines is to be selected on the basis of
whether or not each of said M memory blocks of each of said n.times.M
alternate memory elements has a defective memory cell.
21. A semiconductor memory device as claimed in claim 19, wherein each of
said switches has L input terminals to which said L internal bus lines are
connected, and said L internal bus lines are adjacent to each other.
22. A semiconductor memory device as claimed in claim 21, wherein said
control data includes N numerical data pieces provided for every M blocks
and corresponding to said N external bus lines, and each of said N
numerical data pieces related to a corresponding one of said N external
bus lines indicates which one of said L input terminals is to be connected
to said corresponding one of said N external bus lines.
23. A semiconductor memory device as claimed in claim 22, wherein said
memory means has storage areas provided for said N numerical data pieces
and wherein when one of said storage areas of said memory means
corresponding to an i-th external bus line (i=1, 2, . . . ) of said N
external bus line indicates a j-th input terminal (j=0, 1, 2, . . . ) of
said L input terminal, an i-th switch of said N switches which is
connected to an i-th external bus line of said N external bus lines
selects an (i+j)-th internal bus line of said M internal bus lines. |
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Claims |
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Description |
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BACKGROUND OF THE INVENTION
The present invention generally relates to a semiconductor memory device,
and particularly to a large capacity semiconductor memory device suitable
for a storage device in a large-scale computer system. More particularly,
the present invention is concerned with a semiconductor memory device
having information indicative of the presence of defective memory cells
(bits).
Conventionally, much effort to improve the production yield of
semiconductor devices is being made. Presently, a technique which realizes
100% production yield is not available. It is possible to use only
semiconductor memory devices having no defective memory cells. However,
the number of defective memory cells increases with an increase in storage
capacity and thus it is difficult to obtain a large number of
semiconductor memory devices having no defective memory cells. From this
point of view, a semiconductor memory device having redundant bits has
been proposed. Such a semiconductor memory device has a memory cell array
which is divided into a main memory cell array and a redundant memory cell
array. Memory cells in the main memory cell are investigated by a
conventional wafer probing test, and defective memory cells are detected.
The detected defective memory cells are stored in a ROM (read only memory)
provided in the semiconductor memory device. When a defective memory cell
in the main memory cell array is addressed, a redundant bit in the
redundant cell array is actually accessed instead of the addressed
defective memory cell.
FIG. 1 is a block diagram of a conventional semiconductor memory device.
The semiconductor memory device in FIG. 1 includes a memory cell array 10,
which is divided into a main memory cell array 10a and a redundant memory
cell array 10b. The main memory cell array 10a is accessed by a column
decoder 11 and a row decoder 12a. The redundant memory cell array 10b is
accessed by a redundant row decoder 12b and the column decoder 11.
Normally, an address signal from an external circuit (not shown) such as a
central processing unit (CPU) is supplied to the column decoder 11, and
the row decoder 12a through a controller 13 and a switching circuit 14.
Data are read out from or written into memory cells of the main memory
cell array 10a corresponding to the address signal. The controller 13
compares the address signal with addresses stored in a read only memory
(ROM) 13a. When it is determined that the address signal indicates a group
of memory cells including a defective memory cell, the switching circuit
14 supplies the address signal from the controller 13 to the redundant row
decoder 12b. A group of memory cells to be substituted for the group of
memory cells having the defective memory cell is accessed by the column
decoder 11 and the redundant row decoder 12b. Such a replacement is
carried out in a row unit.
Memory cells forming the redundant memory cell array 10b must have no
defective cells. Thus, the redundant memory cell 10b array is configured
by only a limited number of memory cells having no defect. As a result,
the redundant memory cell array 10b can save a limited number of defective
memory cells in the main memory cell array 10a. In order to provide a
large capacity less-expensive semiconductor memory device for use in a
large-scale computer system, it is desired that a semiconductor memory
device having a large number of defective memory cells be used. The
conventional configuration shown in FIG. 1 cannot satisfy such a desire.
In some cases, a large number of the elements each having the
configuration shown in FIG. 1 is used for providing a large capacity
semiconductor memory. In this arrangement, each element has the controller
13, the ROM 13a and the switching circuit 14. This prevents the memory
device from being compactly made and operating at high speeds.
SUMMARY OF THE INVENTION
It is a general object of the present invention to provide an improved
semiconductor memory device in which the aforementioned disadvantages are
eliminated.
A more specific object of the present invention is to provide a
less-expensive semiconductor memory device in which memory elements
including defective memory cells are selectively and efficiently replaced
by normal memory elements.
The above-mentioned objects of the present invention are achieved by a
semiconductor memory device storing data having a unit of N bits (N is an
integer), comprising M memory elements (M is an integer and larger than N)
each divided into a plurality of blocks each having a plurality of memory
cells each storing one-bit data; and M internal bus lines each carrying
one-bit data and connected to a corresponding one of the M memory
elements. The semiconductor memory device also comprises designating
means, coupled to the M memory elements, for receiving an address signal
from an external device and for designating one of the plurality of blocks
of each of the M memory elements so that M blocks are designated by the
address signal; and memory means for storing information on whether or not
each of the plurality of blocks of each of the M memory elements has a
defective memory cell and for outputting the information in accordance
with the address signal. The semiconductor memory device further comprises
N external bus lines each carrying one-bit data; and bus line switching
means, provided between the M internal bus lines and N external bus lines
and connected to the memory means, for determining whether each of the M
blocks designated by the designating means has a defective memory cell by
referring to the information from the memory means and for selectively
connecting N internal bus lines among the M internal bus lines to the N
external bus lines so that one of the M blocks which has a defective
memory cell is prevented from being selected and another one of the M
blocks is selected.
The aforementioned objects of the present invention are also achieved by a
semiconductor memory device storing data having a unit of N bits (N is an
integer), comprising n.times.M memory elements (n is an integer, and M is
an integer and larger than N) each divided into a plurality of blocks each
having a plurality of memory cells each storing one-bit data; M internal
bus lines each carrying one-bit data and connected to corresponding n
memory elements among the n.times.M memory elements so that the n.times.M
memory elements are arranged into a matrix; and designating means, coupled
to the n.times.M memory elements, for receiving an address signal from an
external device and for designating one of the plurality of blocks of each
of the n.times.M memory elements so that M blocks are designated by the
address signal. The semiconductor memory device also comprises memory
means for storing information on whether or not each of the plurality of
blocks of each of the n.times.M memory elements has a defective memory
cell and for outputting the information in accordance with the address
signal; and N external bus lines each carrying one-bit data. The
semiconductor memory device further comprises bus line switching means,
provided between the M internal bus lines and N external bus lines and
connected to the memory means, for determining whether each of the M
blocks designated by the designating means has a defective memory cell by
referring to the information from the memory means and for select | | |
