N-dimensional multi-port memory - Patent Review 5303200

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. A memory circuit, in which data are accessed as if stored in an array of at least three dimensions, comprising:

(a) a plurality of memory elements, each memory element storing at least one bit of data, the memory elements being logically organized in a plurality of sets of parallel memory planes in said array, the parallel memory planes in each set being logically orthogonal to the parallel memory planes in the other sets;

(b) a plurality of address busses, each address bus conveying addresses for memory elements in one of the logically orthogonal sets of parallel memory planes;

(c) data port means for conveying data to and from those memory elements selected by the addresses conveyed on the address busses; and

(d) control means for controlling access of the data port means to the memory elements in accordance with the addresses supplied on the address busses and operative to effect storage and retrieval of data from the memory elements in the logically orthogonal sets of parallel memory planes, wherein the control means prevent simultaneous storage of data into any one of the memory elements that is common to two of the logically orthogonal sets of parallel memory planes.

2. The memory circuit of claim 1, wherein the data port means comprise at least two ports and each of the at least two ports provides access to and from a different one of the logically orthogonal sets of parallel memory planes, the location of each of the memory elements in the array being defined by a row, a column, and a bit plane in which the memory element is disposed.

3. The memory circuit of claim 2, wherein the data port means convey data to and from selected ones of the memory elements that are at locations defined by a row address and a column address, and to and from selected ones of the memory elements that are at locations defined by a row address and a bit plane address.

4. The memory circuit of claim 3, wherein at least one port of the data port means comprises a pixel port and at least another port of the data port means comprises a bit plane port, and wherein said control means are further operative to allow a number, p, of selected ones of the memory elements comprising a pixel to be accessed for storage or retrieval through the pixel port, and a number, b, of selected ones of the memory elements, each comprising a bit plane element, to be accessed for storage or retrieval through the bit plane port.

5. The memory circuit of claim 2, wherein data are transferred through a selected one of the at least two ports at a time.

6. The memory circuit of claim 1, wherein data stored and retrieved from at least one of the logically orthogonal sets of parallel memory planes are transferable through the data port means in a parallel data stream.

7. The memory circuit of claim 1, wherein data stored and retrieved from selected ones of the memory elements in the logically orthogonal sets of parallel memory planes are transferable through all of the data port means in a parallel data stream.

8. The memory circuit of claim 2, wherein said at least two ports provide independent access to the same data.

9. The memory circuit of claim 4, wherein the data stored in the memory elements represent an image.

10. The memory circuit of claim 1, wherein the memory elements are physically disposed in a plurality of separate blocks and the control means include addressing means for controlling access of the data port means to the memory elements of each block by multiplexing an address between the plurality of separate blocks, disposition of the memory elements into said separate blocks enhancing an access speed for reading and writing data to the memory elements.

11. An integrated circuit for storing and accessing data represented as if stored in an N-dimensional array, comprising:

(a) data storage means for selectively writing the data at specified locations in the circuit, where the locations are uniquely defined by N coordinates so that the data are represented as being stored in one of a plurality of memory planes comprising the N-dimensional array, the memory planes being organized as logically orthogonal sets of memory planes, whereby the data can subsequently be retrieved and read from said specified locations;

(b) address means for identifying each of said specified locations with a plurality of the coordinates that comprise an address identifying a location in one of the memory planes in the logically orthogonal sets of memory planes;

(c) input/output means, including a plurality of ports each of which conveys data to and from the data storage means, for storage and retrieval at the specified locations identified by the coordinates; and

(d) multiplexing means for controlling access of the input/output means to the data in accordance with the addresses of the data so that each port conveys data for a different set of the logically orthogonal sets of memory planes.

12. The integrated circuit of claim 11, wherein the multiplexing means prevent data from different ports being simultaneously written to a particular location in the data storage means.

13. The integrated circuit of claim 11, wherein N equals three and the input/output means include at least two ports.

14. The integrated circuit of claim 13, wherein one of the two ports conveys data to and from the specified locations for one set of the logically orthogonal sets of memory planes and the other port conveys data to and from the specified locations for another set of the logically orthogonal sets of memory planes.

15. The integrated circuit of claim 13, wherein both ports convey data in a parallel format to and from the specified locations for each set of the logically orthogonal sets of memory planes.

16. The integrated circuit of claim 13, wherein the data written into the data storage means represents an image and one of the two ports conveys pixel data and the other of the two ports conveys bit plane data for the image.

17. The integrated circuit of claim 16, wherein the addresses for the pixel data that are conveyed through said one of the two ports define the specified location in one of the memory planes by a row and a column address, and the addresses for the bit plane data that are conveyed through said other port define the specified location in another of the memory planes by a row and a bit plane address.

18. The integrated circuit of claim 16, wherein the data storage means comprise a plurality of memory cells, each memory cell storing one bit of data, said pixel data comprising p bits of data that are writeable and readable in a parallel format, and said bit plane data comprising b bits of data that are writeable and readable in parallel format.

19. The integrated circuit of claim 11, wherein data are simultaneously conveyed to and from the data storage means through at least two ports.

20. The integrated circuit of claim 11, wherein data are conveyed to and from the data storage means through only one of the plurality of ports at a time.

21. The integrated circuit of claim 11, wherein the locations to which data are written are physically disposed in a plurality of separate blocks; and wherein the multiplexing means include addressing means for writing and retrieving the data from the separate blocks, the speed with which the data are written and retrieved being thereby enhanced.

22. A dual port memory integrated circuit, wherein data are represented as being organized and stored in a three-dimensional array, comprising:

(a) a plurality of random access memory cells;

(b) a first port for conveying data stored in the random access memory cells from the integrated circuit;

(c) a second port for conveying data stored in the random access memory cells from the integrated circuit;

(d) a first address bus that conveys first port addresses, each first port address identifying a specific random access memory cell in terms of coordinates defining a location in a first set of planes represented as being parallel to each other;

(e) a second address bus that conveys second port addresses, each second port address identifying a specific random access memory cell in terms of coordinates defining a location in a second set of planes represented as being parallel to each other and logically orthogonal to the first set of planes in the three-dimensional array; and

(f) read enable means for controlling the times at which the data stored in the random access memory cells of the first and the second set of planes are read and conveyed through the first and the second ports.

23. The dual port memory integrated circuit of claim 22, wherein the first port conveys data from locations within each of the first set of planes at addresses defined by a row and a column, and wherein the second port conveys data from locations within each of the second set of planes at addresses defined by a row and a bit plane.

24. The dual port memory integrated circuit of claim 22, wherein the first port conveys data, p bits at a time, and the second port conveys data, b bits at a time.

25. The dual port memory integrated circuit of claim 23, wherein the first and the second ports convey data into the integrated circuit for storage at specified random access memory cells in the first and the second set of planes, respectively, said specified locations being defined by the first and the second port addresses respectively conveyed on the first and the second address busses, and write enable means for controlling the times at which the data are conveyed to the specified locations and stored therein.

26. The dual port memory integrated circuit of claim 22, wherein the data stored in the random access memory means represent an image, said data conveyed through the first port representing pixels of the image, and the second port conveying data representing bit planes of the image.

27. The dual port memory integrated circuit of claim 22, wherein both of the ports convey data in a parallel format.

28. The dual port memory integrated circuit of claim 22, wherein the plurality of random access cells are disposed in a plurality of physically separate blocks, the first and second port address determining which of the separate blocks are addressed when the data are stored and read, thereby enhancing the speed with which the data are stored and read.

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FIELD OF THE INVENTION

This invention generally pertains to an integrated circuit for electronically storing data, and more specifically, to a memory device having a plurality of ports for accessing the data stored therein.

BACKGROUND OF THE INVENTION

One of the more important applications for integrated circuit memory devices is in the field of image processing. In an image processing system, a video sensing device (e.g., an array of charge coupled devices or a video camera) typically produces image data as an analog signal that is digitized by an analog-to-digital (A-D) converter and stored in a memory circuit in a pixel representation, as a two-dimensional array of gray scale values. Efficient processing of the image data is often best implemented on bit-serial arithmetic units (processors), which offer the advantages of variable sized arguments and a small number of input/output pins. The bit-serial processors require the image data to be read one bit (bit plane) at a time so that their input is a serial data stream, starting with the least significant bit (LSB) and proceeding through the most significant bit (MSB) by taking successive bit slices of the pixels. By using one bit-serial processor for each column of the image, one row of a bit plane image can be read at a time, as each bit-serial processor simultaneously receives a bit of the same significance (e.g., the fifth bit of all of the pixels on a row). Unfortunately, use of bit-serial processors requires that information comprising the image data be converted from the pixel representation to the bit plane representation, and then back to pixel representation, for display on a monitor.

For example, the pixel representation of image data may comprises a 128.times.128 array of eight-bit pixels. In contrast, the corresponding bit plane representation of this image data would be eight bit planes, each including a 128.times.128 array of one-bit data.

Clearly, the pixel representation and the bit plane representation of image data are different formats that require accessing the bits of the image data differently. Thus, a typical image processing system uses a number of serial-to-parallel and parallel-to-serial converters to convert image data between the two representations. Provision of a memory circuit that eliminates the need for such conversions and allows both pixel and bit slice data to be stored and retrieved as parallel data would thus contribute a significant improvement to the current state of the art by enhancing the speed with which the image data are stored and accessed, particularly for the bit plane representation.

Presently, memory devices are not commercially available that can access data stored in memory selectively in either a pixel or a bit plane representation. In U.S. Pat. No. 4,641,282, a memory system is disclosed for use in a display or printing system for processing graphics data. The memory system has a plurality of memory planes, each provided with an operation circuit that performs logical operations on the picture data stored in each memory plane and simultaneously writes the results in the memory planes. However, there is no provision for reading the memory planes as gray scale data, i.e., there is no access to the data in a parallel format, in pixel representation.

In U.S. Pat. No. 4,623,990, a single-array memory includes a storage cell providing dual read/write access via either an "A" side or a "B" side. Thus, the memory cell allows the same data to be accessed through two ports, but only in the same format or representation. The idea is extended in U.S. Pat. No. 4,610,004, which discloses an integrated circuit having two read ports and two write ports, again allowing data to be accessed in the same format or representation through multiple ports; the device enables data to be accessed at different addresses according to the phase of an "A" side or "B" side clock.

Bit slice data are written to a plurality of memory devices and then accessed in pixel representation in U.S. Pat. No. 4,509,043. One or more bit planes selected to constitute a group define a "surface," and similarly, another group of one or more bit planes defines another surface. The priority of the surfaces is identified so that one surface appears to overlie the other. Multiple ports are not provided in the memory device and therefore, access of the image data selectively in either bit plane or pixel representation through different ports is precluded.

A multi-dimensional parallel storage device is disclosed in U.S. Pat. No.4,570,236. An address computing circuit is provided for each multi-dimensional element produced by scanning an image according to a scanning pattern, enabling the recursive computation of a storage element or a reference array point for a linear storing function to occur after shifting of a window in the displayed image. The data are processed as vectors, allowing multiple storage elements to be simultaneously accessed in vector form, but through only one part.

Advantages of the present invention over the prior art in permitting data stored in an integrated circuit memory circuit to be accessed selectively in bit plane or pixel representation through different ports will be apparent from the attached drawings and the Description of the Preferred Embodiment that follow.

SUMMARY OF THE INVENTION

In accordance with the present invention, a memory circuit is provided in which data are accessed as if stored in an array of at least three dimensions. The circuit includes a plurality of memory elements, each storing at least one bit of data. Each of a plurality of address busses conveys addresses for specific memory elements that are organized in one of a plurality of sets of parallel memory planes in the array. Each set of the parallel memory planes is orthogonal to other sets of parallel memory planes. Data port means are operative to convey data to and from memory elements in the memory planes selected by the addresses conveyed on the address busses. The data port means store and retrieve data from the memory elements that are organized in different orthogonal sets of parallel memory planes. Multiplexing means control access of the data port means to the memory elements in accordance with the addresses supplied on the address busses and are operative to effect storage and retrieval of data from the memory elements in orthogonal sets of the memory planes.

In one preferred form of the invention, there are two orthogonal sets of memory planes and at least two ports. The location of each memory element in the array is then defined by a row, a column, and a bit plane in which each memory element is disposed. The data port means convey data to and from selected memory elements that are at locations defined by row and column addresses, and to and from memory elements that are at locations defined by row and bit plane addresses. At least one port of the data port means comprises a pixel port and at least another port of the data port means comprises a bit plane port. The multiplexing means are further operative to allow a number, p, of memory elements comprising a pixel to be accessed for storage or retrieval through the pixel port, and a number, b, of memory elements, each comprising a bit plane element to be accessed for storage or retrieval through the bit plane port.

In one form of the invention, data stored and retrieved from memory elements addressed in either of the orthogonal sets of memory planes are transferable through the data port means in a parallel data stream. The memory elements are preferably divided between a plurality of separate blocks, the multiplexing means including addressing means for multiplexing the separate blocks. The memory circuit can thereby access the data at an enhanced speed, compared to prior art devices.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic view of a virtual arrangement for a two port, three-dimensional memory in accordance with the present invention;

FIG. 2 is a block diagram of functional elements of the three-dimensional memory, as implemented in an integrated circuit for a preferred embodiment;

FIG. 3 is a schematic representation of a preferred embodiment of the three-dimensional memory, wherein two blocks of memory cells (each 128 columns.times.256 rows) are included, providing a total memory of 64K bits;

FIG. 4 is a schematic block diagram illustrating the interconnection of components comprising the memory circuit;

FIG. 5 is a schematic block diagram of an input circuit for pixel and bit slice data;

FIG. 6 is a schematic block diagram of a multiplexer circuit for the bit slice data, which is used to select between the "upper" and "lower" blocks of memory cells;

FIG. 7 is a schematic diagram of a four-way multiplexer circuit used to select the "left" or "right" portion of the "upper" or "lower" blocks of memory cells for writing or reading pixel data;

FIG. 8 is a schematic block diagram of the row decoder used for selecting a row of memory cells in each block of memory;

FIG. 9 is a more detailed block diagram illustrating the selection of memory cells for pixel and bit slice data for each block of memory;

FIG. 10 is a schematic diagram of the memory block and column selection circuitry for the pixel and bit slice data;

FIG. 11A is a representative schematic diagram of circuitry used to select a column in one group for storage or retrieval of bit slice data;

FIG. 11B is a representative schematic diagram of circuitry used to select all columns in one group for storage or retrieval of pixel data;

FIG. 12 is a representative schematic diagram of a circuit used to select a row in the blocks of memory cells; and

FIG. 13 is a representative schematic diagram of a column selection circuit for storing or reading either pixel or bit slice data.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

The virtual architecture of a first preferred embodiment of a dual port, three-dimensional memory array is generally illustrated at reference numeral 18 in FIG. 1. Although the memory elements comprising the dual port, three-dimensional memory array are not physically organized as visually represented in FIG. 1, the data are logically stored and accessed therein as if arranged in a plurality of pixel planes 20a through 20p, and in a plurality of bit planes 22 (only one of which is shown in an exemplary manner, to simplify the illustration) that are orthogonal to the pixel planes. Whether in pixel or bit slice representation, in the preferred embodiment, the data are preferably accessed in parallel format as if stored in one of 512 rows 28, eight bits at a time, as pixel data bits (p) through a pixel port 24, or 16 bits at a time, as bit slice data bits (b) through a bit plane port 26.

It will be apparent to those of ordinary skill in the art that the pixel data can alternatively comprise 4, 12, 24, 32, or some other number of bits per pixel. Similarly, the bit slice data may be stored and accessed in other than 16-bit increments. Furthermore, three-dimensional memory array 18 may include either fewer or more rows than the 512 rows of data used in the preferred embodiment. Such changes certainly impact upon the physical design of the dual port, three-dimensional memory as implemented in an integrated circuit (IC), but are clearly within the broader concept of this invention and achieved by simply modifying the preferred embodiment, as will be apparent to one of ordinary skill in the art, given the following description.

With reference to the virtual configuration of three-dimensional memory 18 shown in FIG. 1, the 512 rows.times.16 pixel planes are able to store 8,192 eight-bit pixels of data. However, the same data represent 4,096 bit slices (16 bits each). The pixels are addressed by the specific pixel plane 20a through 20p and the row 28 in which they are found using a 13-bit address. The bit slice data are addressed in terms of the bit plane (0 through 7) and the row 28 (ranging from 0 through 511) on which the data are stored, by a 12-bit address.

Unlike prior art memory devices, dual port, three-dimensional memory array 18 can store and read out data in either the pixel or bit slice representation, thereby eliminating the need for external bit-converters to process one representation into the other. As a result, a significant increase in data access and utilization speed is obtained compared to conventional memory circuits, which are used in connection with bit-serial converters, as described above in the Background of the Invention.

Turning now to FIG. 2, a block diagram illustrates the rough physical layout of the functional blocks of an IC implementation of the dual port, three-dimensional memory array in a memory circuit 30. In its preferred form, memory circuit 30 comprises an application specific integrated circuit (ASIC) that includes approximately 394,000 transistors. When operating in a pixel mode, it functions like a conventional 8 Kbyte random access memory (RAM) in which 8-bit pixels are stored, and when operating in a bit plane mode, it functions like a conventional 4K.times.16-bit static RAM that reads and writes 16-bit bit slices. Memory circuit 30 is preferably manufactured using a National Semiconductor.TM. 0.8 micron CMOS foundry process. The memory circuit was actually designed for the 1.0 micron process and then scaled down to the 0.8 micron process to achieve the desired speed for storing and accessing image data.

Substantial enhancements in speed, reduction in layout complexity, and shortened critical signal paths are obtained in the preferred embodiment of memory circuit 30 by using two generally conventional 32 K bit static random access memory (SRAM) arrays for data storage, including a lower memory block 32a and an upper memory block 32b. The terms "lower memory block" and "upper memory block" refer to the relative significant bits of the row address for data, the lower block being used to store data in the first 256 rows (0 through 255) and the upper block being used to store data in the second 256 rows (256 through 511). This arrangement enables a symmetrical distribution of data in each of the 32K bit memory blocks so that the data are stored or read as pixels through pixel column input/output circuitry 36a/36b disposed at one end of the memory blocks, and as bit slices through bit plane input/output circuitry 38a/38b disposed at the opposite end of each block. Row decoders 34a and 34 b are disposed adjacent each of memory blocks 32a and 32b. A clocks and controls block 40 is disposed between the two SRAM memory blocks, providing the shortest possible signal path between the controls and the row and column decoders of blocks 34, 36, and 38.

The preferred embodiment of the dual port, three-dimensional memory implemented in memory circuit 30 does not permit the simultaneous access of data through the pixel and bit plane ports. However, it will be apparent to those of ordinary skill in the art that the preferred embodiment disclosed herein can readily be modified to permit simultaneous access of data through the pixel and bit plane ports. Instead, a pixel/bit plane signal input to a pixel/bp selector circuit 42 determines the mode that is active at any one time, both for writing and for reading data. External crystal controlled clock signals and control signals from an external source (such as a central processing unit-not shown) are input to a clock and control input block 44. Separate bit plane and pixel clocks are used in memory circuit 30 to allow the two modes to operate at different frequencies.

The 12-bit address required for selecting bit slice data during read and write operations is input through input buffers in blocks 46 and 48. Bits 12-4 of this address (the row address) is multiplied with bits 12-4 of the pixel address, controlled by the pixel/bp signal in block 50.

The multiplexed row address and bit slice addresses 1-3 are then stored in an address register, also in block 50. In addition, block 50 includes a bit plane output multiplexer. The first six bits of bit slice data are processed through a bit plane input port 52, and the remaining ten bits are processed through a bit plane input port 54. The bit slice data are stored in memory blocks 32a or 32b at memory cell locations determined by the multiplexed row address and the bit plane address (1-3) stored in the address register in block 50.

In a similar manner, during operation in the pixel mode, pixel data are stored or read from memory cells determined by a pixel address input to a block 62 (for address bits 0 through 3) and to a block 64 (for address bits 12 through 4). Pixel data are input through a pixel input port 68, for storage at the memory cell locations defined by the address input to a block 66. As explained below, multiplexed address bit 12 determines the specific memory block 32a or 32b at which the pixel or bit slice data are stored or retrieved.

Before storage in the specific memory cells selected by the address, bit slice data are processed through a bit plane data input register 56, and pixel data are processed through a pixel data input register 70. Bit plane data input register 56, pixel data input register 70, and address registers 50 and 66 include time delay circuits (not shown in FIG. 2) that provide an appropriate time delay so that all inputs (address and data) can have a zero hold time.

Bit slice data are output through a bit plane output port, which is divided between a block 58a for bits 0 through 7 and a block 58b for bits 8 through 15. During operation in the pixel mode, the pixel bits 0 through 7 are output through a pixel output port 72.

In FIG. 3, the organization of data stored in memory blocks 32a and 32b is shown. Lower memory block 32a includes 16 groups of columns 96a through 96p, each group having eight columns organized into 256 rows of memory cells. Similarly, upper memory block 32b comprises 16 groups 98a through 98p, with eight columns per group, also organized into 256 rows of memory cells. Thus, each memory block includes 128 columns.times.256 rows.

The 13-pixel address bits are split between bits 0 through 3 and bits 4 through 12. The first four bits 0 through 2 are input over lines 102a and 102b to memory blocks 32a and 32b, respectively, and bits 4 through 11 of the pixel address are input over lines 92 to a first input of a 2:1 multiplexer block 90. Likewise, the first three bits 1 through 3 of the bit plane address are input over lines 104a and 104b, and the remaining bits 4-11 of the bit plane address are input on lines 94 to a second input of 2:1 multiplexer 90. Depending upon whether the bit plane or pixel mode is selected, 2:1 multiplexer block 90 selects one of the sets of address lines 92 or 94 to determine the row address. The row address is conveyed on lines 100 to both memory blocks 32a and 32b.

Since the same row address is input to both of the memory blocks, one of the two memory blocks must be selected for a read or write operation in either the pixel or bit plane mode. Accordingly, pixel address bit 12 is input to a 4:1 multiplexer block 66a, causing it to select the lower or upper memory block 32a or 32b. In addition, 4:1 multiplexer block 66a receives pixel address bit three, enabling it to determine whether the pixel data should be read or written from or to a left or right portion of the selected lower or upper memory block. In a similar fashion, the 12th bit of the bit plane address is input to a 2:1 multiplexer circuit 50, causing it to select between memory blocks 32a and 32b for storage or retrieval of bit slice data. Thus, although the row in each of the memory cell blocks is selected based on bits 4 through 11, other bits in the address determine whether memory cells in the lower or upper memory blocks are being selected, and in the case of pixel data, whether the pixel data are to be written to or read from among the left eight groups (96a through 96h)/(98a through 98h) of the lower or upper memory block, respectively, or written to or read from among the right eight groups (96i through 96p)/(98i through 98p) of the lower or upper memory blocks, respectively.

Turning now to FIG. 4, the relationship between clock and controls block 40 and the other portions of circuit 30 is shown. Clocks and controls block 40 includes a number of input and output terminals, identified by acronyms in Table 1, as follows:

TABLE 1 ______________________________________ SIGNAL ACRONYM DEFINITION LINE(S) ______________________________________ ##STR1## Pixel Write Enable - Bar 106 PIX/BIT Pixel/Bit Plane Mode Select 108 ##STR2## Pixel Mode Enable - Bar 110 PCLK Pixel Clock 112 PA3 Pixel Address Bit Three 102 PA12 Pixel Address Bit Twelve 102 ##STR3## Bit Plane Write Enable - Bar 114 ##STR4## Bit Plane Mode Enable - Bar 116 BCLK Bit Plane Clock 118 BA12 Bit Plane Address Bit Twelve 104 WRUR Write Upper Right Portion Memory 119 WRUL Write Upper Left Portion Memory 120 ##STR5## Write Pixel Enable - Bar 122 WRLR Write Lower Right Portion Memory 124 WRLL Write Lower Left Portion Memory 126 WRBU Write Bit Plane Upper Memory 128 WRBL Write Bit Plane Lower Memory 130 PIXZ Hi-Impedance (on Pixel Ports) N/A PCLKD Pixel Data Clock Signal 131 PA3I Pixel Address Bit Three 134 PCLKA Pixel Address Clock Signal 132 PA12I Pixel Address Bit Twelve 136 MCLKA Multiplexer Clock Signal 138 BPZU Hi-Impedance (on Bit Plane Ports) N/A BPZL Hi-Impedance (on Bit Plane Ports) N/A BCLKD Bit slice data Clock Signal 140 BCKLD Bit Plane Address Clock Signal 142 BA12I Bit Plane Address Bit Twelve 144 PIX ADD Pixel Address 92 BIT ADD Bit Plane Address 94 PIX DATA Pixel Data 146 BIT DATA Bit slice data 152 LPADD Lowest Bits Pixel Address 156 ADD Row Address 158 BDATA Bit slice data 160 PDATA Pixel Data 154 RPD.sub.IN Right Portion Input Pixel Data 154a LPD.sub.IN Left Portion Input Pixel Data 154b D.sub.IN Bit Slice Input Data 160 RPD.sub.OUT Right Pixel Output Data 162a LPD.sub.OUT Left Pixel Output Data 164a BD.sub.OUT Bit Slice Output Data 166b ______________________________________

As is conventional, the specific bit or range of bits comprising a signal is identified in the figures by a number enclosed in parentheses. For example, pixel address bit 3, which is conveyed on one of lines 102 to the input of clocks and controls 40, is identified by "PA(3)." Another of lines 102 conveys pixel address bit 12, identified by "PA(12)."

The 12th bit of the bit plane address is input to clocks and controls block 40 over line 104. Also input are a pixel write enable signal, which is input on a line 106; a pixel/bit plane mode select signal, input on a line 108; a pixel mode enable signal, conveyed on a line 110, and a pixel clock signal, which is input on a line 112. A bit plane write enable signal is input to clocks and controls block 40 on a line 114, and a bit plane mode enable signal is input on a line 116. A bit plane clock signal is applied on a line 118. Clocks and controls block 40 uses these clock and input signals to develop various control signals, including the following: a pixel write enable signal for the right portion of upper memory block 32b, conveyed on a line 119; a pixel write enable signal for the left portion of memory block 32b, conveyed on a line 120; an inverted logic write pixel enable signal (inverted logic signals are represented by use of a bar over the identifying acronym, e.g., WRP) conveyed on a line 122; a pixel write enable signal for the right portion of, lower memory block 32a, conveyed on a line 124; a pixel write enable signal for the left portion of lower memory block 32a conveyed on a line 126; a bit plane write enable signal for upper memory block 32b, conveyed on a line 128; and, a bit plane write enable signal for lower memory block 32a, conveyed on a line 130.

In addition, the following control signals are provided by clocks and controls block 40: a pixel address clock signal is output on a line 132; pixel address bits 3 and 12 are output on lines 134 and 136, respectively; a multiplexer clock signal is output on a line 138, which is connected to 2:1 multiplexer 90; a bit slice data clock signal is output on a line 140; a bit plane address clock signal is conveyed by a line 142; and bit plane address bit twelve is output on a line 144. Clocks and controls block 40 also generates three other signals labeled PIXZ, BPZU, and BPZL. During each clock cycle, these three signals are applied to the pixel and bit plane output ports, respectively, any time that the corresponding port is not in use for output of data, thereby causing the port to have a high impedance (in excess of 10 megohms). The pixel and bit plane ports are tri-state, having an output for each bit that is either a logic level 0, a logical level 1, or a high impedance.

The mode under which circuit 30 operates is determined primarily by the PIX/BIT signal input to clocks and control