While data cannot be transmitted down a scan chain through a stuck-at fault location, data in properly operating latches downstream of the stuck-at fault location can be shifted down the chain. By varying operating parameters, such as power supply and reference voltages, clock timing patterns, temperature and timing sequences, one or more latches down the SRL chain from the stuck-at fault location may be triggered to change state from the stuck-at fault value. The SRL chain is then operated to shift data out the output of the SRL chain. The output is monitored and any change in value from the stuck-at state is noted as identifying all good latch positions to end of the chain. The process is repeated: varying each of the selected operating parameters until the latch position following the stuck-at fault latch is identified.

A pin-scan-in system driving circuit drives a pin-scan-in circuit to test short-circuit of the wirings or breaking of the wirings in the circuit-mounting substrate, and this circuit is driven using a reduced number of gates. The pin-scan-in system driving circuit drives the pin-scan-in circuit provided in an LSI logic circuit, and the LSI logic circuit is provided with a pin-scan-in circuit selector which selects the pin-scan-in circuit and a selected condition-holding circuit which holds the condition selected by the pin-scan-in circuit selector.

A circuit for the burn-in test of a semiconductor module, to which burn-in test signals from a burn-in test device can be applied, has memory elements. Each burn-in test signal is assigned at least one memory element, for storage of the respective burn-in test signal that is present. The memory elements are connected to a functional unit, which, through of a corresponding state, indicates whether one of the test signals has been contact-connected defectively. In a further section, the circuit configuration furthermore comprises a test device for checking the functionality of the semiconductor module, and a storage device for storing test results using a pass-fail result. A first programmable element and a second programmable element are provided, for storage of the pass-fail results and of the state of the functional unit. The programmable elements each maintain their stored state after an interruption in the voltage supply and can subsequently be evaluated using their state.

A method and system for diagnosing open defects in logic circuits. The method employs a pair of diagnostic fault models and an associated algorithm to automate the diagnoses of open defects--defects that cause interconnects to be open or high resistance in logic. The two diagnostic fault models, the net and node models, are used to predict potential logic errors that could be caused at the outputs of a logic circuit in the presence of an open defect on any interconnect under consideration in the logic circuit. The predicted errors are combined to form a diagnostic signature set corresponding to the logic circuit. The diagnostic signature set is then compared with a set of errors observed during testing using a diagnostic matching algorithm that ranks the presence of open defects on all interconnects under consideration in the circuit.

An apparatus and method for forcing stuck-at and transient errors at sequential and combinational logic and signal lines in a large scale data processing system. Error forcing is achieved by including a scan-in gate with error input and address lines for each scan point to be tested. A fault signal of adjustable duration is generated and combined in a unique fashion to an existing scan-in signal to permit either stuck-at or transient errors to be forced.