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Claims  |
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What is claimed is:
1. A semiconductor memory device, comprising:
a first memory array formed on a semiconductor substrate, said first memory
array including first memory cells arranged in a plurality of columns;
a second memory array formed on the same semiconductor substrate as said
first memory array, said second memory array including second memory cells
arranged in a plurality of columns corresponding to said plurality of
columns of said first memory array;
a plurality of first bit lines provided corresponding to said plurality of
columns of said first memory array;
a plurality of second bit lines provided corresponding to said plurality of
columns of said second memory array;
a plurality of switching means provided, respectively between said
plurality of first bit lines and said plurality of second bit lines, said
plurality of switching means being divided into a plurality of blocks;
means for receiving an external signal designating the number of blocks;
block selecting means for simultaneously selecting blocks of the number
designated by said external signals out of said plurality of blocks, said
block selecting means comprising:
holding means for taking in and holding said external signal; and
decoding means for decoding a signal held by said holding means and an
address signal indicating any of said plurality of columns in said first
memory array or said second memory array; and
control means for simultaneously turning on said switching means included
in the blocks selected by said selecting means.
2. The semiconductor memory device according to claim 1, wherein said first
memory cells are dynamic-type memory cells, and said second memory cells
are static-type memory cells.
3. The semiconductor memory device according to claim 1, wherein said
control means includes:
transfer controlling signal generating means for generating a transfer
controlling signal for designating inhibition/permission of data transfer
between said first memory array and said second memory array; and
controlling signal generating means for generating a plurality of
controlling signals corresponding to said plurality of blocks in response
to the signal decoded by said decoding means and said transfer controlling
signal; and wherein
each of said plurality of controlling signals is applied to all switching
means included in a corresponding block in a lump.
4. The semiconductor memory device according to claim 3, wherein
said decoded signal includes a plurality of signals corresponding to said
plurality of blocks,
said controlling signal generating means includes a plurality of logical
circuit means provided corresponding to said plurality of blocks each for
generating a logical multiplication signal of a corresponding signal out
of said plurality of signals and said transfer controlling signal,
said plurality of signals include activation signals of a number indicated
by said held signal and deactivation signals of a number which is smaller
than the number of said blocks by the number indicated by said held
signal, and
each of said activation signals activates corresponding logical circuit
means, and each of said deactivation signals deactivates corresponding
logical circuit means.
5. The semiconductor memory device according to claim 4, further
comprising:
a plurality of first sense amplifier means provided corresponding to said
plurality of columns of said first memory array for reading out data from
first memory cells in corresponding columns, respectively; and
a plurality of second sense amplifier means provided corresponding to said
plurality of columns in said second memory array for reading out data from
said second memory cells in corresponding columns, respectively, wherein
each of said plurality of switching means includes;
first transfer gate means provided between said first sense amplifier means
in the corresponding column and said second sense amplifier means in the
corresponding column, and
second transfer gate means provided between said second sense amplifier
means in the corresponding column and said second memory cells in the
corresponding column.
6. The semiconductor memory device according to claim 5, wherein
said transfer controlling signal includes a first controlling signal for
inhibiting/permitting data transfer between said plurality of first sense
amplifier means and said plurality of second sense amplifier means and a
second controlling signal for inhibiting/permitting data transfer between
said plurality of second sense amplifier means and said second memory
array, and wherein
each of said plurality of logical circuit means includes first generating
means for generating a logical multiplication signal of the corresponding
first controlling signal and the corresponding signal out of said
plurality of signals and second generating means for generating a logical
multiplication signal of the corresponding second controlling signal and
the corresponding signal out of said plurality of signals.
7. The semiconductor memory device according to claim 1, wherein said
semiconductor memory device is used as a secondary cache memory.
8. A semiconductor memory device, comprising:
a plurality of blocks formed on the same semiconductor substrate, each of
said plurality of blocks including first memory cells arranged in a
plurality of first columns, second memory cells arranged in a plurality of
first columns, second memory cells arranged in a plurality of second
columns corresponding to said plurality of first columns, a plurality of
first bit lines provided corresponding to said plurality of first columns,
a plurality of second bit lines provided corresponding to said plurality
of second columns, and a plurality of switching means provided,
respectively, between said plurality of first bit lines and said plurality
of second bit lines;
means for receiving an external signal designating the number of blocks;
block selecting means for simultaneously selecting blocks of the number in
accordance with said external signal received by said receiving means out
of said plurality of blocks, said block selecting means comprising:
holding means for taking in and holding said external signal; and
decoding means for decoding a signal held by said holding means and an
address signal indicating any of said plurality of columns in said first
memory cells or said second memory cells; and
control means for simultaneously turning on switching means included in the
blocks selected by said block selecting means.
9. A method of transferring data between first memory cells and second
memory cells in a semiconductor memory device comprising a plurality of
blocks each including said first memory cells arranged in a plurality of
first columns, said second memory cells arranged in a plurality of second
columns corresponding to said plurality of first columns, a plurality of
first bit lines provided corresponding to said plurality of first columns,
and a plurality of second bit lines provided corresponding to said
plurality of second columns, said method of transferring data comprising
the steps of:
indicating the amount of data to be transferred simultaneously between said
first memory cells and said second memory cells;
simultaneously selecting blocks of a number corresponding to said indicated
amount of data, said selecting step comprising the step of:
taking in and holding said number corresponding to said indicated amount of
data; and
decoding said number and an address signal indicating any of said plurality
of columns in said first memory cells or said second memory cells;
reading out data from each of said plurality of first memory cells
arranged, respectively, in said plurality of first columns onto
corresponding one of said first bit lines;
transferring data in said simultaneously selected blocks out of said read
data to corresponding one of said second bit lines; and
writing said transferred data into the second memory cells arranged in the
corresponding second column.
10. The method of transferring data according to claim 9, wherein
said semiconductor memory device further comprises a plurality of switching
means provided, respectively, between said plurality of first bit lines
and said plurality of second bit lines, and wherein
said step of transferring includes the step of simultaneously turning on
the switching means included in said simultaneously selected blocks. |
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Claims |
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Description |
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BACKGROUND OF THE INVENTION
1.Field of the Invention
The present invention relates to semiconductor memory devices, and, more
particularly, to a semiconductor memory device having on the same chip a
DRAM (Dynamic Random Access Memory) and a SRAM (Static Random Access
Memory). Description of the Background Art
Generally, a high-speed memory referred to as a cache memory is provided
between a CPU (Central Processing Unit) and a main memory in a computer or
the like. A main memory generally has a large capacity, so that it is
difficult to implement a main memory with a high-speed memory in respect
of costs, for example. Therefore, a method of increasing the operating
speed of a main memory by using a high-speed memory having a small
capacity is adapted. This high-speed memory having a small capacity is a
cache memory. In execution of a program, a CPU first makes access to a
cache memory. In a case where data of a designated address is in the cache
memory, execution of the program is continued, and, in a case where data
of a designated address is not in the cache memory, execution of the
program is interrupted, and storage data in the cache memory and the main
memory are exchanged so that the data of the designated address is
transferred from the main memory to the cache memory. In many cases, a
semiconductor memory such as a DRAM or the like with a small memory cell
area having advantage in increasing the capacity is used as a main memory,
while a semiconductor memory such as a SRAM or the like in which
importance is attached to the operating speed rather than reduction in the
memory cell area is used as a cache memory.
Conventionally, a cache memory and a main memory are provided on separate
chips, so that it is necessary to provide a bus for transferring data
between the main memory and the cache memory, and, accordingly, the
structure of a storage device including the main memory and the cache
memory is complicated. Therefore, it is proposed to implement a high-speed
memory with a large capacity having a structure more simple than that of
the conventional one by providing a DRAM and a SRAM on the same chip. Such
a high-speed memory with a large capacity is described in Japanese Patent
Laying-Open No. 62-38590 (1987), for example. A high-speed memory with a
large capacity having a structure in which a DRAM and a SRAM are provided
on the same chip is hereinafter referred to as a cache DRAM.
FIG. 5 is a schematic block diagram illustrating the whole structure of a
conventional cache DRAM. Referring to FIG. 5, the cache DRAM includes a
DRAM memory array 100 having memory cells (not shown) arranged in a matrix
of 512 columns.times.512 rows and a SRAM memory array 200 having memory
cells (not shown) arranged in a matrix of 512 columns.times.16 rows. A row
decoder 110 selects one row out of the 512 memory cell rows in DRAM memory
array 100. A column decoder 120 selects one column out of the 512 memory
cell columns in DRAM memory array 100. A sense amplifier.multidot.I/O gate
130 includes sense amplifiers each for amplifying a storage data signal in
DRAM memory array 100 and an I/O gate for performing giving and receiving
of data between DRAM memory array 100 and the outside. One sense amplifier
is provided corresponding to each bit line pair in DRAM memory array 100.
The I/O gate controls giving and receiving of data between each sense
amplifier and the outside.
A row decoder 210 selects one row out of the 16 memory cell rows in SRAM
memory array 200. Column decoder 220 selects one column out of the 512
memory cell columns in SRAM memory array 200. An I/O gate 230 performs
giving and receiving of data between SRAM memory array 200 and the
outside. A data transfer gate 300 performs data transfer between DRAM
memory array 100 and SRAM memory array 200. A data transfer controlling
circuit 310 controls data transfer gate 300 in response to an externally
applied controlling signal TR. A column address buffer 320 designates
memory cell columns to be selected by column decoders 120 and 220 in
response to
externally applied nine bit address signals A0-A8. A row address buffer 330
designates a memory cell row to be selected by row decoder 110 in response
to the externally applied nine bit address signals A0-A8. A row address
buffer 340 designates a memory cell row to be selected by row decoder 210
in response to external four bit address signals A9-A12 other than the
external address signals A0-A8. When data is read from DRAM memory array
100 and when data is read from SRAM memory array 200, all of the sense
amplifiers in sense amplifier.multidot.I/O gate 130 are activated. Bit
line pairs in DRAM memory array 100 and bit line pairs in SRAM memory
array 200 correspond to each other with one-to-one correspondence through
data transfer gate 300.
SRAM memory array 200 is used as the cache memory, and DRAM memory array
100 is used as the main memory. Memory cells arranged in the same row are
connected to the same word line (not shown), and memory cells arranged in
the same column are connected to the same bit line pair (not shown), in
both of DRAM memory array 100 and SRAM memory array 200.
When data is read from DRAM memory array 100, row decoder 110 selectively
activates only one word line corresponding to a memory cell row designated
by row address buffer 330 out of the 512 word lines in DRAM memory array
100. This causes storage data of 512 memory cells included in the one
memory cell row designated by row address buffer 330 out of the memory
cells in DRAM memory array 100 to appear onto corresponding bit line
pairs, respectively. In sense amplifier.multidot.I/O gate 130, column
decoder 120 electrically connects only a sense amplifier, which
corresponds to one bit line pair connected to a memory cell column
designated by column address buffer 320 out of 512 pairs of bit line pairs
in DRAM memory array 100, to the I/O gate. Accordingly, only storage data
in a memory cell included in the column designated by column address
buffer 320 out of storage data in the 512 memory cells is amplified and
then provided to the outside by sense amplifier.multidot.I/O gate 130.
When data is written into DRAM memory array 100, data is externally applied
to the I/O gate in sense amplifier.multidot.I/O gate 130. Row decoder 110
and column decoder 120 operate in the same manner as in the case of
reading data from DRAM memory array 100. Accordingly, the external data
applied to the I/O gate in sense amplifier.multidot.I/O gate 130 is
applied only to one bit line pair designated by column address buffer 320
through a corresponding sense amplifier. Row decoder 110 activates only
one word line corresponding to a memory cell row designated by row address
buffer 330 out of word lines in DRAM memory array 100, so-that the data
applied to the one bit line pair through sense amplifier.multidot.I/O gate
130 is written only into a memory cells included in the memory cell row
designated by row address buffer 330 out of 512 memory cells connected to
that bit line pair.
When data is read from SRAM memory array 200, row decoder 210 and column
decoders 120, 220 operate. Specifically, row decoder 210 selectively
activates only one word line corresponding to a memory cell row designated
by row address buffer 340 out of 16 word lines in SRAM memory array 200.
This causes storage data in 512 memory cells included in the memory cell
row designated by row address buffer 340 out of the memory cells in SRAM
memory array 200 to appear on to corresponding bit line pairs,
respectively. Column decoder 220 electrically connects only one bit line
pair, which corresponds to a memory cell column designated by column
address buffer 320 out of 512 bit line pairs in SRAM memory array 200, to
I/O gate 230. Column decoder 120 operates in the same manner as in the
case of writing data into DRAM memory array 100 and in the case of reading
data from DRAM memory array 100. An output from column address buffer 320
is applied in common to column decoder 120 and 220, so that column
decoders 120 and 220 select bit line pairs, which correspond to each
other, from DRAM memory array 100 and SRAM memory array 200, respectively.
At the same time, data transfer gate 300 is controlled by data transfer
controlling circuit 310 to electrically connect each bit line pair in DRAM
memory array 100 to a corresponding bit line pair in SRAM memory array
200. According to this, data appearing on each bit line pair in SRAM
memory array 200 is transmitted through data transfer gate 300 to a
corresponding bit line pair in DRAM memory 100. Then, the data transmitted
to each bit line pair in DRAM memory array 100 is amplified by a
corresponding sense amplifier in sense amplifier.multidot.I/O gate 130.
Each amplified data is transmitted again through data transfer gate 300 to
a corresponding bit line pair in SRAM memory array 200. Only one bit line
pair selected by column decoder 220 out of bit line pairs in SRAM memory
array 200 is electrically connected to I/O gate 230. Accordingly, in SRAM
memory array 200, only storage data in a memory cell at crossing of the
memory cell column designated by column address buffer 320 and the memory
cell row designated by row address buffer 340 is provided through I/O gate
230 to the outside.
When data is written into SRAM memory array 200, data is externally applied
to I/O gate 230, and row decoder 210, column decoders 220, 120, and data
transfer gate 300 operate in the same manner as in the case of reading
data from SRAM memory array 200. Accordingly, the external data applied to
I/O gate 230 is amplified in sense amplifier.multidot.I/O gate 130 through
a bit line pair corresponding to a memory cell column designated by column
address buffer 320 and then, in SRAM memory array 200, is written into a
memory cell at crossing of the memory cell column designated by column
address buffer 320 and a memory cell row designated by row address buffer
340.
When data is transferred from DRAM memory array 100 to SRAM memory array
200, first, data transfer controlling circuit 310 controls data transfer
gate 300 so that the bit line pairs in DRAM memory array 100 and the bit
line pairs in SRAM memory array 200 are electrically separated. Then, with
the bit line pairs in DRAM memory array 100 and the bit line pairs in SRAM
memory array 200 being electrically separated, row decoder 110 operates,
and the sense amplifiers in sense amplifier.multidot.I/O gate 130 are
activated. This causes storage data in 512 memory cells in a memory cell
row designated by row address buffer 330 to be read onto corresponding bit
line pairs, respectively, in DRAM memory array 100. Then, row decoder 210
operates. This causes only a word line corresponding to a memory cell row
designated by row address buffer 340 to be activated in SRAM memory array
200. Subsequently, data transfer controlling circuit 310 controls data
transfer gate 300 so that the bit line pairs in DRAM memory array 100 and
the bit line pairs in SRAM memory array 200 are electrically connected to
each other. As a result, data read onto respective bit line pairs in DRAM
memory array 100 are written through data transfer gate 300 into memory
cells connected to the one activated word line in SRAM memory array 200.
Specifically, storage data in memory cells in one row in DRAM memory array
100 are transferred in a lump into memory cells in one row in SRAM memory
array 200.
When data is transferred from SRAM memory array 200 to DRAM memory array
100, first, data is read from SRAM memory array 200. Specifically, in a
period during which data transfer controlling circuit 310 controls data
transfer gate 300 so that the bit line pairs in DRAM memory array 100 and
the bit line pairs in SRAM memory array 200 are electrically separated,
row decoder 210 operates. This causes only a word line corresponding to a
memory cell row designated by row address buffer 340 to be activated in
SRAM memory array 200, so that storage data in 512 memory cells included
in the designated memory cell row appear onto corresponding bit line
pairs, respectively. Then, row decoder 110 operates, and the sense
amplifiers in sense amplifier.multidot.I/O gate 130 are activated.
According to this, in DRAM memory array 100, a word line corresponding to
a memory cell row designated by row address buffer 330 is activated, and
it becomes possible that data appearing on respective bit line pairs are
amplified in sense amplifier.multidot.I/O gate 130. Then, data transfer
controlling circuit 310 controls data transfer gate 300 so that the bit
line pairs in DRAM memory array 100 and the bit line pairs in SRAM memory
array 200 are electrically connected. This causes the data appearing on
respective bit line pairs in SRAM memory array 200 to be written through
data transfer gate 300 into memory cells connected to the one activated
word line in DRAM memory array 100. Specifically, storage data in memory
cells in one row in SRAM memory array 200 are transferred in a lump to
DRAM memory array 100.
FIG. 6 is a circuit diagram illustrating the relations of connection
between a SRAM memory array and a DRAM memory array in such-a conventional
cache DRAM. Referring to FIG. 6, each of sense amplifiers 135 is provided
corresponding to one of memory cell columns 1000 in DRAM memory array 100.
Each of sense amplifiers 136 is provided corresponding to one of memory
cell columns 2000 in SRAM memory array 200. Sense amplifiers 135 and 136
are included in sense amplifier.multidot.I/O gate 130 in FIG. 5. Two
N-channel MOS transistors 305 and 306 ar provided between each sense
amplifier 135 and a corresponding sense amplifier 136. Two N-channel MOS
transistors 307 and 308 are provided between each sense amplifier 136 and
a corresponding memory cell column 2000 in SRAM 200. Transistors 305 to
308 are included in data transfer gate 300 in FIG. 5. Gate potentials of
transistors 305, 306 and transistors 307, 308 are provided in common from
data transfer controlling circuit 310. Specifically, data transfer
controlling circuit 310 provides a potential at a high level or a low
level in response to an external controlling signal TR to electrically
connect and separate DRAM memory array 100 and SRAM memory array 200. A
differential amplifiers to which two signals of potentials complementary
to each other are applied is used both as sense amplifier 135 and as sense
amplifier 136.
In a mode in which data writing and data reading into/from DRAM memory
array 100 are performed, the output potential of data transfer controlling
circuit 310 attains the low level. Accordingly, transistors 305 and 306
are both turned off, so that each sense amplifier 135 differentially
amplifies the potential of one bit line BLa1 included in a bit line pair
connected to a corresponding DRAM memory cell column 1000 and the
potential of the other bit line BLb1 included in the bit line pair
connected to the corresponding DRAM memory cell column 1000. According to
this, the potentials of bit lines BLa1, BLb1 in each bit line pair become
complementary potentials in accordance with storage data in a memory cell
connected to an activated word line out of the memory cells included in
the corresponding DRAM memory cell column 1000.
In a mode in which data is read from SRAM memory array 200, the output
potential of data transfer controlling circuit 310 attains the high level.
Accordingly, in this case, transistors 305, 306 and transistors 307, 308
are all turned on, so that each sense amplifier 136 supplies to a
corresponding sense amplifier 135 two signals of complementary potentials,
which are obtained by differentially amplifying the potential of one bit
line BLa2 included in a bit line pair connected to a corresponding SRAM
memory cell column 2000 and the potential of the other bit line BLb2
included in the bit line pair connected to the corresponding SRAM memory
cell column 2000, through corresponding transistors 305 and 306. Each
sense amplifier 135 differentially amplifies two output signals of a
corresponding sense amplifier 136. As a result, the potentials of bit
lines BLa2, BLb2 in each bit line pair in SRAM memory array 200 become
complementary potentials in accordance with storage data in a memory cell
connected to an activated word line out of memory cells included in a
corresponding memory cell column 2000.
In a mode in which data is transferred from DRAM memory array 100 to SRAM
-memory array 200, after complementary potentials in accordance with
storage data in each of memory cells connected to an activated word line
in DRAM memory array 100 appears onto a corresponding bit line pair BLa1,
BLb1, the output potential of data transfer controlling circuit 310
attains the high level. If the output potential of data transfer
controlling circuit 310 attains the high level, two signals of
complementary potentials obtained by differentially amplifying the
potentials of corresponding bit lines BLa1 and BLb1 by sense amplifier 135
are applied through corresponding transistors 305 and 306 to a
corresponding sense amplifier 136. Each sense amplifier 136 differentially
amplifies two output signals of a corresponding sense amplifier 135,
applies one of the two signals of complementary potentials obtained as a
result of that through a corresponding transistor 307 to a corresponding
bit line BLa2, and applies the other of the two signals of the
complementary potentials through a corresponding transistor 308 to a
corresponding bit line BLb2. Consequently, complementary potentials in
accordance with storage data in each of memory cells connected to an
activated word line in DRAM memory array 100 appear onto a corresponding
bit line pair in SRAM memory array 200.
In a mode in which data is transferred from SRAM memory array 200 to DRAM
memory array 100, after complementary potentials in accordance with
storage data in each of memory cells connected to an activated word line
in SRAM memory array 200 appear onto a corresponding bit line pair BLa2,
BLb2, the output potential of data transfer controlling circuit 310
attains the high level. Accordingly, in this case, if the output potential
of data transfer controlling circuit 310 attains the high level, each
sense amplifier 136 applies two signals of complementary potentials
obtained by differentially amplifying the potentials of a corresponding
bit line pair BLa2, BLb2 through corresponding 305 and 306 to a
corresponding sense amplifier 135. Each sense amplifier 135 differentially
amplifies the two output signals of a corresponding sense amplifier 136,
applies one of the two signals of complementary potentials obtained as a
result of that to a corresponding bit line BLa1, and applies the other of
the two signals of the complementary potentials to a bit line BLb1.
Consequently, complementary potentials in accordance with storage data in
each of memory cells connected to an activated word line in SRAM memory
array 200 appear onto a corresponding bit line pair BLa1, BLb1 in DRAM
memory array 100.
As described above, by using a cache DRAM, a data bus for transferring data
from a main memory becomes unnecessary, and it becomes possible to
transfer data of more bits (data in memory cells in one row) than in the
conventional case at a time between a main memory, DRAM memory array 100,
and a cache memory, SRAM memory array 200.
As described above, in a conventional cache DRAM, the number of memory cell
columns in a DRAM memory array and the number of memory cell columns in a
SRAM memory array are set to be the same, and data transfer between the
DRAM memory array and the SRAM memory array is performed by block transfer
in which each memory cell row in the memory arrays is made to be one
block. Therefore, if the number of memory cell columns in the DRAM memory
array and that in the SRAM memory array is assumed to be n, the amount of
data which can be transferred at a time between the DRAM memory array and
the SRAM memory array is fixed to n bits.
Now, a cache memory is provided for the purpose of apparently relieving a
gap between an operation cycle of a CPU and the access time of a main
memory; however, according to a so-called two-hierarchy system in which a
single cache memory is provided between a CPU and a main memory, when a
gap between the access time of the cache memory and the access time of the
main memory is large, it is not possible to sufficiently relieve a gap
between an operation cycle of the CPU and the access time of the main
memory.
Specifically, if the access time of a main memory is considerably slower
than the access time of a cache memory, in a case where storage data in
the cache memory is sequentially transferred to the main memory, after
certain data is applied to the main memory, the cache memory cannot apply
the next data until the applied data is written into the main memory
completely, and, in a case where storage data in the main memory is
transferred to the cache memory, after certain data read out in the main
memory is written, the cache memory cannot perform the next data writing
until the next data is read out in the main memory completely. As a
result, time required for reading data from the main memory to the CPU and
for writing data from the CPU to the main memory is not so reduced.
Therefore, recently, there are some cases where a so-called
three-hierarchy memory configuration in which one more cache memory is
provided between a cache memory and a main memory for relieving a gap
between the access time of them is adopted. In a three-hierarchy memory
configuration, first, a CPU makes access to one of two cache memories and
thereafter makes access to the other cache memory only when desired data
is not in the one cache memory. One of two cache memories which is
accessed by the CPU is hereinafter referred to as a primary cache, and the
other cache memory is hereinafter referred to as a secondary cache.
Now, it is assumed that a conventional cache DRAM is used as a secondary
cache. As described above, the amount of data which can be transferred at
a time between a SRAM memory array and a DRAM memory array is constant in
a conventional cache DRAM. Therefore, a problem arises in a case where the
size of a block in a primary cache and the size of a block in a secondary
cache are different. This problem will be described with reference to FIG.
7. FIG. 7 is a diagram conceptually illustrating a three-hierarchy memory
configuration in a case where a conventional cache DRAM is used as a
secondary cache.
Referring to FIG. 7, in a case where it is desired to read data from a
memory part 700, a CPU 400 first makes access to a primary cache 500. If
data desired by CPU 400 is in primary cache 500, CPU 400 instructs primary
cache 500 to read the desired data and continues execution of a program.
However, if the data desired by CPU 400 is not in primary cache 500, CPU
400 interrupts execution of the program and makes access to secondary
cache 600. Specifically, in a case where a desired data is in a SRAM
memory array 200 in a cache DRAM used as secondary cache 600, CPU 400
instructs reading of the data from SRAM memory array 200, and, in a case
where the desired data is not in SRAM memory array 200, CPU 400 instructs
data transfer from a block in DRAM memory array 100 wherein the desired
data is stored to a block in SRAM memory array 200. This causes all data
of one block to be read from the block in SRAM memory array 200 to which
data has been transferred from DRAM memory array 100 in response to
instruction by CPU 400. The read data of the one block are transferred to
one block in primary cache 500. CPU 400 indicates reading of data from the
one block to primary cache 500 to obtain the desired data.
Thus, in a case where data desired by CPU 400 is in DRAM memory array 100
in secondary cache 600, all data in a block wherein the desired data is
stored is transferred in a sequence of DRAM memory array 100--SRAM memory
array 200--primary cache 500. Conversely, in a case where CPU 400
instructs storing of a desired data in primary cache 500 into DRAM memory
array 100 in secondary cache 600, data in primary cache 500 is
transferred, one block by one block, in a sequence of primary cache
500--SRAM memory array 200--DRAM memory array 100.
However, if the amount (m bits) of data in one block in primary cache 500
is larger than the amount (n bits) of data in one block in secondary cache
600, in a case where data desired by CPU 400 is in DRAM memory array 100,
data transferred from SRAM memory array 200 to primary cache 500 fill only
n/m of a block in primary cache 500. Specifically, when data in a block B1
out of blocks in primary cache 500 from which data should be finally read
in accordance with instruction by CPU 400 and data in a block B2 in SRAM
memory array 200 are exchanged, data which should be transferred from
secondary cache 600 are not in a region of (m-n) bits of block B1, and
there is no region to which data stored in advance in the region of (m-n)
bits of block B1 are to be transferred in block B2 in SRAM memory array
200 to which data from block B1 is to be transferred.
Thus, if the size of a block in primary cache 500 and the size of a block
in secondary cache 600 are different, there is a possibility of causing a
so-called mishit in which an address of a destination of data transfer is
not in a memory of the destination of data transfer when data in an
arbitrary block in primary cache 500 and data in an arbitrary block in
secondary cache 600 are exchanged.
However, in such a memory configuration of a three-hierarchy system, a
mishit should be caused only in a case where data desired by CPU 400 is
not in primary cache 500 and SRAM memory array 200. Accordingly, there
should not be mishits caused on the occasion of data exchange between a
block in primary cache 500 and a block in secondary cache 600 in CPU 400
which lower functionality of the whole system loaded with CPU 400 and
memory circuitry 700.
In order to solve such a problem, it is desired that the amount of data
transferred at a time from DRAM memory array 100 through data transfer
gate 300 into one block in SRAM memory array 200 on the occasion of data
exchange between an arbitrary block in primary cache 500 and an arbitrary
block in SRAM memory array 200 should be equal to the amount of data in
one block in primary cache 500.
However, the amount of data transferred at a time between SRAM memory array
200 and DRAM memory array 100 in a conventional cache DRAM is constant, so
that it is not possible to avoid the problem as described above unless the
size of a block in a cache DRAM used as secondary cache 600 is set
appropriately in accordance with the size of a block in a memory used as
primary cache 500. Accordingly, in order to solve the problem as described
above by using a conventional cache DRAM, it is necessary to manufacture
the cache DRAM to be used as secondary cache 600 with the size of a block
being changed for sizes of a block in the memory used as primary cache
500, and the efficiency of manufacture becomes worse.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor memory
device in which occurrence of a mishit is suppressed.
Another object of the present invention is to provide a high-speed
semiconductor memory device with a large capacity in which the rate of
occurrence of a mishit is small.
Still another object of the present invention is to provide a semiconductor
memory device in which the tendency of a mishit, which is caused by the
difference between the size of a block in a secondary cache and the size
of a block in a primary cache, to occur is small in a case where the
semiconductor memory device is used as the secondary cache.
A further object of the present invention is to provide a cache DRAM in
which it is not necessary to manufacture blocks of various sizes in
accordance with the aim of application.
A still further object of the present invention is to provide a
semiconductor memory device in which it is possible to set appropriately
the amount of data to be transferred between a plurality of types of
memory arrays formed on the same chip in accordance with the size of a
block in a primary cache.
According to an aspect, a semiconductor memory device of the present
invention includes a first memory array having first memory cells arranged
in a plurality of columns, a second memory array having second memory
cells arranged in a plurality of columns corresponding to the plurality of
columns, a plurality of first bit lines provided respectively
corresponding to all the first memory cell columns in the first memory
array, a plurality of second bit lines provided respectively corresponding
to all the second memory cell columns in the second memory array, a
plurality of switching circuits provided between and respectively
corresponding to all the first bit lines and all the second bit lines, and
a circuit for controlling the switching circuits. The switching circuits
are divided into a plurality of blocks, and the circuit for controlling
the switching circuits includes a selecting circuit for simultaneously
selecting blocks of a number corresponding to a predetermined external
signal out of the blocks and a circuit for simultaneously turning on all
switching means included in the blocks selected by the selecting circuit.
Preferably, the first memory cell array and the second memory cell array
are a DRAM memory cell array and a SRAM memory cell array, respectively,
formed on the same semiconductor substrate.
According to another aspect, a semiconductor memory device of the present
invention includes a plurality of blocks formed on the same semiconductor
substrate, a terminal for receiving an external signal indicating the
number of blocks, a block selecting circuit for simultaneously selecting
blocks of the number in accordance with the external signal out of the
plurality of blocks, and a controlling circuit for controlling data
transfer in each block in response to an output of the block selecting
circuit. Each block includes first memory cells arranged in a plurality of
first columns, second memory cells arranged in a plurality of second
columns corresponding to the plurality of first columns, a plurality of
first bit lines provided corresponding to the plurality of first columns,
a plurality of second bit lines provided corresponding to the plurality of
second columns, and a plurality of switching circuits provided between the
plurality of first bit lines and the plurality of second bit lines,
respectively. The controlling circuit simultaneously turns on switching
circuits included in the blocks selected by the block selecting circuit.
Preferably, in both of the above-described aspects, the block selecting
circuit includes a holding circuit for taking in and holding an external
signal and a decoding circuit for decoding the signal held by the holding
circuit and an address signal indicating any column of a plurality of
columns in a first memory array or a plurality of columns in a second
memory array, and the controlling circuit includes a transfer controlling
signal generating circuit for generating a transfer controlling signal for
designating inhibition/permission of data transfer between the first
memory array and the second memory array and a controlling signal
generating circuit for generating a plurality of controlling signals
corresponding to a plurality of blocks in response to the signals decoded
by the decoding circuit and the transfer controlling signal. Each
controlling signal is given in a lump to all switching circuits in the
corresponding block.
According to still another aspect, a method of transferring data in
accordance with the present invention is a method of transferring data
between first memory cells and second memory cells in a semiconductor
memory device provided with a plurality of blocks on the same
semiconductor substrate each including first memory cells arranged in a
plurality of first columns, second memory cells arranged in a plurality of
second columns corresponding to the plurality of first columns, a
plurality of first bit lines provided corresponding to the plurality of
first columns, and a plurality of second bit lines provided corresponding
to the plurality of second columns, wherein the method of transferring
data includes the step of designating the amount of data to be transferred
simultaneously between the first memory cells and the second memory cells,
the step of simultaneously selecting blocks of a number corresponding to
the designated amount of data, the step of reading data from each of the
plurality of first memory cells arranged respectively in the plurality of
first columns onto a corresponding first bit line, the step of
transferring data read from the simultaneously selected blocks out of the
read data to a corresponding second bit line, and the step of writing the
transferred data into second memory cells arranged in the corresponding
second columns.
Preferably, a plurality of switching circuits are provided, respectively,
between the plurality of first bit lines and the plurality of second bit
lines, and the step of transferring includes the step of turning on all
switching circuits in the simultaneously selected blocks.
Since a semiconductor memory device according to the present invention and
a method of transferring data inside the semiconductor memory device are
constructed as described above, the plurality of switching circuits
connecting bit lines provided corresponding to the first memory cell
columns and bit lines provided corresponding to the second memory cell
columns, respectively, are controlled simultaneously to be turned on,
switching circuits of a number in accordance with a predetermined external
signal at a time. Therefore, if the predeterm | | |
