System and method for preserving instruction granularity when translating program code from a computer having a first architecture to a

Claims

What is claimed is:

1. A method for translating a first program code to a second program code and for executing the second program code while preserving instruction granularity of the first program code when processing interrupts in response to asynchronous events, the first program code being executable on a computer having a first architecture adapted to a first instruction set and the second program code being executable on a computer having a memory and register state and a second architecture adapted to a second instruction set that is reduced relative to the first instruction set, said method comprising the steps of:

(a) operating a first computer to translate each first code instruction to a corresponding granular sequence of second code instructions wherein said second code instructions include at least two groups of said second code instructions, said two groups including a first group and a second group, said first group including second code instructions other than state update instructions which can be aborted during execution without risking a state error, said second group including all state update instructions, and wherein every second group instruction follows every first group instruction in each granular sequence of second code instructions;

(b) operating a second computer system adapted with the second architecture to execute the second program code; and in response to each asynchronous event during second code execution, interrupting execution of a current granular second code instruction sequence in order to perform asynchronous event processing for said each asynchronous event by

(i) aborting for a retry said current second code granular instruction sequence when said execution of said current granular second code instruction sequence is interrupted either before every first group instruction in said current granular second code instruction sequence has been executed, or, after all first group instructions in said current granular second code instruction sequence have been executed but before execution of any second group instruction that is in said current granular second code instruction sequence and is subject to a possible exception; and

(ii) delaying said asynchronous event processing for said each asynchronous event, in order to execute any unexecuted second code instructions in said current granular second code instruction sequence, when said execution of said current granular second code instruction sequence is interrupted after execution of all state update instructions that are in said current granular second code instruction sequence, that are in said second group, and that are subject to a possible exception.

2. A method as set forth in claim 1 wherein said second group of second code instruction includes a third subgroup including state update instructions that are subject to exception, and a fourth subgroup including state update instructions that are free of exception, and wherein every fourth subgroup instruction follows every third subgroup instruction in each granular sequence of second code instructions.

3. A method as set forth in claim 2 wherein said first group of second code instructions includes a first subgroup of instructions that read and temporarily store inputs and a second subgroup of instructions that operate on said inputs and generate and temporarily store modified results.

4. A method as set forth in claim 2 wherein said asynchronous event processing is delayed for completion of execution of said current granular second code instruction sequence when said execution of said current granular second code instruction sequence is interrupted after execution of any of said third subgroup instructions that are in said current granular second code instruction sequence.

5. A method as set forth in claim 2 wherein the granular sequence of second code instructions corresponding to one of said first code instructions includes a single simple write instruction that is in said third subgroup.

6. A method as set forth in claim 1 wherein a memory record is made as to whether each second code instruction is a granular boundary instruction for the first code instruction to which it corresponds.

7. A method as set forth in claim 6 wherein when execution of said current granular second code instruction sequence is interrupted, a second code instruction having been last executed is recorded and checked against said memory record to determine whether said second code instruction having been last executed is a boundary instruction, and when said second code instruction having been last executed is a boundary instruction, asynchronous event processing is continued.

8. A method as set forth in claim 7 wherein when said second code instruction having been last executed is not a boundary instruction, a program counter for the second program code is aligned with a next previous boundary instruction in said second program code when said current second code granular instruction sequence is aborted for a retry, and said program counter for the second program code is aligned with a next following boundary instruction in said second program code when said asynchronous event processing for said each asynchronous event is delayed in order to execute any unexecuted second code instructions in said current granular second code instruction sequence.

9. A method as set forth in claim 8 which includes making a forward scan of second code instructions remaining to be executed in said current granular second code instruction sequence to determine whether any of the second code instructions remaining to be executed are subject to a possible exception, backing the program counter for the second program code to the next previous boundary instruction when an instruction subject to exception is found during said forward scan, and when no instruction subject to an exception is found during said forward scan, executing said second code instructions remaining to be executed in said current granular second code instruction sequence, and then continuing asynchronous event processing.

10. A method as set forth in claim 9 wherein said step of operating said first computer to translate each first code instruction to a corresponding granular sequence of second code instructions includes making a list of each second code instruction having a possible exception and wherein said list is checked during said forward scan when determining whether any of the second code instructions remaining to be executed are subject to a possible exception.

11. A method as set forth in claim 1 or 2 or 10 wherein said second code instructions include instructions subject to possible memory management, arithmetic and instruction exceptions.

12. A method as set forth in claim 1 wherein said first architecture is a CISC architecture and said second architecture is a RISC architecture.

13. A method for executing a second program code while preserving instruction granularity of a first program code from which the second program code is translated when processing interrupts in response to asynchronous events; the first program code being executable on a computer having a first architecture adapted to a first instruction set and the second program code being executable on a computer having a memory and register state and a second architecture adapted to a second instruction set that is reduced relative to the first instruction set; each first code instruction having a corresponding granular sequence of second code instructions wherein said second code instructions include at least two groups of said second code instructions, said two groups including a first group and a second group, said first group including second code instructions other than state update instructions which can be aborted during execution without risking a state error, said second group including all state update instructions, and wherein every second group instruction follows every first group instruction in each granular sequence of second code instructions; said method comprising the steps of:

operating a computer system having a memory and register state and adapted with the second architecture to execute the second program code; and in response to each asynchronous event during second code execution, interrupting execution of a current granular second code instruction sequence in order to perform asynchronous event processing for said each asynchronous event by

(i) aborting for a retry said current second code granular instruction sequence when said execution of said current granular second code instruction sequence is interrupted either before every first group instruction in said current granular second code instruction sequence has been executed, or, after all first group instructions in said current granular second code instruction sequence have been executed but before execution of any second group instruction that is in said current granular second code instruction sequence and is subject to a possible exception; and

(ii) delaying said asynchronous event processing for said each asynchronous event, in order to execute any unexecuted second code instructions in said current granular second code instruction sequence, when said execution of said current granular second code instruction sequence is interrupted after execution of all state update instructions that are in said current granular second code instruction sequence, that are in said second group, and that are subject to a possible exception.

14. A method as set forth in claim 13 wherein said first group of second code instructions includes a first subgroup of instructions that read and temporarily store inputs and a second subgroup of instructions that operate on said inputs and generate and temporarily store modified results; said second group of second code instructions includes a third subgroup including state update instructions that are subject to exception, and a fourth subgroup including state update instructions that are free of exception, and wherein every fourth subgroup instruction follows every third subgroup instruction in each granular sequence of second code instructions; and wherein said asynchronous event processing is delayed for completion of execution of said current granular second code instruction sequence when said execution of said current granular second code instruction sequence is interrupted after execution of any of said third subgroup instructions that are in said current granular second code instruction sequence.

15. A method as set forth in claim 13 wherein a memory record is made as to whether each second code instruction is a granular boundary instruction for the first code instruction to which said each second code instruction corresponds; when execution of said current granular second code instruction sequence is interrupted, a second code instruction having been last executed is recorded and checked against said memory record to determine whether said second code instruction having been last executed is a boundary instruction, and when said second code instruction having been last executed is a boundary instruction, asynchronous event processing is continued.

16. A method as set forth in claim 15 wherein when said second code instruction having been last executed is not a boundary instruction, a program counter for the second program code is aligned with a next previous boundary instruction in said second program code when said current second code granular instruction sequence is aborted for a retry, and said program counter for the second program code is aligned with a next following boundary instruction in said second program code when said asynchronous event processing for said each asynchronous event is delayed in order to execute any unexecuted second code instructions in said current granular second code instruction sequence.

17. A method as set forth in claim 16 which includes making a forward scan of second code instructions remaining to be executed in said current granular second code instruction sequence to determine whether any of the second code instructions remaining to be executed are subject to a possible exception, backing the program counter for the second program code to the next previous boundary instruction when an instruction subject to exception is found during said forward scan, and when no instruction subject to an exception is found during said forward scan, executing said second code instructions remaining to be executed in said current granular second code instruction sequence, and the continuing asynchronous event processing.

18. A method as set forth in claim 17 wherein a list of each second code instruction having a possible exception is checked during said forward scan when determining whether any of the second code instructions remaining to be executed are subject to a possible exception.

19. A method as set forth in claim 13 wherein said second code instructions include instructions subject to possible memory management, arithmetic and instruction exceptions.

20. A method as set forth in claim 13 wherein said first architecture is a CISC architecture and said second architecture is a RISC architecture.

21. A method for executing a second program code while preserving instruction granularity of a first program code from which the second program code is translated when processing interrupts in response to asynchronous events; the first program code being executable on a computer having a first architecture adapted to a first instruction set and the second program code being executable on a computer having a memory and register state and a second architecture adapted to a second instruction set that is reduced relative to the first instruction set; each first code instruction having a corresponding granular sequence of second code instructions; said second program code having a corresponding memory record as to whether each second code instruction is a granular boundary instruction for the first code instruction to which said each second code instruction corresponds; said method comprising the steps of:

operating a computer system having a memory and register state and adapted with the second architecture to execute the second program code; and in response to each asynchronous event during second code execution, interrupting execution of a current granular second code instruction sequence in order to perform asynchronous event processing for said each asynchronous event by recording a second code instruction having been last executed, and checking said second code instruction having been last executed against said memory record to determine whether said second code instruction having been last executed is a boundary instruction; and

(a) when said second code instruction having been last executed is a boundary instruction, continuing asynchronous event processing; and

(b) when said second code instruction having been last executed is not a boundary instruction,

(i) aborting for a retry said current second code granular instruction sequence when said current granular second code instruction sequence includes an unexecuted instruction that is subject to a possible exception, and

(ii) when said current granular second code instruction sequence does not include an unexecuted instruction that is subject to a possible exception, delaying said asynchronous event processing for said each asynchronous event, in order to execute each unexecuted second code instruction in said current granular second code instruction sequence.

22. A method as set forth in claim 21 wherein when said second code instruction having been last executed is not a boundary instruction, a program counter for the second program code is aligned with a next previous boundary instruction in said second program code when said current second code granular instruction sequence is aborted for a retry, and said program counter for the second program code is aligned with a next following boundary instruction in said second program code when said asynchronous event processing for said each asynchronous event is delayed in order to execute any unexecuted second code instructions in said current granular second code instruction sequence.

23. A method as set forth in claim 22 which includes making a forward scan of second code instructions remaining to be executed in said current granular second code instruction sequence to determine whether any of the second code instructions remaining to be executed are subject to a possible exception, backing the program counter for the second program code to the next previous boundary instruction when an instruction subject to exception is found during said forward scan, and when no instruction subject to an exception is found during said forward scan, executing said second code instructions remaining to be executed in said current granular second code instruction sequence, and the continuing asynchronous event processing.

24. A method as set forth in claim 23 wherein a list of each second code instruction having a possible exception is checked during said forward scan when determining whether any of the second code instructions remaining to be executed are subject to a possible exception.

25. A method as set forth in claim 21 wherein said second code instructions include instructions subject to possible memory management, arithmetic and instruction exceptions.

26. A method as set forth in claim 21 wherein said first architecture is a CISC architecture and said second architecture is a RISC architecture.

27. A method for executing a second program code while preserving instruction granularity of a first program code from which the second program code is translated when processing interrupts in response to asynchronous events; the first program code being executable on a computer having a first architecture adapted to a complex instruction set (CISC) and the second program code being executable on a computer having a memory and register state and a second architecture adapted to a reduced instruction set (RISC) that is reduced relative to the first instruction set; each first code instruction having a corresponding granular sequence of second code instructions; said second program code having a corresponding memory record as to whether each second code instruction is a granular boundary instruction for the first code instruction to which said each second code instruction corresponds; said method comprising the steps of:

operating a computer system having a memory and register state and adapted with the second architecture to execute the second program code; and in response to each asynchronous event during second code execution, interrupting execution of a current granular second code instruction sequence in order to perform asynchronous event processing for said each asynchronous event by

recording a second code instruction having been last executed, and checking said second code instruction having been last executed against said memory record to determine whether said second code instruction having been last executed is a boundary instruction; and

(a) when said second code instruction having been last executed is a boundary instruction, continuing asynchronous event processing; and

(b) when said second code instruction having been last executed is not a boundary instruction, making a forward scan of second code instructions remaining to be executed in said current granular second code instruction sequence to determine whether any of the second code instructions remaining to be executed are subject to a possible exception, and

(i) when said forward scan finds a second code instruction remaining to be executed that is subject to a possible exception, aborting said current second code granular instruction sequence for a retry after completion of said asynchronous event processing for each asynchronous event; and

(ii) when said current granular second code instruction sequence does not include an unexecuted instruction that is subject to a possible exception, executing each unexecuted second code instruction in said current granular second code instruction sequence, and thereafter continuing said asynchronous event processing for said each asynchronous event.

28. A method as set forth in claim 27 wherein when said second code instruction having been last executed is not a boundary instruction, a program counter for the second program code is aligned with a next previous boundary instruction in said second program code when said current second code granular instruction sequence is aborted for a retry, and said program counter for the second program code is aligned with a next following boundary instruction in said second program code when said asynchronous event processing for said each asynchronous event is delayed in order to execute any unexecuted second code instructions in said current granular second code instruction sequence.

29. A method as set forth in claim 27 wherein a list of each second code instruction having a possible exception is checked during said forward scan, in order to determine whether any of the second code instructions remaining to be executed are subject to a possible exception.

30. A method as set forth in claim 27 wherein said second code instructions include instructions subject to possible memory management, arithmetic and instruction exceptions.

31. A system for executing a second program code containing sequences of instructions that are from a second instruction set for a second architecture, said second instruction set being reduced relative to a first instruction set for a first architecture while preserving instruction granularity of a first program code from which the second program code is translated and which contains instructions from the first instruction set, each first code instruction having a corresponding granular sequence of second code instructions wherein said second code instructions include at least two group of said second code instructions, said two groups including a first group and a second group, said first group including second code instructions other than state update instructions which can be aborted during execution without risking a state error, said second group including all state update instructions, and wherein every second group instruction follows every first group instruction in each granular sequence of second code instructions; said system comprising:

a computer for executing the second code, said computer having a second architecture and having a processor and a memory coupled to said processor, and means responsive to an asynchronous event during second code execution for interrupting execution of a current granular second code instruction sequence in order to perform asynchronous event processing for said asynchronous event, said means responsive to an asynchronous event including:

(i) means for aborting for a retry said current second code granular instruction sequence when said execution of said current granular second code instruction sequence is interrupted either before every first group instruction in said current granular second code instruction sequence has been executed, or, after all first group instructions in said current granular second code instruction sequence have been executed but before execution of any second group instruction that is in said current granular second code instruction sequence and is subject to a possible exception; and

(ii) means for delaying said asynchronous event processing for said each asynchronous event, in order to execute any unexecuted second code instructions in said current granular second code instruction sequence, when said execution of said current granular second code instruction sequence is interrupted after execution of all state update instructions that are in said current granular second code instruction sequence, that are in said second group, and that are subject to a possible exception.

32. A method as set forth in claim 31 wherein said first group of second code instructions includes a first subgroup of instructions that read and temporarily store inputs and a second subgroup of instructions that operate on said inputs and generate and temporarily store modified results; said second group of second code instructions includes a third subgroup including state update instructions that are subject to exception, and a fourth subgroup including state update instructions that are free of exception, and wherein every fourth subgroup instruction follows every third subgroup instruction in each granular sequence of second code instructions; and wherein said means for delaying includes means for delaying said asynchronous event processing for completion of execution of said current granular second code instruction sequence when said execution of said current granular second code instruction sequence is interrupted after execution of any of said third subgroup instructions that are in said current granular second code instruction sequence.

33. A system as set forth in claim 32 wherein said memory holds a memory record indicating whether each second code instruction is a granular boundary instruction for the first code instruction to which said each second code instruction corresponds; and said means responsive to an asynchronous event includes means, responsive when said execution of said current granular second code instruction sequence is interrupted, for recording a second code instruction having been last executed and checking said second code instruction having been last executed against said memory record to determine whether said second code instruction having been last executed is a boundary instruction, and when said second code instruction having been last executed is a boundary instruction, for continuing asynchronous event processing.

34. A system as set forth in claim 33, wherein said means responsive to an asynchronous event includes means responsive when said second code instruction having been last executed is not a boundary instruction for aligning a program counter for the second program code with a next previous boundary instruction in said second program code when said execution of said current second code granular instruction sequence is aborted for a retry, and for aligning said program counter for the second program code with a next following boundary instruction in said second program code when said asynchronous event processing for said asynchronous event is delayed in order to execute any unexecuted second code instructions in said current granular second code instruction sequence.

35. A system as set forth in claim 34, wherein said means responsive to an asynchronous event includes means for making a forward scan of second code instructions remaining to be executed in said current granular second code instruction sequence to determine whether any of the second code instructions remaining to be executed are subject to a possible exception, backing the program counter for the second program code to the next previous boundary instruction when an instruction subject to exception is found during said forward scan, and when no instruction subject to an exception is found during said forward scan, for executing said second code instructions remaining to be executed in said current granular second code instruction sequence, and for then continuing asynchronous event processing.

36. A system as set forth in claim 35 wherein said means for making a forward scan includes means for checking a list of each second code instruction having a possible exception when determining whether any of the second code instructions remaining to be executed are subject to a possible exception.

37. A method as set forth in claim 31 wherein said second code instructions include instructions subject to possible memory management, arithmetic and instruction exceptions.

38. A method as set forth in claim 31 wherein said first architecture is a CISC architecture and said second architecture is a RISC architecture.

39. A system for executing a second program code containing sequences of instructions that are from a second instruction set for a second architecture, said second instruction set being reduced relative to a first instruction set for a first architecture while preserving instruction granularity of a first program code from which the second program code is translated and which contains instructions from the first instruction set, each first code instruction having a corresponding granular sequence of second code instructions; said system comprising:

a computer for executing the second code, said computer having a second architecture and having a processor and a memory coupled to said processor, and means responsive to an asynchronous event during second code execution for interrupting execution of a current granular second code instruction sequence in order to perform asynchronous event processing for said asynchronous event, said memory holding a memory record indicating whether each second code instruction is a granular boundary instruction for the first code instruction to which said each second code instruction corresponds; and said means responsive to an synchronous event including:

means for recording a second code instruction having been last executed, and checking said second code instruction having been last executed against said memory record to determine whether said second code instruction having been last executed is a boundary instruction; and

(a) means responsive when said second code instruction having been last executed is a boundary instruction for continuing asynchronous event processing; and

(b) means responsive when said second code instruction having been last executed is not a boundary instruction, for

(i) aborting for a retry said current second code granular instruction sequence when said current granular second code instruction sequence includes an unexecuted instruction that is subject to a possible exception, and

(ii) when said current granular second code instruction sequence does not include an unexecuted instruction that is subject to a possible exception, delaying said asynchronous event processing for said each asynchronous event, in order to execute each unexecuted second code instruction in said current granular second code instruction sequence.

40. A system as set forth in claim 39 wherein said means responsive to an asynchronous event includes means responsive when execution of said current granular second code instruction sequence is interrupted, for recording a second code instruction having been last executed and checking said second code instruction having been last executed against said memory record to determine whether said second code instruction having been last executed is a boundary instruction, and when said second code instruction having been last executed is a boundary instruction, for continuing asynchronous event processing.

41. A system as set forth in claim 40, wherein said means responsive to an asynchronous event includes means responsive when said second code instruction having been last executed is not a boundary instruction for aligning a program counter for the second program code with a next previous boundary instruction in said second program code when said current second code granular instruction sequence is aborted for a retry, and for aligning said program counter for the second program code with a next following boundary instruction in said second program code when said asynchronous event processing for said asynchronous event is delayed in order to execute any unexecuted second code instructions in said current granular second code instruction sequence.

42. A system as set forth in claim 41, wherein said means responsive to an asynchronous event includes means for making a forward scan of second code instructions remaining to be executed in said current granular second code instruction sequence to determine whether any of the second code instructions remaining to be executed are subject to a possible exception, backing the program counter for the second program code to the next previous boundary instruction when an instruction subject to exception is found during said forward scan, and when no instruction subject to an exception is found during said forward scan, for executing said second code instructions remaining to be executed in said current granular second code instruction sequence, and for then continuing asynchronous event processing.

43. A system as set forth in claim 42, wherein said means for making a forward scan includes means for checking a list of each second code instruction having a possible exception when determining whether any of the second code instructions remaining to be executed are subject to a possible exception.

44. A method as set forth in claim 39 wherein said second code instructions include instructions subject to possible memory management, arithmetic and instruction exceptions.

45. A method as set forth in claim 39 wherein said first architecture is a CISC architecture and said second architecture is a RISC architecture.

CROSS-REFERENCE TO RELATED APPLICATIONS

Reference is made to the following concurrently filed patent application, which is hereby incorporated by reference:

Ser. No. 07/666,071 entitled IMPROVED SYSTEM AND METHOD FOR PRESERVING INSTRUCTION STATE-ATOMICITY FOR TRANSLATED PROGRAM CODE and filed by Scott G. Robinson, Richard Sites and Richard Witek.

Reference is also made to the following concurrently filed patent applications assigned to the present assignee and related to code translation:

Ser. No. 07/666,070 entitled BRANCH RESOLUTION VIA BACKWARD SYMBOLIC EXECUTION and filed by Richard L. Sites.

Ser. No. 07/666,216 entitled LOCATING PROGRAM CODE BY SUCCESSIVE CODE EXECUTION AND INTERPRETATION and filed by Richard L. Sites.

Ser. No. 07/666,210 entitled USE OF STACK DEPTH TO IDENTIFY MACHINE CODE MISTAKES and filed by Richard L. Sites.

Ser. No. 07/666,223 entitled CROSS-IMAGE REFERENCING OF PROGRAM CODE and filed by Richard L. Sites.

Ser. No. 07/666,083 entitled USE OF STACK DEPTH TO IDENTIFY ARCHITECTURE AND CALLING STANDARD DEPENDENCIES IN MACHINE CODE and filed by Thomas R. Benson.

Ser. No. 07/666,084 entitled REGISTER USAGE TRACKING TO SUPPORT COMPILED 32-BIT CODE IN 64-BIT ENVIRONMENT and filed by Thomas R. Benson.

Ser. No. 07/666,085 entitled MAPPING ASSEMBLY LANGUAGE ARGUMENT LIST REFERENCES ACROSS MACHINE ARCHITECTURES and filed by Thomas R. Benson.

Ser. No. 07/666,082 entitled TRACKING VAX.RTM. CONDITION CODES FOR PORTING TO RISC ARCHITECTURE and filed by Thomas R. Benson.

Ser. No. 07/666,023 entitled EFFICIENT AND FLEXIBLE LINK OF PROGRAM UNITS AT PROGRAM ACTIVATION and filed by Daniel L. Murphy.

Reference is also made to the following concurrently filed patent applications assigned to the present assignee.

Ser. No. 07/666,039 entitled IMPROVED SYSTEM AND METHOD FOR EXECUTING MULTIPLE CODES IN A MULTI-ARCHITECTURE ENVIRONMENT WITH CODE DEBUGGING CAPABILITY and filed by Mark A. Herdeg, James A. Wooldridge, Scott G. Robinson, Ronald F. Brender and Michael V. Iles.

Ser. No. 07/666,028 entitled SYSTEM AND METHOD FOR AUTOMATICALLY INTERFACING CALL CONVENTIONS BETWEEN TWO DISSIMILAR PROGRAM UNITS and filed by Daniel L. Murphy.

Ser. No. 07/665,888 entitled IMPROVED SOFTWARE DEBUGGING SYSTEM AND METHOD ESPECIALLY ADAPTED FOR CODE DEBUGGING WITHIN A MULTI-ARCHITECTURE ENVIRONMENT and filed by James A. Wooldridge, Ronald F. Brender and Henry N. Grieb, III.

Ser. No. 07/666,022 entitled IMPROVED SIMULATOR SYSTEM AND METHOD ESPECIALLY ADAPTED FOR CODE EXECUTION IN A MULTI-CODE EXECUTION AND DEBUGGING SYSTEM WITHIN A MULTI-ARCHITECTURE ENVIRONMENT and filed by Mark A. Herdeg and Michael V. Iles.

Ser. No. 07/666,072 entitled IMPROVED SYSTEM AND METHOD FOR DETECTING CROSS-DOMAIN INSTRUCTION CALLS AND DATA REFERENCES ESPECIALLY ADAPTED FOR CODE INTERFACE JACKETING IN A MULTI-CODE EXECUTION AND DEBUGGING SYSTEM WITHIN A MULTI-ARCHITECTURE ENVIRONMENT and filed by Mark A. Herdeg, Scott G. Robinson, Ronald F. Brender and Michael V. Iles.

Ser. No. 07/665,752 entitled IMPROVED SYSTEM AND METHOD FOR JACKETING CROSS-DOMAIN CALLS IN A MULTI-CODE EXECUTION AND DEBUGGING SYSTEM WITHIN A MULTI-ARCHITECTURE ENVIRONMENT and filed by Ronald F. Brender and Michael V. Iles.

Ser. No. 07/665,886 which is entitled FASTER PROCESS FOR DEVELOPING NEW COMPUTER SYSTEMS EMPLOYING NEW AND BETTER PROCEDURES FOR SOFTWARE DEVELOPMENT AND TESTING and filed by Robert V. Landau, James E. Johnson and Michael V. Iles.

BACKGROUND OF THE INVENTION

The present invention relates to systems and methods for adapting program codes for execution on different computer systems and more particularly to systems and methods for translating codes based on a first instruction set to codes based on a relatively reduced instruction set while preserving instruction granularity.

In the early years of computer programming, instructions for computer programs were generated at the microcode level. With the development and growth of software engineering, more tasks were combined in single complex instructions executable by computers having a hardware architecture designed for the instruction complexity.

Increasing instruction complexity generally provided increasing price/performance benefits in the developing environment of computer hardware costs and performance capabilities. As a result, complex instruction set codes (CISC) became widely accepted.

With increased instruction complexity, however, it has become more difficult to design system hardware for higher execution speed. Instead, a reduced instruction set code (RISC), coupled with correlated RISC computer hardware architecture, has gained acceptance as a mechanism to lead to significantly improved system price/performance.

A RISC system generally employs simpler basic instructions to direct desired operations. A single RISC instruction normally specifies a single operation with at most a single memory access. Further, a RISC system normally provides a register for each basic instruction. The instructions in a RISC instruction set are thus still at a higher level than microcode.

In the typical CISC system, a single instruction may specify a complex sequence of operations and it may make many direct accesses to memory. Thus, operations performed by a CISC instruction may require several RISC instructions.

A RISC system is generally designed with optimized hardware and software tradeoffs that provide faster system operation, better overall system performance and lower system cost relative to available hardware cost and performance capability.

One obstacle to conversion from CISC systems to RISC systems is the existence of large software libraries which have been developed for CISC systems and which are not generally available for RISC systems. When a computer system user chooses to acquire a new computer system, one of the user's major considerations is whether the user's library of application programs can be used or converted for use on the new computer system, and what the cost of replacing that library would be. Thus, for computer system users who wish to achieve better price/performance through RISC computer systems, it is highly important that an economic and effective mechanism be provided for adapting, or "migrating" the user's library of application programs for execution on the RISC computer system.

Several choices are available to the user for program migration. Recompiling or recoding can be employed, but these techniques are typically used for migrating programs written in a high level language such as FORTRAN which either have no detailed machine dependencies or which have any existing machine dependencies removed by manual programming modifications. Further, in recompiling or recoding, the user typically bears all responsibility for program modification and program behavioral guarantees.

Alternatively, interpretation procedures can be used, but the penalty for this approach typically is substantially reduced program performance. More particularly, interpretation procedures are software programs that run on one computer and read a stream of subject instructions (which may well be instructions for a different type of computer) as data, and for each subject instruction perform the indicated operation. Such procedures typically execute 10 to 100 machine instructions on the one computer to interpret a single subject instruction. Thus, interpretation procedures provide substantially reduced program performance, compared to direct execution of functionally-equivalent code on the one computer.

The most effective and efficient migration, however, involves code translation. In code translation, each instruction from an existing program is translated into one or more instructions in the language of the destination machine.