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CROSS-REFERENCE TO RELATED APPLICATIONS
This application cross-references and incorporates by reference the
following simultaneously filed, co-pending and co-assigned applications of
Texas Instruments Incorporated:
______________________________________
Serial No. Title
______________________________________
560,983 filed July 31, 1990, now U.S.
A Counter Circuit
5,131,018
560,961 filed July 31, 1990, now
A Configuration Selection
abandoned Circuit for a Semi-
conductor Device
560,962 filed July 31, 1990, pending
A Pulse Generation
Circuit
560,541 filed July 31, 1990, pending
A CMOS Single Input
Buffer for Multiplexed
Inputs
560,523 filed July 31, 1990 abandoned,
A Voltage Reference
now 840,680 filed February 21, 1992
Initialization Circuit
560,934 filed July 31, 1990 abandoned,
A Power up Detection
now 892,388 filed May 27, 1992
Circuit
561,536 filed July 31, 1990
A Power Up Reset
Circuit
560,662 filed July 31, 1990
A Substrate Bias
Generator System
560,542 filed July 31, 1990 abandoned,
A Voltage Level
now 908,633 filed July 2, 1992
Detection Circuit
560,720 filed July 31, 1990 abandoned,
A Circuit and Method
now 933,972 filed August 24, 1992
for Two Stage
Redundancy Decoding
560,935 filed July 31, 1990 abandoned,
A Method for Initalizing
now 892,390 filed May 27, 1992
Redundant Circuitry
560,646 filed July 31, 1990
A Voltage Driver Circuit
______________________________________
FIELD OF THE INVENTION
This invention is in the field of integrated circuits, and is more
specifically related to memory devices.
BACKGROUND OF THE INVENTION
The development of VLSI semi-conductor devices of the Dynamic Random Access
Memory (DRAM) type is well known. Over the years, the industry has
steadily progressed from DRAMS of the 16K type (as shown in the U.S. Pat.
No. 4,081,701 issued to White, McAdams and Redwine), to DRAMS of the 64K
type (as shown in U.S. Pat. No. 4,055,444 issued to Rao) to DRAMS of the
IMB type (as shown in U.S. Pat. No. 4,658,377 issued McElroy), and
progressed to DRAMS of the 4 MB type. The 16 MB DRAM, wherein more than 16
million memory cells are contained on a single semiconductor chip is the
next generation of DRAMs scheduled for production.
In designing VLSI semiconductor memory devices of the 16 MB DRAM type,
designers are faced with numerous challenges. One area of concern is power
consumption. The device must be able to power the increased memory cells
and the supporting circuits. However, for commercial viability, the device
must not use excessive power. The power supplies used and the burn in
voltage for the part must also be compatible with the thin gate oxides in
the device.
Another area of concern is the elimination of defects. The development of
larger DRAMS has been fostered by the reduction in memory cell geometries,
as illustrated in U.S. Pat. No. 4,240,092 to KUO (a planar capacitor cell)
and as illustrated in U.S. Pat. No. 4,721,987 to Baglee et. al. (a trench
capacitor cell). The extremely small geometries of the 16 MB DRAM will be
manufactured using sub-micron technology. The reduction in feature size
has meant that particles that previously did not cause problems in the
fabrication process, now can cause circuit defects and device failures.
In order to ameliorate defects, redundancy schemes have been introduced.
The redundancy schemes normally consist of a few extra rows and columns f
memory cells that are placed within the memory array to replace defective
rows and columns of memory cells. Designers need new and improved
redundancy schemes in order to effectively and efficiently repair defects
and thereby increase yields of 16 MB DRAM chips.
Another area of concern is testing. The device must have circuits to allow
for the industry standards 16 X parallel tests. In addition, other
circuits and test schemes are needed for internal production use to verify
operability and reliability.
The options that the device should have is another cause for concern. For
instance, some customers require a X1 device, while others require a X4
device. Some require an enhanced page mode of operation. Additionally, it
is yet undecided whether the DRAM industry will maintain 4096-cycle
refresh, or move towards a lower number of refresh cycles.
Another cause for concern is the physical layout of the chip. The memory
cells and supporting circuits must fit on a semiconductor chip of
reasonable size. The size of the packaged device must be acceptable to
buyers.
New design strategies and circuits are required to meet the above concerns,
and other concerns, relating to the development of the next generation,
and to future generations, of Dynamic Random Access Memory devices.
It is an object of this invention therefore, to provide a method such that
during testing of the memory devices it can easily be determined if the
devices remain in the stress test.
Other objects and advantages of this invention will become apparent to
those of ordinary skill in the art, having reference to the following
specification, together with the drawings.
SUMMARY OF THE INVENTION
A test validation process for a semiconductor device applies signals
indicating a test mode to the semiconductor device. The device produces
output signals and the output signals are read to determine whether the
device is in the indicated test mode. The test mode is conducted by
operating the device. The output signals are read upon completion of the
test mode to determine if the device is still in the indicated test mode.
The test validation method is useful for memory chips and particularly
Dynamic Random Access Memory, DRAM, devices that are burn-in stress
tested.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 0.1 is a block system level drawing illustrating a 16 MB Dynamic
Random Access Memory chip incorporating the preferred embodiment of the
invention.
FIG. 0.11 is a graph orientation drawing illustrating how to connect FIGS.
0.11A1-0.11A5, FIGS. 0.11B1-0.11B5, FIGS. 0.11C1-0.11C5, FIGS.
0.11D1-0.11D5, FIGS. 0.11E1-0.11E5, FIGS. 0.11F1-0.11 F5, and FIGS.
0.11G1-0.11G5. The figures are oriented by lying the figures such that the
A1-G5 reference characters of each figure is on the bottom left hand
corner of the figure.
FIGS. 0.11A1-0.11A5, FIGS. 0.11B1-0.11B5, FIGS. 0.11C1-0.11C5, FIGS.
0.11D1-0.11D5, FIGS. 0.11E1-0.11E5, FIGS. 0.11F1-0.11 F5, and FIGS.
0.11G1-0.11G5, when connected together, form a block diagram drawing more
particularly illustrating the DRAM of FIG. 0.1.
FIG. 0.2 is a top view drawing illustrating the pin designations of the
packaged memory chip.
FIG. 0.3 is a three dimensional view of the packaged memory chip wherein
the encapsulating material is rendered transparent.
FIG. 0.4 is an assembly view of FIG. 0.3.
FIG. 0.5 is a cross sectional view of FIG. 0.3
FIG. 0.6 is a top view drawing illustrating the bond pad designations of
the memory chip.
FIG. 0.7 is a top view drawing illustrating a portion of the memory array.
FIG. 0.8 is a cross sectional view of a portion of the memory array.
FIG. 0.9 is a side view of the cross sectional view of FIG. 0.8.
Note: FIGS. 1 through 149 are electrical schematic drawings of various
circuits of the 16 mb DRAM of FIG. 0.1 and FIG. 0.11. It is to be noted
and understood that the prefix "X:" precedes the device reference
characters illustrated in these FIGS. even though "X:" is not physically
written on these drawings. "X:" corresponds to the FIG. number of the
schematic. Codes for various of the electrical schematics are contained in
the appendices. Appendices A53-A57 contain a signal from-to list for the
electrical schematics. Unless the figures and the structural description
indicates otherwise, it is to be presumed that the circuits are biased by
the voltage Vperi.
FIG. 1 illustrates the RCL, or Row Clock Logic Circuit.
FIG. 2 illustrates the CL1, or Column Logic Circuit.
FIG. 3 illustrates the RBC, or Ras Before Cas Circuit. FIG. 4 illustrates
the RBC.sub.-- RESET Circuit, or the Ras Before Cas Reset Circuit.
Note: there is no FIG. 5.
FIG. 6 illustrates the PADABUF Circuit, or the Pad Address Buffer Circuit.
FIG. 7 illustrates the RADR, or Row Address Driver Circuit.
FIG. 8 illustrates the BITCOUNT, or Bit Count Circuit.
FIG. 9 illustrates the RF, or Row Factor Circuit. Code in Appendix A1.
FIG. 10 illustrates the RLEN.sub.--, or Row Logic Enable Circuit.
FIG. 11 illustrates the RLXH, or Row Logic X (Word) High Circuit.
FIG. 12 illustrates the RDDR, or Row Decoder Driver Circuit. Code in
Appendix A3.
FIG. 12.2 illustrates the BNKPC.sub.--, or Bank Select Pre-charge Circuit.
FIG. 13 illustrates the XDECM, or Row Decoder Circuit.
FIG. 14 illustrates the RRA, or Row Redundancy Address Circuit. Code in
Appendices A5 and A7.
FIG. 15 illustrates the RRDEC, or Row Redundancy Decoder Circuit.
FIG. 16 illustrates the RRX, or Row Redundancy X Factor Circuit.
FIG. 17 illustrates the RRXE, Row Redundancy X Factor Emulator Circuit.
FIG. 18 illustrates the RRQS, or Row Redundancy Quadrant Select Circuit.
FIG. 19 illustrates the RXDEC, or Redundancy X (word) Decoder Circuit.
FIG. 20 illustrates the SDXWD, or Sense Clock X-Word Detect Circuit.
FIG. 21 illustrates the SDS1, or Master Sense Clock Circuit.
FIG. 22 illustrates the SDS2, or Sense Clock-2 Circuit.
FIG. 23 illustrates the SDS3, or Sense Clock-3 Circuit.
FIG. 24 illustrates the SDS4, or Sense Clock-4 Circuit.
FIG. 25 illustrates the BNKSL, or Bank Select Circuit. Code in Appendix A9.
FIG. 26 illustrates the BSS.sub.-- DR, or Bank Select Driver Circuit.
FIG. 27 illustrates the LENDBNKSL, or Left End Bank Select Circuit.
FIG. 28 illustrates the RENDBNKSL, or Right End Bank Select Circuit.
FIG. 29 illustrates the 11234, or Sense Clock 1234 Circuit.
FIG. 30 illustrates the PCNC, or P charge and N charge Circuit.
FIG. 31 illustrates the SA, or Sense Amplifier Circuit. Code in Appendix
A11.
FIG. 32 illustrates the SA.sub.-- END, or Sense Amplifier End Circuit.
FIG. 33 illustrates the CABUF01, or Column Address Buffer 01 Circuit.
FIG. 34 illustrates the CABUF29, or Column Address Buffer 29 Circuit.
FIG. 35 illustrates the CLEN, or Column Logic Enable Circuit.
FIG. 36 illustrates the CF07, or Column Factor 0, 7 Circuit. Code in
Appendix A13.
FIG. 36.1 illustrates the CF07DR, or Column Factor 0,7 Driver Circuit.
FIG. 36.2 illustrates the CF815, or Column Factor 8 thru 15 Circuit.
FIG. 37 illustrates the YDEC, or Y Decoder Circuit.
FIG. 37.1 illustrates the CRDEC, or Column Redundancy Coder Enable Circuit.
FIG. 38 illustrates the CRRA, or Column Redundancy Row Address Circuit.
Code in Appendix A35.
FIG. 39 illustrates the CRCA, or Column Redundancy Address Circuit. Code in
Appendices A37 and A39.
FIG. 40 illustrates the CRDEC.sub.--, or Column Redundancy Decoder Circuit.
FIG. 41 illustrates the CRY, or Column Redundancy Y Factor Circuit. Code in
Appendix A41.
FIG. 42 illustrates the CRSS, or Column Redundancy Segment Select Circuit.
FIG. 43 illustrates the CRQS, or Column Redundancy Quadrant Circuit.
FIG. 44 illustrates the CRYS, or Column Redundancy Y Select Circuit.
FIG. 45 illustrates the CRIOS, or Column Redundancy I/O Select Circuit.
FIG. 46 illustrates the CRDPC, or Column Delay Redundancy Pre-Charge
Circuit.
FIG. 47 illustrates the Column Address Transition Detector Circuit, CATD.
FIG. 48 illustrates the Column Logic Summation Circuit, CLSUM.
FIG. 49 illustrates the Column Sum Logic Driver Circuit, CLSUMDR.
FIG. 50 illustrates the Quadrant Select Circuit, QDDEC. Code in Appendix
A15.
FIG. 51 illustrates the Global Amplifier Select End Circuit, GASELE. Code
in Appendix A17 and A19.
FIG. 52 illustrates the Global Amplifier Select Circuit, GASEL.
FIG. 53 illustrates the Data Write Enable Signal Circuit, DWE.sub.--. Code
in Appendix A21.
FIG. 54 illustrates the IOCLMP, or I/O Clamp Circuit. Code in Appendix A23.
FIG. 55 illustrates the Local I/O Amplifier Circuit, LIAMP. Code in
Appendix A25.
FIG. 56 illustrates the Global I/O Amplifier Circuit, GIAMP. Code in
Appendix A27.
FIG. 57 illustrates the I/O Multiplexor Circuit, IOMUX. Code in Appendix
A29.
FIG. 58 illustrates the I/O Multiplexor 3 Circuit, IOMUX3.
FIG. 59 illustrates the Pre-Output Buffer Circuit, POUTBUF.
FIG. 59.1 illustrates the Pre-Output Buffer 3, POUTBUF3.
FIG. 60 illustrates the Output Buffer Circuit, OUTBUF. Code in Appendix
A31.
FIG. 60.2 illustrates the Output Buffer 3 Circuit, OUTBUF3.
FIG. 60.3 illustrates WMO and CLX4 Generation.
FIG. 61 illustrates the Input Buffer Circuit, INBUF. Code in Appendix A33.
FIG. 62 illustrates the Input Buffer 3 Circuit, INBUf3.
FIG. 63 illustrates the I/O Control Logic Circuit, IOCTL.
FIG. 64 illustrates the I/O Control Logic Circuit, IOCTL3.
FIG. 65 illustrates the W1 or Write Clock 1 Circuit.
FIG. 66 illustrates the WBR or Write Before RAS Circuit.
FIG. 67 illustrates the Read Before Write Pulse Circuit RBWP.sub.--.
FIG. 68 illustrates the Write Before RAS Pulse Circuit WBRP.
FIG. 69 illustrates the Read Write Logic Enable Circuit RWLEN. FIG. 70
illustrates the Control Logic Read Master Circuit CLRMX.sub.--.
FIG. 71 illustrates the Data Enable Circuit DEN.sub.--.
FIG. 72 illustrates the TMDLEN Circuit, or the Test Mode Data Enable
Circuit
FIG. 73 illustrates the Write Logic Master Circuit WLMX.
FIG. 74 illustrates the Internal Output Enable Clock 1 Circuit G1.
FIG. 75 illustrates the Early Write Circuit LATWR.sub.--.
FIG. 76 illustrates the Control Logic Output Enables Circuit CLOE.
FIG. 77 illustrates the Voltage Bandgap Reference Generator Circuit
VBNDREF.
FIG. 78 illustrates the Voltage Multiplier Circuit VMULT.
FIG. 79 illustrates the Voltage Burn In Circuit VBIN.
FIG. 80 illustrates the VDD Clamp Circuit VDDCLAMP.
FIG. 80.1 illustrates the Voltage Clamp Circuit VCLMP.
FIG. 81 illustrates the Voltage Level Multiplier VLMUX.
FIG. 82 illustrates the Voltage Array Buffer Circuit VARYBUF.
FIG. 83 illustrates the Voltage Periphery Buffer Circuit VPERBUF.
FIG. 84 illustrates the Voltage Array Driver Circuit VARYDRV.
FIG. 85 illustrates the Voltage Periphery Driver Circuit VPERDRV.
FIG. 86 illustrates the Voltage Array Driver Standby Circuit VARYDRVS.
FIG. 87 illustrates the Voltage Periphery Driver Standby Circuit VPERDRVS
FIG. 88 illustrates the Voltage Regulator Control Logic for Standby Circuit
VRCTLS.
FIG. 88.1 illustrates the Voltage Regulator Control Logic for Array Circuit
VRCTLA.
FIG. 88.2 illustrates the Voltage Regulator Control Logic for Periphery
Circuit VRCTLP.
FIG. 88.3 illustrates the Voltage Regulator Control Logic for Control
Circuit VRCTLC.
FIG. 89.0 illustrates the Voltage Regulator VBB0 Level Detector Circuit
Zero Level Detector Circuit VRVBB0.
FIG. 90 illustrates the Voltage Bit Line Reference Circuit VBLR.
FIG. 90.1 illustrates the Bit Line Reference Switch Circuit, BLRSW.
FIG. 90.2 illustrates the Voltage Top Plate Generator, VPLT.
FIG. 90.3 illustrates the Voltage Top Plate Switch, VPLTSW.
FIG. 90.4 illustrates the BIHO Circuit.
FIG. 90.5 illustrates the VREFINIT circuit.
FIG. 90.6 illustrates the VDDREF, or VDD Reference Circuit.
FIG. 91 illustrates the DFT Over Voltage Circuit, TLOV.
FIG. 92 illustrates the DFT Over Voltage Latch Circuit, TVOVL.
FIG. 93 illustrates the DFT initialized Circuit, TLINI.
FIG. 94 illustrates the DFT Ras.sub.-- Only Refresh Circuit, TLROR.
FIG. 95 illustrates the DFT Exit Circuit, TLEX.
FIG. 96 illustrates the DFT Jedec Mode Circuit, TLJDC.
FIG. 97 illustrates the DFT Row Address Latch Circuit, TLRAL. Code in
Appendix A45.
FIG. 98 illustrates the DFT Address Key Decoder Circuit, TLKEY.
FIG. 99 illustrates the DFT Storage Cell Stress Latch Circuit, TLSCSL.
Note: There is no FIG. 100.
FIG. 101 illustrates the DFT Mode Circuit, TLMODE.
FIG. 102 illustrates the DFT Parallel Test Data High Circuit, TLPTDH.
FIG. 103 illustrates the DFT Jedec Multiplex Circuit, TLJDCMX.
FIG. 104 illustrates the DFT Parallel Test Expected Data Circuit, TLPTED.
FIG. 105 illustrates the DFT Parallel Test X1 Circuit, TLPTX1.
FIG. 106 illustrates the DFT Word Line Comparator Circuit, TLWLC.
FIG. 106.1 illustrates the DFT Word Line Leakage OR Gate Circuit, TLWLOR.
FIG. 107 illustrates the DFT Word Line Leakage Multiplexor Circuit,
TLWLLMX.
FIG. 108 illustrates the DFT Redundancy Signature Circuit, TLRS. FIG. 109
illustrates the DFT Row Redundancy Roll Call Circuit, TLRCALL.
FIG. 110 illustrates the DFT Column Redundancy Row Call Circuit, TLCCALL.
FIG. 111 is a Block Diagram illustrating the VBB Circuits.
FIG. 112 illustrates the Low Power Oscillator Circuit, LPOSC.
FIG. 113 illustrates the VBB Low Power Pump Circuit, VBBLPP.
FIG. 114 illustrates the High Power Oscillator Circuit HPOSC.
FIG. 115 illustrates the VBB High Power Pump Circuit, VBBHPP.
FIG. 116 illustrates the Power up Boost Oscillator Circuit, BOSC.
FIG. 117 illustrates the VBB Booster Pump Circuit, VBBPB.
FIG. 118 illustrates the VBB Detector Circuit, VBBDET.
FIG. 119 illustrates the Level Detector Circuit, LVLDET.
FIG. 120 illustrates the Power Up Detector Circuit, PUD.
FIG. 121 illustrates the Pre Reset and Initialization Detector Circuit,
PRERID.
FIG. 122 illustrates the CREDSP Circuit.
FIG. 123 illustrates the RRDSP Circuit.
FIG. 124 illustrates the Row Redundancy Address Test Circuit, RRATST.
FIG. 125 illustrates the TPLHO Circuit, or the Top Plate Holdoff Circuit.
FIG. 126 illustrates the TTLCLK Circuit, or the TTL Clock Circuit.
FIG. 127 illustrates the RS Latch, RSQ.
FIG. 128 illustrates the RS Latch, RS.
FIG. 129 illustrates the RS Latch, RS.sub.-- 3.
FIG. 130 illustrates the TLPTSELA Circuit.
FIG. 131 illustrates the Multiplexor Circuit, SMUX.
FIG. 132 illustrates the Delay Element, SDEL1.
FIG. 133 illustrates the Delay Element SDEL2.
FIG. 134 illustrates the Delay Element SDEL2EXT.
FIG. 135 illustrates the Delay Element SDEL4.
FIG. 136 illustrates the logic Circuit XNOR.
FIG. 137 illustrates the Level Shift Circuit, LVLSHF.
FIG. 138 illustrates the Buffer Circuit, TTLADD.
FIG. 139 illustrates the Buffer Circuit, TTLDATA.
FIG. 140 illustrates the Sample and Hold Circuit, SAMHLD.
FIG. 141 illustrates the NAND Gate, NAND4.
FIG. 142 illustrates the NAND gate NAND3.
FIG. 143 illustrates the NAND gate NAND2.
FIG. 144 illustrates the NOR Gate NOR3.
FIG. 145 illustrates the NOR Gate NOR2.
FIG. 146 illustrates the Inverter INV.
FIG. 147 illustrates the Inverter INVL.
FIG. 148 illustrates the Circuit ESD.
FIG. 149 illustrates the Circuit ESD.sub.-- VEXT.
FIG. 150 is a block diagram illustrating the memory cell addressing
sequence.
FIG. 151 is a block diagram illustrating the sense amp configuration for a
memory quadrant.
FIG. 152 is a block diagram further illustrating a portion of the sense amp
configuration for a memory quadrant.
FIG. 153 is a block diagram further illustrating a portion of the sense amp
configuration for a memory quadrant.
FIG. 154 is a system level diagram illustrating the Local I/O to Global I/O
decoding for one quadrant of memory.
FIG. 155 is a partial block diagram of the row addressing scheme.
FIG. 156 is a partial block diagram of the column addressing scheme.
FIG. 157 is read cycle timing diagram.
FIG. 158 is an early write cycle timing diagram.
FIG. 159 is a write cycle timing diagram.
FIG. 160 is a read-write cycle timing diagram.
FIG. 161 is an enhanced page-mode read cycle timing diagram.
FIG. 162 is an enhanced page-mode write cycle timing diagram.
FIG. 163 is an enhanced page-mode read-write cycle timing diagram.
FIG. 164 is a RAS.sub.-- only refresh cycle timing diagram.
FIG. 165 is an automatic CAS.sub.-- before RAS.sub.-- refresh cycle timing
diagram.
FIG. 166 is a hidden refresh cycle (READ) cycle timing diagram.
FIG. 167 is a hidden refresh cycle (WRITE) cycle timing diagram.
FIG. 168 is a test mode entry (WCBR) cycle timing diagram.
FIG. 169 is a partial block diagram illustrating the data path during a
read operation.
FIG. 170 is a partial block diagram illustrating the data path during a
write operation.
FIG. 171 is a flow chart of the inital power up sequence of the memory
chip.
FIG. 172 is a flow chart of the inital power up sequence of the memory chip
with an established substrate bias voltage Vbb.
FIG. 173 is a general flow and timing diagram of the substrate bias voltage
Vbb.
FIG. 174 is a signal diagram of the LVLDET circuit 119.
FIG. 175 is a system level block diagram illustrating the DRAM of FIG. 0.1
incorporated into a computer system.
DESCRIPTION OF THE APPENDICES
Note: The information contained in the Appendices is incorporated by
reference into this application.
APPENDIX A1 depicts the table of Row Factor codes. The Row Factor codes
showed the relationship between the RF signals and the RAX, RAW signals.
The RFR signals are outputs of the twelve instances of schematic 9.0.
APPENDIX A3 depicts the Row Decoder Driver codes. The Row Decoder Driver
circuit shown in schematic 12.0 is used 32 times in each of the four
quadrants of the circuit. The RDDR.sub.-- CODE table depicted in Appendix
A3 explains the relationships between the output signals, RDj0k0 through
RDj7k3, to the signals in each quadrant.
APPENDICES A5 and A7 depict the Row Redundancy Address codes in two tables,
the first labeled RRA.sub.-- CODE1 and the second labeled RRA.sub.--
CODE2. Schematic 14.0, the Row Redundancy Address circuit, is used 120
times in the chip. Tables RRA.sub.-- CODE1 and RRQA.sub.-- CODE2, shown in
appendix pages A5 and A7 respectively, illustrate how the 120 instances of
the RRA circuit are used in the chip to produce 120 output signals labeled
RRA0-RRA119.
APPENDIX A9 depicts the Bank Select Codes. The Bank Select Codes illustrate
how the 15 instances of the BNKSL circuit, schematic 25.0, are used to
produce 16 unique outputs for each quadrant.
APPENDIX A11 depicts the Sense Amplifier codes. The SA circuit, schematic
31.0, is used 7,680 times in each quadrant. The SA.sub.-- CODE table
illustrates how these instances of the SA circuit are connected.
APPENDIX A13 depicts the Column Factor Codes. The Column Factor codes
illustrate how the Column Factor circuits are used. There are 8 instances
of the column factor circuits CF07, schematic 36.0, eight instances per
quadrant of column factor drivers circuit CF07DR, schematic 36.1, and
eight instances of the column factor circuits CF815, schematic 36.2. The
CF.sub.-- CODE table illustrated in Appendix A13 indicates how these
circuits are connected.
APPENDIX A15 depicts the Quadrant Select Codes. The Quadrant Select Codes
illustrate the decoding scheme for the selection of the active quadrant.
The quadrant select circuit is illustrated in schematic 50.0. Referring to
the QDDEC.sub.-- CODE table one may determine which of the four quadrants
is the currently selected quadrant according to the schematic 50.0.
APPENDIX A17 and A19 illustrate the codes for the Global Amplifier Select
End circuit and the Global Amplifier Select circuit, respectively. The
Global Amplifier Select circuits perform a one of eight decode. The codes
shown in the appendix pages, in combination with schematic pages 51.0 and
52.0, illustrate how the decoding is done.
APPENDIX A21 depicts the Data Write Enable codes. The Data Write Enable
codes illustrate how the DWE.sub.-- circuit, depicted on schematic 53.0,
is used in each of the four quadrants. The circuit DWE.sub.-- is repeated
eight times for each quadrant. The table on this appendix allows the
reader to determine how these date Write Enable lines are connected.
APPENDIX A23 illustrates the I/O clamp codes. There are 34 instances of the
IOCLMP circuit, depicted on schematic 54.0, in each quadrant. The
IOCLMP.sub.-- CODE table illustrated in Appendix A23 depicts how the 34
instances of the circuit are distributed in each quadrant. Appendix page
A25 illustrates the Local IO Amplifier codes. The LIAMP circuit, depicted
on page 55.0 of the schematic, is used 34 times in each quadrant. Appendix
page A25 contains the LIAMP.sub.-- CODE table, which details how the 34
instances of the LIAMP circuit are distributed in each quadrant.
APPENDIX A27 depicts the Global IO Amplifier codes. The Global IO amplifier
circuit, illustrated on FIG. 56.0, is used eight times in each of the four
quadrants. The table on Appendix A27, GIAMP.sub.-- CODE, details how the
eight GIAMP circuits in each quadrant are connected.
APPENDIX A29 illustrates the IOMUX.sub.-- CODE table. The IOMUX circuit,
illustrated on FIG. 57.0, is used in three quadrants, quadrant 0, 1 and 2.
The IOMUX.sub.-- CODE table details how each instance of the IOMUX circuit
is connected.
APPENDIX A30 depicts the POUTBUF.sub.-- CODE table. The POUTBUF circuit,
illustrated on FIG. 59.0 is used in three quadrants, quadrants 0, 1, and
2. The POUTBUF.sub.-- CODE table details how each instance of the POUTBUF
circuit is connected.
APPENDIX A31 depicts the OUTBUF.sub.-- CODE table. The OUTBUF circuit,
illustrated on FIG. 60.0, is used in three of the four quadrants,
quadrants 0, 1 and 2. The table on this page of the Appendix,
OUTBUF.sub.-- CODE, details how each of the three circuits is connected.
APPENDIX A33 depicts the INBUF.sub.-- CODE table. The INBUF circuit,
illustrated on FIG. 61.0, is used in three of the four quadrants,
quadrants 0, 1 and 2. The table on page A33 depicts how each of the three
occurrances of the INBUF circuit are connected.
APPENDIX A35 illustrates the Column Redundancy Row Address Code table. The
Column Redundancy Row Address Code table is used to depict how the circuit
CRRA, illustrated on FIG. 38.0, is used in the DRAM. The CRRA circuit is
used 36 times in the DRAM, and the table CRRA.sub.-- CODE depicted on
Appendix page A35 details how the 36 instances of the circuit are
connected.
APPENDICES A37 and A39 depict the CRCA.sub.-- CODE tables. The Column
Redundancy Column Address Circuit, illustrated on FIG. 39.0, is used 96
times in the DRAM. The tables on Appendix pages A37 and A39 detail how the
96 occurances of the CRCA circuit are connected.
APPENDIX A41 illustrates the CRYS.sub.-- CODE table. The CRYS circuit,
illustrated on FIG. 44.0, is used 24 times in the DRAM. The CRYS.sub.--
CODE table depicted on Appendix page A41 details how the 24 occurances of
the CRYS circuit are connected.
APPENDIX A43 illustrates the substrate characterization data. The substrate
pump system on the DRAM, or the VBB system, is depicted in several FIGS.
previously described. The substrate pump characterization data shows
timing and power information for the substrate pump circuits.
APPENDIX A45 depicts the decoding for the DFT test logic Row Address Latch
circuit, which is illustrated on FIG. 97.0, labeled TLRAL. The table on
the Appendix page A45 shows the output values of the circuit TLRAL for
several combinations of the inputs.
APPENDIX A47 describes the CATD circuit operation, illustrated on FIG.
47.0.
APPENDIX A48 depicts the function of the Row Address-6 blocks of the
circuit illustrated on FIG. 155.
APPENDIX A49 depicts the function of the Column Address-6 blocks
illustrated on FIG. 156.
APPENDIX A50 illustrates timing cycle data for the DRAM.
APPENDIX A51 describes the functions of selected blocks used on FIG. 178.
APPENDIX A52 is a table illustrating the state functions of the array
driver and the periphery driver circuitry.
APPENDICES A53 to A57 contain the signal from-to list for the DRAM. The
first column contains the signal name. The second and third columns
contain the circuit name and corresponding FIG. number that the signal is
output from. The fourth and fifth columns contain the circuit name and the
corresponding FIG. number that the signal is input to.
APPENDIX A58 contains a name decoding scheme for the electrical schematics
described in the figures. Those electrical schematics that are used
multiple times are shown only once in the figures. APPENDIX A58 depicts
how to determine the names of signals connected to a particular instance
of a replicated circuit.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
FIG. 0.1 illustrates a 16 Megabit Dynamic Random Access Memory Chip
referred to as a 16 MB DRAM. The chip size is about 325.times.660 mm. The
chip is partitioned into four memory array quadrants. Each memory array
quadrant contains 4 Megabits. A 4 MB memory array quadrant contains 16
memory blocks. Each memory block contains 256 Kilobits. The Column
Decoders lie along the vertical axis of the chip adjacent to their
respective memory array quadrants. The ROW decoders lie along the
horizontal axis of the chip, adjacent to their respective memory array
quadrants. The periphery circuits containing such devices as the input and
output buffers and the timing and control circuits are centrally located
along both horizontal the vertical axis of the chip. The bond pads are
centrally located along the horizontal axis of the chip.
FIG. 0.11 is a graph orientation drawing illustrating how to connect FIGS.
0.11A1-0.11A5, FIGS. 0.11B1-0.11B5, FIGS. 0.11C1-0.11C5, FIGS.
0.11D1-0.11D5, FIGS. 0.11E1-0.11E5, 0.11F1-0.11F5, and FIGS.
0.11G1-0.11G5. These figures are connected by placing them flat so that
the A1-G5 reference characters of each figure are on the bottom left hand
corner. The connected figures form a top view block diagram of the 16 MB
DRAM of FIG. 0.1.
FIG. 0.2 is a top view drawing illustrating the package/pin out of the
device. The chip is center bonded and encapsulated in a thin plastic,
small outline J-type package. Among other features, the DRAM is bond
programmable as either a X1 or a X4 device. The pin designations for both
the X1 and X4 modes of operation are illustrated.
FIG. 0.3 is a three-dimensional view of the encapsulated chip wherein the
encapsulating plastic is rendered transparent. The pin designations shown
correspond to the X4 option. The TSOJ package is of the lead over chip
with center bond (LOCCB) type. Basically, the chip lies underneath the
lead fingers. A polyimide tape attaches the chip to the lead fingers. Gold
wires are wire-bonded from the lead fingers to the center bonding pads of
the chip.
FIG. 0.4 is an assembly view of the packaging concept and FIG. 0.5 is a
cross-section view of the packaged device.
FIG. 0.6 is a diagram illustrating the names and sequence of the bond pads.
The sequence for both the X1 and the X4 options are illustrated. EXT BLR
is a pad that is for in-house only. The brackets, such as those for bond
pad 4 and 25 indicate that this is a bond pad option.
General characteristics of the 16 MB DRAM device of FIG. 0.1 follow. The
device receives external VDD of typically 5 volts. On chip internal
voltage regulation powers the memory arrays at 3.3 volts and the periphery
circuits at 4.0 volts to reduce power consumption and channel hot carrier
effects. The substrate is biased at -2 volts. The organization is bond
programmable X1/X4. The enhanced page mode is the main option, with a
metal mask programmable option for a write per bit (data mask) operation.
The main option for the refresh scheme is 4096 cycles at 64 ms. However,
the DRAM is bond programmable for 2048 cycle refresh.
The DRAM has numerous design-for-test features. Test mode entry 1 is
through WCBR with no address key for 16X internal parallel test with mode
data compare. Test mode entry 2 is WCBR with over-voltage and address key
only thereafter (8 volts on A11), Exit from test mode occurs from any
refresh cycle (CBR or RAS only). Test mode entry 1 is the industry
standard 16X parallel test. This test is similar to those use on the 1 MB
and 4 MB DRAMS, except that 16 bits are compared simultaneously instead of
8 bits. The valid address keys are A0, A1, A2, and A6. Test mode entry 2
contains numerous tests. There is a 32X parallel test with data compare
and a 16X parallel test with data compare. Different hexadecimal addresses
are keyed for the different parallel tests. A storage cell stress test and
a VDD margin test allows connection of the external VDD to internal VARY
and VPERI through the P-channel devices. Other tests include a redundancy
signature test, a row redundancy roll call test, a column redundancy roll
call test, a row transfer test, a word-line leakage detection test, clear
concurrent test modes, and a reset to normal mode. The DRAM also contains
a test validation method that indicates if it has remained in a test mode.
Although not illustrated in FIG. 0.1, for clarity, the DRAM contains
redundancy features for defect elimination. It has four redundant rows per
256K memory block. All four may be used at one time. There are 3 decoders
per redundant row and 11 row addresses per redundant row decoder. It uses
fuses for row redundancy with, on-average, 10 fuses blown for a single
repair. The row redundancy uses a two stage programmable concept to more
efficiently enable repair. There are 12 redundant columns per quadrant and
four decoders per redundant column. There are 8 column addresses and 3 row
addresses per decoder. The total fuse count for column repair is about, on
average, 10 fuses blown for a single repair. Column redundancy also has a
two-stage programmable feature to more efficiently enable repair.
FIG. 0.7 is a top view of the capacitor cell layout. The bit lines are
poly-3 (TiSi.sub.2) polyside. No bitline reference is used and the
bitlines are triple twisted for noise immunity. The bit line voltage is
about 3.3 volts. The word lines are segmented poly-2. They are strapped
every 64 bits with metal2. The memory cells are of the modified trench
capacitor type and may be formed by a process such as disclosed in the
following co-pending and co-assigned applications, all filed, Jul. 25,
1989:
Serial #385,441;
Serial #385,601;
Serial #385,328;
Serial #385,344; and
Serial #385,340.
Alternative suitable memory cells of the stacked trench-type are disclosed
in co-pending and co-assigned application Serial #385,327 also filed Jul.
25, 1989.
In FIG. 0.7, the dimensions include a 1.6 um bit-line pitch by 3.0 um
double word line pitch, with a cell size of about 4.8 um.sup.2 obtained
through 0.6 micron technology. The trench opening is about 0.8
um.times.0.8 um. The trench-to-trench space is about 1.1 um and the trench
depth is about 6.0 um. The dielectric is of nitride/oxide, having a
thickness of about 65A. Field plate isolation is utilized. The transistors
have thin gate oxide. FIG. 0.8 is a cross-sectional view of the modified
trench capacitor cell and FIG. 0.9 is a side view of the trench capicator
cell.
The structural description for the various circuits contained in the DRAM
of FIG. 0.1 and the FIGS. 0.11A1 through 0.11G5 is given next. It is to be
noted and understood that the prefix "X:" precedes the device reference
characters in the circuits next described, wherein "X" corresponds to the
FIG. number of the circuit. For clarity, "X:" is not physically written on
these drawings. The codes the circuits having are contained in the
Appendices. Appendices A53-A57 contain a signal from-to list for the
electrical schematics. Appendix A58 is a signal description key for the
signals used in the electrical schematics.
FIG. 1 is an illustration of the Row Clock Logic circuit, RCL. The Row
Clock Logic circuit has four input signals and three output signals. The
first input signal, EXREF, is coupled to the first input of the XTTLCLK
block, which is labeled 1:XTTLCLK. The second input signal, RID, is
coupled to the second input, not counting the VPERI supply connection of
XTTLCLK, of the TTLCLK circuit through two serially connected delay
elements; 1:XSDEL4, 1:XSDEL4.sub.-- 1 and 1:XSDEL4.sub.-- 2. The third
input signal, RAS.sub.--, is coupled to the third input of the TTLCLK
block. The fourth input signal, RAN, is coupled to the second input of the
NAND gate 1:ND1 through the inverter 1:IV2.
The Row Clock Logic circuit has 3 output signals. Node 1:N1, the output
signal of the TTTLCLK circuit, is coupled to the first output signal RL1
through three serially connected inverters; 1:IV1, 1:IV3, and 1:IV10. Node
1:N1, the output of the TTLCLK circuit, is further coupled to the output
signal RL1.sub.-- through four serially connected inverters; 1:IV1, 1:IV4,
1:IV11, and 1:IV9. Node 1:N11, the output of the inverter 1:IV4, is
coupled to the first input of NAND gate 1:ND1. The output of NAND gate
1:ND1 is coupled to the input of delay element 1:XDL4 through the inverter
1:IV5. The output of delay element 1:XDL4 is coupled to the first input of
the switch 1:XSW1 through the delay element 1:XDL1. The output of delay
element 1:XDL1 is further coupled to the second input of the SWITCH 1:SW1
through the delay element 1:XDL2. The output of the delay element 1:XDL2
is further coupled to the third input of the SWITCH 1:XSW1 through delay
element 1:XDL3. The output of the SWITCH 1:SW1 is coupled to the output
signal RL2 through three serially connected inverters; 1:IV6, 1:IV7, and
1:IV8.
FIG. 2 is an illustration of the Column Logic circuit, CL1. The Column
Logic circuit has four input signals and three output signals. The first
input signal, RL1, is coupled to the input of the inverter 2:IV1. The
second input signal, EXREF, is coupled to the first input of the XTTLCLK
circuit, which is labeled 2:XTTLCLK. The third input signal, CAS.sub.--,
is coupled to the fourth input of the TTLCLK circuit. The fourth input
signal, RID, is coupled to the second input of the TTLCLK circuit, coupled
through the NOR gate 2:NR1 and the inverter 2:IV6. The output node of
inverter 2:IV1 is coupled to the input of the delay element
2:XSDEL1.sub.-- 1, the B inputs of the SWITCHES 2:SW1 and 2:SW2, and the
third input of the XTTLCLK circuit. The output of the delay element
XSDEL1.sub.-- 1 is coupled to the A input of the switch 2:SW1 and to the A
input of the SWITCH 2:SW2. The output of the SWITCH 2:SW1, node 2:N3, is
coupled to the A inputs of the SWITCHES 2:SW3 and 2:SW4 through the delay
element 2:XSDEL1.sub.-- 2. The output of the SWITCH 2:SW2 is coupled to
the B inputs of the SWITCHES 2:SW3 and 2:SW4. The output of the switch
2:SW3 is coupled to the A inputs of the SWITCHES 2:SW5 and 2:SW6 through
the delay element 2:XSDEL1.sub.-- 3. The output of the SWITCH 2:SW4 is
coupled to the B inputs of the SWITCHES 2:SW5 and 2:SW6. The output of the
SWITCH 2:SW5 is coupled to the A input of the SWITCH 2:SW7 through the
delay element 2:XSDEL1.sub.-- 4. The output of the SWITCH 2:SW6. Node
2:N10 is coupled to the B inputs of the SWITCH 2:SW7. The output of the
switch 2:SW7 is coupled to the input of the NAND gate 2:ND1 through the
inverter 2:IV2. The output of the NAND gate 2:ND1 is coupled to the output
signal RBC.sub.-- EN.sub.--. The output of the circuit TTLCLK node 2:N15
is coupled to the output signal CL1.sub.-- through 2 serially connected
inverters; 2:IV3 and 2:IV4. The output of the block TTLCLK is further
coupled to the input of the NAND gate 2:ND1. The output of the block
TTLCLK is also coupled to the input of the NAND gate 2:ND2 through the
inverter 2:IV5. The output of the SWITCH 2:SW7, node 2:N12, is coupled to
the input of the NAND gate 2:ND2 through the inverter 2:IV2. The output of
the NAND gate 2:ND2 is coupled to the output signal CBR.sub.-- EN.sub.--.
The output signal CL1.sub.-- is further coupled to the input of the NOR
gate 2:NR1.
FIG. 3 illustrates the RAS before CAS or RBC circuit. The RBC circuit has
five input signals and six output signals. The first input signal,
RBC.sub.-- EN.sub.--, is coupled to the first input of the NOR gate 3:NR1
and further coupled to the third input of the NAND gate 3:ND1. The second
signal, CBR.sub.-- EN.sub.--, is coupled to the second input of the NOR
gate 3:NR2. The third input signal, RID, is coupled to the first input of
the NOR gate 2:NR4. The fourth input signal, RBC.sub.-- RESET, is coupled
to the second input of the NOR gate 3:NR4. The fifth input signal,
TLRCOPY, is coupled to the third input of the RS latch circuit RS.sub.--
3; which is labeled 3:XRS.sub.-- 3. The output of the NOR gate 3:NR4 is
coupled through the inv | | |
