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Description  |
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TECHNICAL FIELD
This invention relates to an electronic circuit, and method of its use, for
controlling an array of memory devices, as well as for testing the devices
and selectively correcting any errors found therein.
BACKGROUND OF THE INVENTION
Continued advances in the design of Random Access Memory devices (RAMs) has
led to tremendous increases in their storage capacity. The storage
capacity of individual RAMs has risen from 4K bits to 4 megabits within a
relatively short time. In only a few years, 16-megabit RAMs are expected.
The low cost of present-day RAMs now makes it practical to employ large
arrays of such RAMs in computers and computer-based systems. When found in
such computers and computer-based systems, such RAMs are arrayed on one or
more printed wiring boards, usually called "memory boards."
As the storage capacity of present-day RAMs has increased, so too has the
time required to test RAMs arrayed on memory boards by conventional
testing techniques which typically involve software-based testing
algorithms executed by a microprocessor. The simplest method of testing an
array of RAMs is to write a first binary bit (e.g., a "1") into each
successive storage location and then read the location to determine if the
previously-written bit appears. Thereafter, a second binary bit (i.e., a
"0") is written into each successive storage location and then a read
operation is performed to see if indeed that bit now appears. (Whether a
"1" or "0" is written first is immaterial.) If the bit read from a RAM
location is different from the bit previously written into the same
location, then a fault exists.
Algorithms for testing an array of RAMs by successively writing and reading
"1"s and "0"s into successive locations are generally known as "marching"
algorithms. The simplest marching algorithm is carried out by writing and
reading a "1" into each successive RAM location followed by writing and
then reading a "0" writing and then reading a "0" (or vice versa) into
each such location. As may be appreciated, such a test requires accessing
each memory location in each RAM in the array four separate times. For
this reason, such a marching algorithm is said to have a complexity of 4N.
More sophisticated marching algorithms, which require accessing each
location more times, have a correspondingly greater complexity. Marching
algorithms having a complexity of 14N or even 30N are not unusual.
The greater the number of times each storage location of each RAM in an
array must be accessed, the longer the time for testing since there is a
finite time (e.g., 80 nanoseconds) required to access each location. Even
for a very fast microprocessor running at a speed as high as 33 MHz, the
time required for the microprocessor to test a memory board having a large
array of RAMs by executing a simple marching algorithm can be long.
Thus, there is a need for a circuit especially adapted for testing an array
of RAMs in a rapid and efficient manner.
SUMMARY OF THE INVENTION
Briefly, in accordance with the invention, a circuit is provided for
controlling as well as testing an array of RAMs. The circuit of the
invention includes a controller which serves to initiate an access of a
storage location in one of the RAMs corresponding to a user-prescribed
address. In addition, the controller is also operative to initiate a
user-prescribed marching test of the memory locations during selected
intervals. In addition to the controller, the invention also includes a
data path section which serves to store data to be written to and read
from the accessed memory location as well as to detect parity errors (if
any) in the user-prescribed address and in data to be written to the RAMs
and errors, if any, in the memory locations detected during execution of
the user-prescribed march test. The circuit of the invention, which
includes specific elements for initiating testing of an array of RAMs and
for detecting errors during testing, can carry out testing of the RAMs
very rapidly, even faster than a conventional microprocessor.
In a preferred embodiment of the invention, an interface is provided to
allow the circuit to communicate test information and commands across a
four-wire boundary scan port to facilitate boundary scan testing of the
circuit initiated by an external test system.
BRIEF DESCRIPTION OF THE DRAWING
FIG. 1 is a block schematic diagram of a circuit, in accordance with the
invention, for controlling a bank of RAMs and for testing the RAMs in each
bank to detect faults, if any, therein;
FIG. 2 is a map of a set of registers within a first register array in the
circuit of FIG. 1
FIG. 3 is a map of the bit fields within a command register in the array of
FIG. 2;
FIG. 4 is a map of the bit fields within a status register in the array of
FIG. 2;
FIG. 5 is a map of the bit fields within a march element, a number of which
are stored in the registers in FIG. 2;
FIG. 6 is a map of the bit fields within an error flag register in the
array of FIG. 2;
FIG. 7 is a table of the operation codes produced by an opcode generator
within the circuit of FIG. 1;
FIG. 8 is a block schematic diagram of a state machine within the circuit
of FIG. 1;
FIG. 9 is a table showing the state traversals of the state machine of FIG.
8 for each of a plurality of different operations executed by the circuit
of FIG. 1;
FIG. 10 is a block schematic diagram of a march test delay and
initialization logic unit within the circuit of FIG. 1;
FIG. 11 is a map of a set of registers within a second register array in
the circuit of FIG. 1;
FIG. 12 is a map of the bit fields within a first command register in the
array of FIG. 11;
FIG. 13 is a map of the bit fields within a first status register in the
array of FIG. 11;
FIG. 14 is a block schematic diagram of an march test pattern generator and
error detector unit within the circuit of FIG. 1;
FIG. 15 is a block schematic diagram of an interface section within the
circuit of FIG. 1; and
FIGS. 16 and 17 collectively illustrate a flowchart diagram of a marching
algorithm used to test the RAMs of FIG. 1.
DETAILED DESCRIPTION
FIG. 1 is a block diagram of a control and test circuit 10 in accordance
with the invention for controlling and testing up to eight separate banks
12 of conventional RAMs 14.sub.1, 14.sub.2, 14.sub.3 . . . 14.sub.n (only
one bank of RAMs being illustrated). The RAM banks 12, together with the
test and control circuit 10, are carried by a circuit board 15. The number
n of RAMs 14.sub.1, 14.sub.2, 14.sub.3 . . . 14.sub.n in each bank 12
depends both on the desired width of the data words to be stored as well
as the number of check or parity bits associated with each stored word.
In a preferred embodiment, the length of each data word stored by each RAM
bank 12 is thirty-two bits, while seven additional check bits are stored
with each data word for parity checking purposes. Thus, the total width of
each data word and associated check bit sum is thirty-nine bits. In a
preferred embodiment, each RAM 14.sub.1, 14.sub.2, 14.sub.3 . . . 14.sub.n
in each bank 12 is chosen to be of the 4M.times.1 variety and thus, each
bank includes thirty-nine separate RAMs 14.sub.1 -14.sub.39. Data is
entered to, and retrieved from, the RAMs 14.sub.1 -14.sub.39 in the banks
12 through a data bus 16 while address information is supplied to each
bank on an address bus 18. It should be understood that each bank 12 could
be comprised of a lesser or greater number of RAMs 14.sub.1 -14.sub.n and
the configuration of the RAMs in the banks may be different, depending on
the desired width of the data word to be stored and the number of
associated check bits. For example, the width of each data word to be
stored could be as wide as 256 bits, necessitating that each bank 12 be
comprised of the corresponding number of RAMs required to store a word of
such a width and the parity bits associated therewith.
The control and test circuit 10 of the invention is comprised of a control
section 20, a data path (i.e., error detection and correction section) 22,
and an interface section 24. As will be described in greater detail below,
the control section 20 serves to control the addressing as well as the
testing of the RAMs 14.sub.1, 14.sub.2, 14.sub.3 . . . 14.sub.n in each
bank 12. The data path section 22 serves to detect the presence of any
errors during execution of a user-prescribed march test algorithm
initiated by the control section 20. Also, the data path section 22 serves
to detect check bit errors and to correct any single-bit memory errors.
The interface section 24, described in greater detail with respect to FIG.
16, provides the control and test circuit 10 with an ability to
communicate with an external test system 25 through a four-wire boundary
scan port meeting the IEEE 1149.1 Standard, as described in the document
IEEE 1149.1 Boundary Scan Access Port and Boundary-Scan Architecture,
available from the IEEE, New York, N.Y.
Control Section 20
As seen in FIG. 1, the control section 20 includes an address queue 26
which takes the form of a first-in, first-out (FIFO) register array
comprised of four separate registers 26.sub.1, 26.sub.2, 26.sub.3 and
26.sub.4, each thirty bits wide. Each of the four registers 26.sub.1,
26.sub.2, 26.sub.3 and 26.sub.4 is supplied, via a bus 27, with a separate
one of four, thirty-bit address words (SA[31:02]) from an external source
(not shown), such as a microprocessor or the like, coupled to the RAM
banks 12. Each address word SA[31:02] is indicative of the address of a
storage location in one of the RAM banks 12 or a storage location in the
control section 20 itself. By configuring the address queue 26 of four
separate registers 26.sub.1, 26.sub.2, 26.sub.3 and 26.sub.4, an address
word stored in one of the four registers can be read while a new address
word can be entered to another register in the queue to provide for more
rapid access.
Each address word SA[31:02] is supplied with a four-bit parity word
SAP0-SAP3. The parity word SAP0-SAP3 supplied with each address word
SA[31:02] is not stored in the address queue 26, but rather, is stored in
a latch 28. After being received at the latch 28, the parity word
SAP0-SAP3 is passed to a parity-checking circuit 30, configured of an
exclusive OR gate tree (not shown). The parity-checking circuit 30, when
rendered operative in a manner described hereinafter, evaluates the parity
word SAP0-SAP3 to determine if the address word SA[31:02] has the proper
parity.
The action taken by the parity-checking circuit 30 if the parity word is
found to be in error depends on whether the address word SA[31:02] refers
to a storage location in one of the RAM banks 12 or to a storage location
in the circuit 10 itself. If the address word SA[31:02] refers to a
storage location in a RAM bank 12, and the associated parity word
SAP0-SAP3 indicates an incorrect parity, then the address queue 26 is
inhibited from placing such an address word on the bus 18. On the other
hand, if the address word SA[31:02] corresponds to a storage location in
the circuit 10, and the associated parity word SAP0-SAP3 indicates an
incorrect parity, the address queue 26 nonetheless will output the address
word. In this way, communication with the circuit 10 is permitted, even
though the proper storage location therein may be addressed.
The address word SA[31:02] output by the address queue 26 is input to an
address shifter 32, comprised of a combinatorial circuit, for selectively
shifting and deleting bits of the address word in accordance with the
memory width and page size. The page size, which is user-selected,
determines the number of consecutive storage locations which may be
accessed during page burst mode operation of the RAMs 14.sub.1, 14.sub.2,
14.sub.3 . . . 14.sub.n. In the preferred embodiment of the circuit 10,
the page size is typically two for a thirty-two bit wide data word. (Note
that the page size may be as large as sixteen.) The memory size influences
the number of bits in the address word SA[31:02] identifying the row and
column of the desired location to be accessed. For example, in a preferred
embodiment where each of the RAMs 14.sub.1, 14.sub.2, 14.sub.3 . . .
14.sub.n is of the 4M+1 variety, the row- and column-identifying portions
of the address word SA[31:02] are each eleven bits long.
The address-shifting circuit 32 is coupled to a row address multiplexer 34
which serves to multiplex the address word processed by the address
shifter, with a signal indicative of the memory width, to produce a signal
indicative of the row address of the desired storage location in a
particular RAM bank 12. The output of the row address multiplexer is
coupled to the input of a multiplexer 35 which feeds the address bus 16.
The address-shifting circuit 32 is also coupled to a column address
multiplexer 36. The multiplexer 36 serves to multiplex the address word
processed by the address shifter 32 with a signals indicative of the
density and width of the RAMs 14.sub.1 -14.sub.n in each bank 12 to yield
an address count for an address counter 38 whose output signal specifies
the column address of the storage location in the particular RAM bank 12.
The output of the counter 38 is input to a logic block 40 which serves to
either increment or complement the address count during page mode
addressing. The output of the logic block 38 is input to the multiplexer
35, which, as described, feeds the address bus 16. A refresh logic block
42, in the form of a counter, also feeds the multiplexer 35 to provide a
refresh address on the address bus 16.
To support the addressing of multiple RAM banks 12, the control section 20
includes an address comparator and row address strobe/column address
strobe generator unit 44. Within the unit 44 is a comparator (not shown)
which serves to compare the address word received from the address queue
26 to a prescribed list of address words to determine within which of the
banks 12 the storage location corresponding to address word SD[31:02]
lies. Based on the results of such comparison, each of a pair of logic
circuits (not shown) within the unit 44 generates a separate one of a pair
of eight-bit signals RAS 0-7 and CAS 0-7, respectively, to enable the row
and column, respectively, of the particular bank 12 containing the desired
location to be accessed. The refresh logic circuit 42, which serves to
refresh the address line 16, also serves to refresh the unit 44.
Within the control section 20 there is a register array 46 which contains
seventeen individual registers 46.sub.1 -46.sub.17 for storing command
information and data received on an input bus 47. FIG. 2 is a map of the
register array 46, identifying the addresses (in hexadecimal) of the
individual registers 46.sub.1 -46.sub.17 (with x indicating don't care
values) and the register access mode (i.e., whether the register is both a
read/write or a read-only)
The register 46.sub.1 within the register array 46 is typically thirty-two
bits wide and is hereinafter referred to as the command register because
it stores a thirty-two-bit command word which controls the operation of
the circuit 10. FIG. 3 is a map of the bit fields in the command register
46.sub.1. The status of bit 0 determines whether the control section 20
initiates a march test on one or more of the eight RAM banks 12 controlled
by the circuit 10. Bits 1-8 each enable a separate one of the eight RAM
banks 12 for testing. Bit 9 determines whether the testing of the
designated RAM bank 12 is to run to completion or is to be interrupted
when a fault is found. Bit 10 determines whether the logic block 38
increments or complements the column address output by the column address
multiplexer 36. Bits 12 and 13 reflect the number of consecutive accesses
to be completed during page mode accessing of each RAM bank 12. Bits 14
and 15 reflect the address queue depth, that is, the total number of the
registers 26.sub.1, 26.sub.2, 26.sub.3 and 26.sub.4 that are utilized to
store incoming addresses. Bits 16 and 17 determine the refresh interval.
The status of bit 18 determines whether the control section will carry out
a memory "scrubbing" operation, i.e., correction of a single faulty bit
found during a normal read operation. Bits 19-26 reflect which of the
banks 12 is currently active. Bit 28 provides the option to disable the
refresh logic circuit to facilitate external refresh commands. Bit 29
allows the parity of the address input to the address queue 26 to be set
even or odd, while bit 30 controls whether the address word SA[31:2] input
to the address queue is to be checked for parity by the parity-checking
circuit 30. Bits 11, 27 and 31 are reserved for future use.
Referring to FIG. 2, the register 46.sub.2 within the register array 46 is
typically thirty-two bits wide and is hereinafter referred to as the
status register because it stores a thirty-two-bit status word containing
information about the presence and population of the RAM banks 12. FIG. 4
is a map of the bit fields in the status register 46.sub.2. Bits 0-3 of
the status register 46.sub.2 establish a four-bit identification code for
the control section 20 of the control and test circuit 10. By control
sections of separate circuits 10 to control different RAM banks 12 on the
same circuit board 15. Bits 4-11 reflect how many banks 12 of RAMs
14.sub.1, 14.sub.2, 14.sub.3 . . . 14.sub.n are present (i.e., how many
are to be controlled and tested by the circuit 10). The bit pairs 13:12,
15:14, 17:16, 19:18, 21:20, 23:22, 25:24 and 27:26 reflect the
configuration of a separate one of the eight RAM banks 12 controlled by
the control section 20. While each of the RAMs 14.sub.1, 14.sub.2,
14.sub.3 . . . 14.sub.n has been described as being of the 4M.times.1
variety, the controller 20 is fully capable of controlling RAMs of the
256K.times.1, 256K.times.4, 1M.times.1, 1M.times.4, 4M.times.1,4M.times.4,
16M.times.1 or 16M.times.4 variety. Bit 28 is indicative of a particular
version of the circuit 10. Bits 29-31 provide an indication of which of
eight separate memory banks 12 to be tested contains a fault.
Referring to FIG. 2, the register 46.sub.3 in the register array 46 is
typically thirty-two bits wide and is referred to as the error address
register because it stores the address of the first location in the memory
banks 12 found to contain an error. The error may be non-fatal as in the
case of a single bit error or a memory march test error. In contrast, the
error may be fatal, as in the case of a multiple bit error, a write data
parity error, an address parity error or a memory bank error.
The register 46.sub.4 in the register array 46 is also typically thirty-two
bits wide and is designated as the strobe shape register, because it
stores a pattern of bits that establishes the parameters of the Row
Address Strobe (RAS) and the Column Address Strobe (CAS) signals generated
by the address comparator and RAS and CAS generator 44 of FIG. 1.
Within the register array 46 are the four registers 46.sub.5 -46.sub.8,
each typically thirty-two bits wide. Each of the registers 46.sub.5
-46.sub.8 is referred to as a march test register because the register
stores a collection of march test "elements" to be executed during testing
of a RAM bank 12. Each march test element is comprised of one or more
sequences of read and write operations. In the illustrated embodiment,
each march element may be comprised of as many as seven separate read and
write operations.
FIG. 5 is a map of the bit fields within a march test element. Bits 2:0 in
the element specify the number of read/write operations (up to seven)
specified thereby. Bit 3 specifies whether the operations comprising the
march element should be performed on successive memory locations in
ascending or descending address order. Bits 5:4 specify the nature of the
first operation of the march test (i.e., a whether the operation is to be
a read or write operation). The bit pairs 7:6, 9:8, 11:10, 13:12, 15:14
and 17:16, specify the nature of the remaining six operations,
respectively, of the march elements.
Referring to FIG. 2, the registers 46.sub.9 -46.sub.16 are typically
thirty-two bits wide, with each being designated as a "bank address
boundary register" for a corresponding one of the eight RAM banks 12. Each
bank 12 has a starting address (a "lower" address) and an ending address
(an "upper" address) for all of the memory locations in that bank. The
upper and lower addresses are referred to as the "bank boundary"
addresses. The bank boundary address for each of the eight RAM banks 12 is
stored in a separate one of the address boundary registers 46.sub.9
-46.sub.16, respectively. In this way, an incoming address can be checked
against the values in a separate one of the eight bank address boundary
registers 46.sub.9 -46.sub.16 to determine which bank is being accessed.
Referring to FIG. 2, the register array 46 also contains the register
46.sub.17 which is typically thirty-two bits wide. The register 46.sub.17
is referred to as an error flag register, as the state of the various bits
in the register reflects whether or different errors have occurred during
testing. FIG. 6 is a map of the bit fields in the register 46.sub.17. Each
of the bits 7:0 represents the presence or absence of a particular one of
eight different types of errors. Bits 31:8 are reserved for future use.
Referring to FIG. 1, within the control section 20 is an opcode generator
48, typically an encoder, which generates a four-bit operation code
("opcode"), designated by the term OPCODE[3:0], in accordance with command
signals externally input to the control section along the bus 27. The
four-bit opcode generated by the opcode generator 48 designates a
particular one of sixteen different operations to be carried out on the
RAM banks 12. FIG. 7 shows a table of the opcodes generated by the opcode
generator 48 and the operations which correspond to each opcode.
Referring to FIG. 1, the four-bit opcode generated by the opcode generator
48 of FIG. 1 is input both to the data path section 22, as well as to a
state machine 50 illustrated in FIG. 8. Referring to FIG. 8, the state
machine 50 is typically a thirteen-state machine comprised of thirteen
combinational circuits 52.sub.1, 52.sub.2, 52.sub.3 . . . 52.sub.13 and
thirteen separate flip-flops 54.sub.1, 54.sub.2, 54.sub.3 . . . 54.sub.13,
each associated with a corresponding combinational circuit. The
combinational circuits 52.sub.1 -52.sub.13 each have a set of inputs
I.sub.1, I.sub.2 . . . I.sub.n supplied with a separate one of the bits of
the opcode from the opcode generator 48 as well as selected bits from the
command register 46.sub.1. Each of the combinational circuits has a single
output O coupled the D input of a corresponding one of the flip-flops
54.sub.1, 54.sub.2, 54.sub.3 . . . 54.sub.13, respectively. Within each of
the combinational circuits 52.sub.1, 52.sub.2 , 52.sub.3 . . . 52.sub.13
is a set of logic gates (not shown) of the NAND, AND, NOR and OR variety
connected so each circuit only outputs a "1" at its output O when a
particular bit pattern is present at the input of the circuit.
When supplied with a "1" at its D input, each of the flip-flops 54.sub.1,
54.sub.2, 54.sub.3 . . . 54.sub.13 produces a separate one of a set of
logic "1" level state bits sti, st0, st1, st2, st2e, st2c, st3, st3e,
st3c, st4, st4e, st4c and stD, respectively. The combinational circuits
52.sub.1, 52.sub.2, 52.sub.3 . . . 52.sub.13 are configured so that at any
given time, only one of the state bits sti, st1, st0, st1, st2, st2e,
st2c, st3, st3e, st3c, st4, st4e, st4c and stD will be set (i.e., at a "1"
level). FIG. 6 shows the sequence of the state bits produced by the
flip-flops 54.sub.1 -54.sub.13 during each of the various operations of
the circuit 10 of FIG. 1. The state bits from the state machine 50 of FIG.
1 are distributed to various elements of the circuit 10 to effectuate a
separate one of the operations described in FIG. 6.
Referring to FIG. 1, coupled to the state machine 50 and to the address
comparator and row address strobe and column address strobe unit 44 is a
march test delay and initialization logic unit 55 which serves to initiate
execution of a march test on selected RAM banks 12. FIG. 10 is a schematic
block diagram of the logic unit 55. As seen in FIG. 10, the logic unit 55
includes an eighteen-bit temporary register 55.sub.1 for storing the
eighteen least significant bits in a successive one of the March Test (MT)
registers 46.sub.5 -46.sub.8, representing the march test elements in that
register. In practice, the march test registers 46.sub.5 -46.sub.8, each
thrity-two bits wide, are collectively treated as a single, 128-bit shift
register to facilitate shifting out of the march elements stored in these
registers in sequential fashion, starting with the register 46.sub.5
first.
To facilitate such shifting, the least significant three bits stored in the
register 55.sub.1 (representing the number of operations in the march test
element just read from a successive one of the registers 46.sub.5
-46.sub.8) are input to both an all-zeros detector (i.e., a three-input
NOR gate) 55.sub.2 and to a first adder circuit 55.sub.3. For the
condition where the least significant three bits in the register 55.sub.1
are all non-zero (indicating that the current march test element contains
one or more operations), the first adder circuit 55.sub.3 determines the
number of bits to be shifted from the march test registers 46.sub.5
-46.sub.8 in order to fetch the next march test element. The output of the
first adder 55.sub.3 is supplied to a first input of a two-input OR gate
55.sub.4 whose output signal controls the shifting of bits out of the
march test registers 46.sub.5 -46.sub.8 and into the register 55.sub.1.
The all-zeros detector 55.sub.2 has its output coupled to a second adder
circuit 55.sub.5 whose output is coupled to the second input of the OR
gate 55.sub.4. The second adder 55.sub.5 determines the number of bits to
be shifted from the registers 46.sub.5 -46.sub.8 to return to the first
march test element in the first march test register 46.sub.5 when an
all-zero condition is detected. As should be appreciated, an all-zero
condition arises when the number of operations in the current march test
element is zero. If the current march test element has no operations, then
the remaining march test elements which follow will also have zero
operations. Thus, upon encountering an all-zero condition, it is desirable
to shift through the remaining locations in the march test registers
46.sub.5 -46.sub.8 to return to the first march test element in the first
march test register.
The outputs of the adders 55.sub.3 and 55.sub.5 are coupled to a seven-bit
counter 55.sub.6 which serves to count the total number of bits shifted
out the march test registers 46.sub.5 -46.sub.8. In this way, a
determination can be made when 128 bits (the total contents of the march
test registers 46.sub.5 -46.sub.8) have been shifted out.
The fourth least significant bit stored in the register 55.sub.1, which
represents the address progression bit of the currently active march test
element, is input to a first input of a separate one of a first set of
twelve exclusive OR gates, represented collectively by the gate 55.sub.8.
The fourth least significant bit in the register 55.sub.1 is also input to
a first input of a separate one of a second set of twelve exclusive OR
gates, collectively represented by a gate 55.sub.10. Each of the first set
of twelve exclusive OR gates, represented by the gate 55.sub.8, has their
second input supplied with a separate one of the bits generated by a
twelve-bit counter 55.sub.11, the count of the counter corresponding to
the row address of the particular RAM bank 12 whose storage location is to
be accessed for testing purposes. The output of the first set of twelve
exclusive OR gates, represented by the gate 55.sub.8, is supplied to the
address comparator and row address strobe and column address strobe
generator 44 of FIG. 1.
The four most significant bits of the counter 55.sub.11 are input to a
multiplexer 55.sub.12 which is controlled by a signal indicative of the
density in the RAMs 14.sub.1 -14.sub.n in the banks 12. The output signal
of the multiplexer 55.sub.12, representing the row address of the
particular RAM bank 12 location to be accessed, is input to a second
twelve-bit counter 55.sub.13 which serves to generate a column address of
the particular RAM bank 12 to be accessed. The least significant twelve
bits of the counter 55.sub.13 is supplied to the second input of the
second set of twelve exclusive OR gates, represented by the gate
55.sub.10. The output signal of the gate 55.sub.10 is supplied to the
strobe generator unit 44.
The four most significant bits of the counter 55.sub.13 are input to a
multiplexer 55.sub.14, which like the multiplexer 55.sub.12, is controlled
by a signal indicative of the density of the RAMs 14.sub.1 -14.sub.n in
the RAM banks 12. The output signal of the multiplexer 55.sub.14,
indicative of the column of the RAM bank 12 being accessed, is input to a
counter 55.sub.16 which is typically initially loaded with data from a
register 55.sub.18 which is supplied from the status register 46.sub.2
with the number of RAM banks 12 which are present. In response to the
signal from the multiplexer 55.sub.14, the counter 55.sub.16 is
decremented. Thus the counter 55.sub.16 will output a signal of a
predetermined state when all the RAM banks 12 have been tested,
The most significant fourteen bits of the data stored in the register
55.sub.1, which represent the seven separate operations of the
currently-active march element, are input to a multiplexer 55.sub.19,
comprised of two individual 7:1 multiplexers. The multiplexer 55.sub.19 is
controlled by a three-bit counter 55.sub.20, which determines which pair
of the bits input to the multiplexer are output to a decoder 55.sub.21
which decodes the bits to yield a separate one of four signals WRITE DATA,
WRITE DATA, READ DATA and READ DATA. The signals from the decoder
55.sub.21 are supplied to the state machine 50 of FIG. 1 and to the march
test pattern generator and error detector unit 68 of FIG. 1.
Data Path Section 22
The data path section 22 includes a write data queue 56, typically a FIFO
device comprised of four registers 56.sub.1, 56.sub.2, 56.sub.3 and
56.sub.4 supplied with a separate one of four, thirty-two-bit data words
SD[31:00] input on a bus 57. Since each data word is thirty-two bits wide,
each of the registers 56.sub.1, 56.sub.2, 56.sub.3 and 56.sub.4 in the
data queue 56 is likewise thirty-two bits wide. In the event that the data
words were of a greater width (say, 256 bits wide), then each of the
registers 56.sub.1, 56.sub.2, 56.sub.3 and 56.sub.4 would be
correspondingly wider.
Supplied along with each data word SD[31:00] is a four-bit parity word
SDP[3:0] indicative of the parity of the data word. Upon receipt, each
parity word SDP[3:0] is separately stored in a latch 58 before being
supplied to a parity-checking circuit 60 of the same general construction
as the parity-checking circuit 30. The parity-checking circuit 60, when
rendered operative in the manner described, checks the parity word
SDP[3:0] to determine if the corresponding incoming data word SD[31:00]
has the proper parity. As in the case of the address queue 26, the action
taken following a determination of incorrect parity of an incoming data
word SD[31:00] depends on whether the data is to be written into one of
the RAM banks 12, or into the circuit 10. A data word SD[31:00] having an
incorrect parity will not be written into a RAM bank 12 from the write
data queue 56 but will be written from the queue into a storage location
in the circuit 10.
The data word SD[31:00] first written into the writ | | |
