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FIELD OF THE INVENTION
This invention relates to computer memory assemblies and more specifically
to the fabrications, testing and operation of large capacity, high density
memory assemblies for high speed computers having large memory
requirements.
BACKGROUND OF THE INVENTION
As computers operate at higher rates and perform more operations in a given
time, and perform tasks and operate programs which involve graphics and
graphical displays, the amount of memory required for the computer
increases dramatically and the need for higher density memory assemblies
or modules increases likewise. Graphics and graphical display computer
applications, together with the manipulation of the graphical
representation, require very large quantities of memory which must be
quickly and reliably accessible to the central processing unit and/or
related other processors in the computer.
An example of a computer with such a need for a very large amount of memory
is the IBM RISC System/6000 computer which typically may have a need for
32-500 megabytes of memory capacity.
When a computer speed approaches MIPS (million instructions per second),
the speed of processing instructions ceases to be limited by the member of
cycles per second at which the processor can operate. Rather, the
operational speed is limited by the speed of the electricity traveling
through the connectors to and from adjacent electrical elements and,
particularly, into and back from the memory in order to access and
retrieve stored data and/or access and store data in the memory. It is
necessary to minimize the length of conductors to and from and within the
memory modules in order to minimize the amount of time lost in processing.
It is necessary, therefore, to make the memory chip assemblies as compact
as possible and minimizing memory cycle response time, therefore, making
the computer more efficient.
Presently, when memory is manufactured, the memory chips are formed by
depositing conductive and semi-conductive circuits onto the surface of
silicon wafers in standard and conventional patterns. These circuits,
which when appropriately powered and accessed, either will accept "write"
commands or signals and retain them representing stored bits of data or
information or will provide electrical signals in response to "read"
commands, permitting the computer to determine the status of bits of
information stored in the memory circuits, which represents bits of data
previously stored.
The manufacturing techniques for making the particular memory chips and
memory circuits are well known conventional techniques. While these
manufacturing techniques are understood and practiced widely, they may
result in memory chips and memory circuits which will have varying
response speeds, i.e., memory response cycle times of 20, 25 or 30
nanoseconds. The varying response times occur because the manufacturing
process is subject to variables which may not be accurately enough
controlled or may not be economically controllable to yield only the
highest speeds or the desired speeds for the memory.
Further, due to problems or variables in the manufacturing process, memory
chips which may be designed to contain a multiple megabit storage capacity
may have a portion of its capacity rendered inoperable or defective. For
example, a stray airborne object or contaminate particle may be deposited
upon the surface of the chip during the manufacturing process which
results in shorting adjacent circuits or improper connections to positions
of a circuit, rendering at least that portion of the chip defective or
inoperable. One characteristic of memory chips and computer memory is that
even though a portion of a memory chip may be defective or inoperable, the
remainder of the chip may be fully functional and unaffected by the
defect. Therefore, a chip having a nominal capacity of one megabits of
data in fact may have a smaller capacity, and yet remain economically and
physically usable in a device which may use additional chips to offset the
defective shortfall or where there are smaller demands for memory
capacity.
After the memory chips have been manufactured, they may be tested to
determine their capacity for retaining data. The chips may be sorted into
categories such as one-quarter good, one-half good, or full good chips
depending upon the amount of usable and operable memory capacity on the
chip. These memory chips then can be assembled into memory modules or
memory arrays in sufficient numbers to provide the necessary minimum
amount of memory for a particular computer or application.
As advances in the design and manufacture of memory circuits and memory
chips occur and the density on the chips increases, the cost of memory
capacity has decreased. One approach has been merely to install excess
memory capacity in the computer to assure that the minimum stated memory
requirement for the computer or application is adequately met by
operational memory circuits, even though additional memory is in fact
present and usable.
One step of the manufacturing and testing procedure for the manufacture of
memory is to assemble it or connect it to test apparatus in such a manner
that it may be operated and tested; and then it is placed in an
environment of elevated temperatures and operated to cause any marginal or
weak circuits on the chip to fail prior to installation. This process is
commonly referred to as burn-in. The burn-in process causes an early
failure of marginal circuits, thereby allowing the identification of those
chips and the quantifying of the available remaining operational memory
prior to installation into a memory module or computer. Burn-in is most
efficiently accomplished when the memory modules are assembled and, thus,
most easily connected and tested. The cost of replacing defective memory
greatly increases after assembly.
Memory at the time of test may provide indications of false failures. When
false failures occur, the memory circuits themselves cannot be relied upon
and, therefore, must be detected at an early stage to prevent undue
re-work or repair costs. As an alternative, the individual testing of each
chip is prohibitively expensive.
With short response times required and large quantities of memory capacity
desired in a particular computer environment, it becomes very important to
have an adequate quantity of good and operational memory chips installed
in an appropriate assembly or module which is then installed into the
computer.
Several approaches exist in the prior art. One approach to memory
fabrication involves what is commonly referred to a memory cube. To form a
memory cube, several chips in a semi-finished state are joined together,
typically, by use of an adhesive or other bonding material to form a cube
or stack of chips. After the chips have been joined together, at least one
of the external surfaces of the assembly of chips is then ground and
polished to expose the read, write and address lines (conductors) and
power connections controlling the individual memory circuits. After the
conductors are exposed, through conventional steps of masking and vapor
deposition of metals, contact pads are formed in electrical continuity
with the respective conductors to provide an interface by which the memory
cube may be powered and operated.
One serious drawback to the memory cube fabrication procedure is that the
memory chips of the cube typically cannot be tested until such time as
adequate electrical contacts have been formed and connected to the
conductors. Therefore, the memory cube may be fabricated from untested
memory chips or chips that have not been fully tested after burn-in. If,
after assembly and fabrication of the finished memory cube, a chip within
the cube is found to be partially or completely defective, the
alternatives available to the memory fabricator are: the cube be
discarded, the cube be disassembled and the defective portions of the cube
removed, or additional memory cubes be fabricated and installed in the
system to compensate for the defective memory in the cubes within the
system if the system design permits.
Disassembling the memory cubes, breaking the bonding between chips, and
removing the defective chips from the assembly may result in damage to
otherwise good remaining chips in the memory cube.
The building of oversized or over-capacity memory assemblies to circumvent
the defect fallout associated with the manufacturing process of the chips,
can result in substantial excess costs associated with the computer. While
the cost of memory chips and memory capacity has steadily declined, if it
is necessary to install excess capacity in the computer in order to meet
at least the minimum memory requirements for the computer or its
applications, the computer manufacturer suffers substantial economic
disadvantage.
Another prior art approach to overcoming the problem of defective memory
while avoiding the economic cost of over populating the computer memory
with memory capacity in order to compensate for the defective memory, is
the use of connectors on substrates or motherboards to permit the
replacement of memory boards carrying memory chips. When a defective
memory chip is detected and need replacement, the memory board carrying
that chip may be removed by disconnecting the memory board contacts from
the connector and a replacement memory board installed. While this
approach certainly solves the problem of having to install substantial
quantities of excess memory, the expense of many connectors and associated
circuit boards for the memory chips may not be an attractive economic
alternative.
Further, use of connectors includes, within the system, additional possible
failure points where electrical continuity between the computer processor
and the memory chips may not be reliable.
Further, if the memory chips that are found to be defective or inoperative
must be removed from the memory boards, the re-work of those memory board
assemblies may damage substantially other memory chips installed on the
boards or destroy the memory board or substrate upon which the memory
chips have been mounted. A not insignificant consideration is the cost of
the re-work labor involved in such repair of the memory modules and memory
boards.
The use of memory chips bonded to memory boards or memory cubes may require
the complete assembly of the memory module prior to testing. This
eliminates opportunities early in the manufacturing and assembly process
for detecting defective memory chips and the substitution of operative
memory chips, therefore.
On the other hand, the individual testing of discrete memory chips to
determine which memory chips are partially defective and the extent of the
defects, is very expensive, time consuming and relatively inefficient.
When memory is assembled in a cube or other stack type structure and fixed
to form the module or assembly, the cooling of the memory chips becomes a
problem. As electricity is conducted to and from the chips and the
circuits formed thereon, heat is created. If the heat is not adequately
dissipated and the memory chips are not maintained at a cool operating
temperature, the resistance of the conductors becomes sufficiently high as
to interfere with proper memory operation and potentially cause the
destruction of the circuits of the memory chip itself.
Therefore, it is necessary to accommodate a cooling system in the memory
module. In the past, efforts have involved alternating the memory chips
and cooling spreaders within the memory cubes.
In other instances, air circulation between chips has been relied upon for
cooling. In some cases, the memory chips have been mounted to heat
spreaders which then extend out substantially past the edges of the chips
forming larger surfaces from which the heat may be dissipated either by
radiation or convection as air passes over the heat spreader extensions.
The more densely populated a memory module is, the more difficult to
dissipate any internally generated heat resulting from the normal
operation of the memory chips. Not only are the stacked and bonded or
cubed memory chips the most efficient from a density standpoint, but also
have the shortest read/write power and address lines. Also, they are the
most difficult to cool because heat is difficult to remove from the solid
cubic memory chip structures.
Examples of prior art which describe and show some of the aspects described
above, include Eichelberger, et al. U.S. Pat. No. 5,190,946, which shows
chips which have been bonded into a memory cube. The chips rely upon edge
contacts exposed through the surface or the edge spaces of the individual
chips together with the conductive paths interconnecting those contact
points with contact points on other chips or outside the integrated
circuit assembly.
Kato U.S. Pat. No. 5,051,865 shows chips bonded together using an adhesive,
and then hazing heat sink plates positioned intermediate some adjacent
chips to acquire and conduct away the heat.
Fassbender, et al. U.S. Pat. No. 5,019,943, illustrates a stack of
integrated circuit chips having connections adjacent at least one edge of
the circuit surface of each chip.
Baudouin, et al. U.S. Pat. No. 4,975,763, illustrates metal conductors
extended out from a circuit package for surface mounting on a circuit
board.
U.S. Pat. Nos. 4,982,264 and 5,059,557 both by Cragon, et al., illustrate
circuit chips being attached to a motherboard and connected to conductors
on the motherboard by solder connections near the edge of the chip on the
circuit face of the chip. Malhi, et al. U.S. Pat. No. 5,031,072
illustrates a plurality of integrated circuit chips inserted into
retaining slots in a silicon baseboard and solder connected from contact
points on the circuit face near the edge of the chip to contacts on the
baseboard.
U.S. Pat. No. 4,983,533 discloses electronic isolation of defective or
inoperative circuits on integrated circuit chips and specifically states
that this technique is applicable to dynamic RAMs (Random Access Memory),
static RAMs and Read-Only-Memory as well as logic units and arithmetic
units.
One may appreciate that the assembly of the memory chips, as described
above, is a substantial deterrent to easy and economical removal and
replacement of defective memory chips where a significant portion of a
memory chip is inoperative.
SUMMARY OF THE INVENTION
It is an object of the invention to enhance the testing and replacement of
defective memory chips in a memory module.
It is another object of the invention to simplify and ease assembly of
memory chips into a memory module.
It is another object of the invention to enhance the cooling of the memory
chips within the memory module while at the same time providing an easily
handled memory and heat spreader assembly.
It is a further object of the invention to support the capability of
assembly and testing without permanent attachment of all memory chips to
the memory module.
It will be understood that both the shortcomings and disadvantages of the
prior art devices may be overcome in addition to improved cost
effectiveness of the manufacture of memory modules by the memory module
described herein. The memory module is comprised of a circuit board or
substrate which may be flexible and which carries on its surface
connection points or contact pads for the power, read, write and address
lines of the memory chips.
In order to accurately position the memory chips, a chip holder is
precisely located over the circuit substrate. The chip holder typically is
provided with positioning slots which will accommodate the heat spreaders.
The heat spreaders are bonded or adhesively attached to the circuit chips.
The heat spreaders are typically heat conductive metal sheets which have
extensions that will slide into the slots of the chip holder and carry the
memory chip into the proper location relative to the contact points on the
circuit substrate.
The heat dissipation from the heat spreaders is accomplished by contacting
a flange on the heat spreader with a common heat sink. The heat sink
extends across the flanges of all the heat spreaders in the chip holder
and will absorb and dissipate the heat from many of the heat spreaders
simultaneously.
Contact between the memory chips and the circuit substrate is effected by
clamping the heat sink onto the heat spreader, which in turn forces the
memory chip toward the circuit substrate. The memory chip has formed,
either near the edge of the circuit face of the chip or on one of the side
faces of the chip, a plurality of contact pads which in turn have had
deposited thereon a solder compound; and the solder heated or reflowed to
form a series of small solder balls bonded to the contact pads and
protruding from the chip surface. The solder forms the balls when reflowed
due to surface tension of molten solder.
The circuit substrate is provided with a plurality of contacts,
corresponding to the contacts and the solder balls on the memory chips.
When the memory chips are properly positioned, the solder balls will align
with and make contact with the contact pads on the circuit substrate. The
contact pads of the circuit substrate preferably will be plated with a
palladium or a palladium alloy material in such a way as to create
dendritic crystals of palladium or the alloy extending from the surface of
the contact pads. Thus, when the solder balls are positioned onto the
contact pads, the dendritic crystals will extend upward and into contact
with the solder balls, thus assuring a mechanical contact as well as an
electrical continuity therebetween. The clamping of the heat sink to the
other components of the module and to any supporting motherboard then will
force the contact balls into intimate, physical and electrical contact
with the dendritic crystals of the plated palladium or alloy, thus
assuring reliable electrical contact adequate for testing purposes.
Power distribution is accomplished by the use of power plates which are
effectively from a large capacitor. The positive and negative plates of
the power distribution apparatus are spaced and insulated from each other.
The power conductors of the circuit substrate are effectively vias through
the substrate structure from the contact pads on one face to a second
contact pad on the opposite face of the circuit substrate. The second
contact pad then may make contact with the power plate immediately
therebelow and provide the required voltage. Ground connections are
provided by vias through the power distribution plate to the ground plate
positioned juxtaposed to the power plate and on the opposite side of the
power plate from the circuit substrate. The entire assembly may be clamped
or bolted to a motherboard not only to provide the required positioning of
the module relative to the motherboard but, also, the compressive forces
necessary to insure adequate electrical contact between the solder balls
of the memory chips and the contact pads of the circuit substrate.
Since only one chip typically is bonded to a single heat spreader, the
spacing between the heat spreader and the adjacent chip provides an air
passage which may be used to convectively cool the heat spreader, if
desired, as an option. With air flow over the heat sink and through the
interstices between the chips and the heat spreaders, if needed, the need
for cryo-cooling may be avoided.
By utilizing individual memory chips bonded and attached to heat spreaders
which are then positioned by the chip holder, manufacturing operations
required for memory cubes such as surface grinding of the assembled chips,
plating of contact pads on individual conductors exposed by the grinding,
disassembly and potential destruction of good memory chips during repair
and re-work of the assembled memory cubes are eliminated resulting in
significant advantages to the present invention.
The compressive force contact between the solder balls and the contact pads
on the circuit substrate permit the relatively easy removal and
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