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Probe for jesting an electrical circuit chip    
United States Patent5313157   
Link to this pagehttp://www.wikipatents.com/5313157.html
Inventor(s)Pasiecznik, Jr.; John (Malibu, CA)
AbstractA membrane probe (10, 12, 14, 16, 58, 144) for testing integrated circuits (56,138) while still on the wafer upon which they are manufactured includes a flexible visually clear and self planarizing membrane (26) having circuit traces (20) and ground shielding planes (14), terminating resistor (152) and active buffer chips (172) formed thereon. Probe contact pads (36,38) electroplated on areas of the traces, and connector pads (32) plated on the membrane facilitate rapid detachable connection to a test fixture (50). The probe has a configuration, dimension and structure like that of the wafer itself so that automated pick and place equipment (136,142) employed for handling the wafers (138) may also be used to handle the probes (144). An unique test fixture (50) is adapted to receive and detachably secure a selected probe to the fixture. A metal-on-elastomer annulus (88,104) is employed in the test fixture to make electrical contact between contact pads (32) plated on the back side of the membrane probe and a printed circuit board that is used to route signals to the testing equipment.
   














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Drawing from US Patent 5313157
Probe for jesting an electrical circuit chip - US Patent 5313157 Drawing
Probe for jesting an electrical circuit chip
Inventor     Pasiecznik, Jr.; John (Malibu, CA)
Owner/Assignee     Hughes Aircraft Company (Los Angeles, CA)
Patent assignment
All assignments
Publication Date     May 17, 1994
Application Number     07/875,511
PAIR File History     Application Data   Transaction History
Image File Wrapper   Patent Term   Fees
Litigation
Filing Date     April 29, 1992
US Classification     324/757
Int'l Classification     G01R 031/00
Examiner     Nguyen; Vinh
Assistant Examiner    
Attorney/Law Firm     Duraiswamy; V. D Low; W. K ., Denson- .
Address
Parent Case     This is a division of application Ser. No. 07/606,676 filed Oct. 31, 1990, now U.S. Pat. No. 5,148,103.
Priority Data    
USPTO Field of Search     324/158 F 324/158 P 324/72.5 439/482 333/246
Patent Tags     probe jesting electrical circuit chip
   
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 U.S. References
 
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ReferenceRelevancyCommentsReferenceRelevancyComments
5090118
Kwon
29/843
Feb,1992

[0 after 0 votes]
5034685
Leedy
324/754
Jul,1991

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5027063
Letourneau
324/754
Jun,1991

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5012187
Littlebury
324/754
Apr,1991

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4972143
Kamensky
324/754
Nov,1990

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4928061
Dampier
324/754
May,1990

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4922192
Gross
324/754
May,1990

[0 after 0 votes]
4849689
Gleason
324/754
Jul,1989

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4820976
Brown
324/760
Apr,1989

[0 after 0 votes]
4791363
Logan
324/754
Dec,1988

[0 after 0 votes]
4783625
Harry
324/754
Nov,1988

[0 after 0 votes]
4733172
Smolley
324/754
Mar,1988

[0 after 0 votes]
4721198
Yajima

Jan,1988

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4697143
Lockwood
324/754
Sep,1987

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4649339
Grangroth
324/537
Mar,1987

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4518914
Okubo
324/762
May,1985

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4161692
Tarzwell
324/754
Jul,1979

[0 after 0 votes]
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 Claims Submit all comments and votes
 


What is claimed is:

1. A probe for testing a circuit wafer having thereon an electrical circuit chip, said probe comprising:

a substrate having a dimension and configuration like that of said wafer, and an edge section means for enabling handling and orientation, and having first and second sides,

a flexible membrane fixed to said first side,

a plurality of electrically conductive traces formed on said membrane,

a plurality of contact pads formed on selected ones of said traces,

a plurality of membrane connector pads formed on said second side of said substrate, and

means for electrically connecting at least some of said contact pads with some of said connector pads.

2. The probe of claim 1 wherein at least said connector pads are photolithographically formed.

3. The probe of claim 1 wherein said means for electrically connecting at least some of said contact pads comprise a plurality of metallized vias extending through said substrate.

4. The probe of claim 1 including a second flexible membrane fixed to said first side of said substrate and carrying the first-recited membrane, and a plurality of ground strips formed on said second flexible membrane.

5. The probe of claim 4 wherein said traces and ground strips form AC transmission lines, and including at least one terminating resistor connected across one of said transmission lines at one of said contact pads.

6. The probe of claim 1 including a second flexible membrane fixed to said first side between said substrate and the first-mentioned membrane, a second plurality of electrically conductive traces on said second flexible membrane and electrically conductive means extending through at least one of said membranes for connecting traces of said second plurality of traces to at least some of said connector pads.

7. The probe of claim 6 including a resistor connecting at least one of said second plurality of electrically conductive traces to one of said membrane connector pads.

8. The probe of claim 1 including at least one buffer chip mounted in said substrate and connected to at least one of said traces.

9. The probe of claim 1 including a well formed in said substrate, and at least one active impedance controlling buffer chip mounted in said well and connected to at least one of said traces.

10. The probe of claim 1 further including a second flexible membrane fixed to said second side of said substrate, said plurality of connector pads being carried upon said second membrane.

11. A probe for testing an electrical circuit chip carried on a circuit wafer, said probe comprising:

a substrate having a dimension and configuration like said circuit wafer, and an edge section means for enabling handling and orientation,

a flexible membrane carried by said substrate,

a plurality of contact pads on said membrane,

a plurality of electrical conductors on said membrane and electrically connected to said contact pads, and

means defined by said probe for detachably connecting said probe by vacuum both mechanically and electrically to a test fixture.

12. The probe of claim 11 including a substrate having a first side supporting said membrane and having a second side, said means for detachably connecting comprising a plurality of membrane connector pads formed on said second side of said substrate, and means extending through said substrate for electrically connecting at least some of said contact pads with some of said connector pads.

13. The probe of claim 12 wherein said connector pads are positioned around the periphery of said second side and wherein said second side has a smooth flat annular surface configured and arranged to be forcibly attracted by a vacuum applied by a test fixture.

14. The probe of claim 11 wherein said means for detachably connecting comprises a plurality of connector pads formed on said membrane, and surface means for urging said membrane against said test fixture to electrically and mechanically connect the probe to such fixture.

15. The probe of claim 11 including a plurality of ground conductors on said membrane and spaced from the first mentioned conductors, and at least one terminating resistor connected between one of said first mentioned conductors and one of said ground conductors.

16. The probe of claim 11 including a substrate having a first side supporting said membrane and having a second side, said conductors and contact pads being positioned on one side of said membrane, and wherein said means for connecting comprises a plurality of connector pads formed on said second side of said substrate and connected to said conductors.

17. The probe of claim 16 including a plurality of vias extending through said substrate and electrically interconnecting said conductors and connector pads.

18. The probe of claim 16 wherein said second side of said substrate is provided with a surface adapted to be forcibly attracted by vacuum applied by a test fixture.

19. A probe for testing electrical circuit chip comprising:

a substrate having first and second sides,

a flexible membrane fixed to said first side, said membrane having inner and outer sides

a plurality of electrically conductive traces on said membrane outer side,

a plurality of contact pads formed on selected ones of said traces,

a plurality of ground strips on said membrane inner side, and

a terminating resistor on said membrane at one of said plurality of contact pads and electrically interconnecting said one contact pad and one of said plurality of ground strips.

20. A probe of claim 19 including a plurality of probe connector pads on said second side of said substrate, and means extending through said substrate for connecting said plurality of traces and said plurality of ground strips respectively to said connector pads.

21. A probe for testing electrical circuit chip carried on a circuit wafer, said probe comprising:

a substrate having a dimension and configuration like said circuit wafer and having first and second sides,

a flexible membrane fixed to said first side,

a plurality of electrically conductive traces formed on said membrane,

a plurality of contact pads formed on selected ones of said traces,

a well formed in said substrate,

at least one active buffer chip mounted in said well and electrically connected to at least one of said conductive traces, and

means for electrically connecting said buffer chip to an external test circuit.

22. A probe of claim 21 wherein said means for electrically connecting comprises a plurality of probe connector pads on said second side of said substrate, and means extending through said substrate for electrically connecting said probe connector pads to said buffer chip.
 Description Submit all comments and votes
 


This application is related to co-pending application Ser. No. 277,819, filed Nov. 30, 1988, invented by Albert Kamensky, James H. Cliborn and Louis E. Gates, Jr., for DIAPHRAGM TEST PROBE Attorney Docket No. PD-87445 and assigned to the assignee of the present application, now U.S. Pat. No. 4,972,143.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to testing of integrated circuits and more particularly concerns improved test fixtures and probes that readily lend themselves to automated testing and efficient probe manufacture and use.

2. Description of the Related Art

Integrated circuits or chips including conductive traces, electrical components, and active devices are fabricated in batches of large numbers of similar or identical circuits on a single wafer and then individually cut from the wafer for use. Because production techniques and processes are pushed to the limits of accuracy and repeatability, significant numbers are of circuits on a single wafer may be unacceptable or inoperable. Therefore it is desirable to test each circuit individually before it is separated from the other by severing the wafer into its many component circuits for its intended use.

Probe cards presently employed for testing of integrated circuits while still on the wafer employ a number of probe contact elements, commonly in the form of very small blades or needles that are mechanically and electrically fixed to a circuit board or the like and have leads that fan out to outer edges of the probe card for making connections between the probe card and testing circuitry. The contact blades or needles of the probe card are moved into contact with specific areas, namely the pads of the integrated circuit or chip under test, and may be electrically connected so as to apply selected input signals and to read output signals from the device under test. In this manner the chips are tested on the wafer, before being connected for intended use, by applying operating signals and monitoring and evaluating resultant outputs.

Probe cards presently employed are bulky and complex, being difficult to store and handle. Mechanical contact needles and blades require precise alignment and positioning. They also require precise planarization. That is, the contact surfaces of the probe must all lie in the same plane. An example of such a probe card employing a number of small, thin metal blades having needle like probe members fixed thereto is illustrated in U.S. Pat. No. 4,161,692 of Tarzwell for Probe Device For Integrated Circuit Wafers. In probe cards of this type the individual probe blades or needles must be mounted individually, frequently by use of micro-manipulators to properly locate the closely packed small probe elements, which then may be soldered or otherwise fixed in place. Final position adjustment in both X,Y, and Z, that is, in lateral position and elevation, is then accomplished for individual ones of the probe blades and needles by bending. For planarization, the probe card may be brought down upon a flat plate so as to ensure that all of the probe contacts will touch at the same time. These procedures are time consuming, tedious and expensive. Moreover, because the final positioning of contacts of prior probe cards is accomplished by bending of the metal blades or needles, the device is subject to errors caused by creep. That is, the parts, after bending, tend to "creep" or return to an original condition or position in which they existed prior to being stressed during the bending adjustment process. The creep occurs even when the probe card is on the shelf and not being used, so that, after a period of months or sometimes weeks on the shelf, the probe contacts may need to be readjusted More frequent adjustment and probe maintenance may be required when the probes are used.

In use of such probe cards the contact between the probe card blades or needles and the circuit chip is frequently made by a scrubbing action, which tends to deflect the slender probe elements as much as several mils on each touchdown. This displacement, which occurs repetitively upon each test, further tends to change the desired positioning of the elements.

The probe may have from fifty to several hundred contacts, each of which must be precisely and individually positioned with respect to all others so that upon contact with the circuit chip all probe contacts will contact all pads of the chip under test. All of this means that the probe cards presently used are exceedingly expensive, require much maintenance, and are subject to many errors.

Other probes employing blades and needles are illustrated in U.S. Pat. No. 4,783,625 to Emory J. Harry et al, and U.S. Pat. No. 4,791,363 to John K. Logan. U.S. Pat. Nos. to Gleason et al, 4,849,689 and Lockwood et al, 4,697,143 show cantilevered trapezoidal probes which may include detachable tip sections and circuit boards that mount probe conductors.

As integrated circuit speeds increase, so too do the difficulty and extent of the testing problems. Such problems are caused by cross talk between adjacent signal traces, signal loss and degradation due to capacitative loading of the circuit under test, and increased need for shielding and impedance matching of signal lines throughout the test fixture and test head. High frequency probe transmission lines must be properly terminated. Although high frequency hardware can be provided up to the test head itself, the physical connection between the test head and the integrated circuit pad, which relies upon exposed metallic blades or needles, provides poor high frequency performance and extremely fragile components. Thus the final part of the probe transmission line cannot be properly terminated.

It is often necessary to increase the density of probe contact pads and to provide test contact with chip pads that are located at the interior of the chip. This may require that leads to the probe contacts cross one another or that the blades or needles of the existing probe cards cross one another. Such a crossing of blades or needles is not physically possible with present configurations of test probes.

As size and spacing of integrated circuit chips decrease and density of chip contacts increases, it becomes ever more difficult to make mechanical blade or needle contacts as small and closely spaced as required for proper testing of modern integrated circuit chips. Moreover, the great bulk and complex configuration of prior art probe cards do not readily lend themselves to automated handling or simplified storage. Frequently the relatively costly test fixtures themselves must be changed whenever the probe card is changed for testing of a different chip configuration.

The test probe described in the above-identified co-pending patent application of Kamensky et al employs photolithographically formed probe contacts and leads to eliminate many of these problems but fails to provide for a number of improvements that are available with the methods and apparatus described herein. The disclosure of such co-pending application is incorporated by this reference as though fully set forth herein.

Accordingly, it is an object of the present invention to provide for testing of integrated circuit chips while avoiding or minimizing above-mentioned problems.

SUMMARY OF THE INVENTION

In carrying out principles of the present invention in accordance with a preferred embodiment of one feature thereof, a plurality of circuit chips of different configuration are tested by providing a plurality of test probes of which each is configured for testing an unique chip configuration. The probes are stored in a cassette. A chip to be tested is positioned adjacent a test fixture, and a pick and place machine is employed to selectively extract a chosen test probe from the cassette and move it to the fixture to which it is detachably connected, both mechanically and electrically, to allow the test probe to contact the chip to be tested.

According to another feature of the invention, a test probe is formed of a flexible membrane having a pattern of electrically conductive traces formed on the membrane, a plurality of contact pads on selected ones of the traces, and connector pads on the membrane connected to the traces to facilitate rapid detachable electric connection to a test fixture.

According to other features of the invention, the membrane probe may have a terminating resistor for terminating a high frequency transmission line or may have a buffer chip, to provide high impedance, low capacitance loading. Multiple layers of a probe membrane may be employed to attain complex geometry of probe contact pads and trace patterns.

BRIEF DESCRIPTION OF THE DRAWINGS

In the accompanying drawings:

FIG. 1 perspective view of a membrane probe embodying principles of the present invention;

FIG. 2 cross section of the probe of FIG. 1;

FIG. 3 is a sectional view of a test fixture and work table for integrated circuit chips of a wafer;

FIG. 3a an enlarged sectional detail of a portion of the of FIG. 3;

FIG. 4 is a pictorial view (with parts broken away) of a test fixture and work table for testing integrated circuit of a wafer, showing a modified elastomeric annulus;

FIG. 4a is an enlarged sectional detail showing aspects of the annulus of FIG. 4;

FIG. 5 is a simplified schematic illustration showing use of pick and place machines for handling test wafers and membrane probes;

FIG. 6 is an enlarged pictorial illustration, partly exploded, of a detail of a test probe having a multi-level membrane, showing a probe contact pad and a terminating resistor;

FIG. 7 is a sectional view of a modified membrane probe having an buffer chip; and

FIG. 8 illustrates a multiple level probe membrane.

DESCRIPTION OF THE INVENTION

FIGS. 1 and 2 illustrate a membrane probe embodying principles of the present invention. This probe is an improved version of the diaphragm test probe disclosed in the above-identified co-pending patent application of Kamensky, Cliborn, and Gates, Jr. The probe disclosed in the present application has a number of features in common with that of the earlier co-pending application, including a flexible diaphragm, conductive contact pads and an arrangement for applying pressure to one side of the flexible diaphragm to accomplish self planarizing contact of the probe pads against the pads of a die or chip under test. The membrane probe disclosed herein has a number of significant improvements over the probe of the co-pending application, among which are the specific probe configuration and arrangement that adapt the probe for use in fully automatic wafer testing processes using conventional pick and place loading and cassette storage of both membrane probes and test wafers. In the design to be described herein the probe is a low cost membrane probe that is readily attachable to and detachable from the test fixture so that the fixture itself does not have to be duplicated each time a new probe is built.

An exemplary membrane probe is illustrated in FIGS. 1 and 2 for purposes of explaining the present invention. The probe is formed of an electrically non-conductive rigid or semi-rigid and self supporting substrate 10 in the configuration of a generally flat, thin disc having a central aperture 12 and clad on both sides with thin layers of a transparent flexible dielectric such as polyimide layers 14,16. Outer layer 16 extends across central aperture 12 but inner layer 14 does not, being of an annular configuration with a central aperture coextensive with substrate aperture 12. A pattern of traces 20,22 is formed on one side (an outer or lower side) of the substrate, upon polyimide layer 16. The traces extend from trace end portions, disposed in a selected pattern at a central portion 26 of the membrane 16, within the boundaries of substrate aperture 12, to .fan out in generally radial directions to a plurality of metallized vias (apertures) 30 that extend through the substrate and polyimide layers on each side. The inner side of the probe, which bears the polyimide layer 14, carries a plurality of relatively short, radially extending connector pads 32, each of which may be connected to one of the traces 20,22 by means one of the appropriately located metallized vias 30. The inner end of each trace bears an axially projecting contact pad, such as pads 36,38, such contact pads being positioned in a configuration that will match the pads of a circuit die that is to be tested. Alternatively, connector pads 32 may be formed directly on the substrate 10, omitting layer 14. In use of the probe, with the outer layer 16 facing downwardly, the contact pads 36,38 are the lowest points of the probe, so that only these pads will contact a chip to be tested.

Substrate 12 is formed preferably of a thin rigid photoceram material having a flat edge section 40 (FIG. 1) formed on one side thereof to enable handling and orientation by well known pick and place equipment, as will be described below. The entire membrane probe is dimensioned, configured and arranged to be handled by known pick and place equipment which may be substantially identical to equipment arranged to handle the wafers to be tested.

In manufacture of the described membrane probe the photoceram substrate 12, in the form of a solid, substantially rigid and self-supporting disc, is provided with a number of preformed holes to be used as the vias 30. Preferably the photoceram disc may have the diameter of a standard wafer and may be either three inches or six inches in diameter, for example, having a thickness of about 30-40 mils. A layer of the membrane 14,16 is applied to each side of the photoceram substrate by employing standard spinning techniques in which a small amount of polyimide is placed on the photoceram surface and the disc spun to centrifugally distribute the polyimide evenly and radially outwardly. Several repetitions of this spinning process will build up the membrane thickness to provide a finished polyimide membrane of about 1 mil in thickness on each side of the photoceram substrate. The polyimide is highly transparent, as described in the above-identified co-pending application, to enable visual registration of the membrane probe contact pads 36,38 with appropriate pads on the wafer die being tested. Although the polyimide film may be applied in various ways, the spinning process is preferred because it yields a film that, although axially flexible in the central area 26, is radially taut so that the film is dimensionally stable in the plane of the film but may be flexed outwardly by gas pressure, as will be described below.

After application of the polyimide film to both sides, the traces and pads are formed on one side. The pads are then formed on the other side and the aperture 12 is formed in the photoceram and also in the inner polyimide layer 14. To perform these steps, after photolithographically applying resist in a suitable pattern to the outer polyimide layer 16, a metal such as a mixture of tungsten with a small amount of titanium, W(Ti), is sputtered over the entire surface including the resist and vias, and the resist (and portions of the sputtered metal) is then lifted to leave a pattern of thin, sputtered traces forming the pattern of traces 20 on the polyimide layer 16. The traces 20, which may be formed of copper, for example, are then electrolytically plated up on the pattern of sputtered on metal traces, at the same time metallizing the interior of the vias 30. Then the entire lower surface, except for those areas at the end of traces 20 that are to be covered by contact pads 36,38, is coated with a passivation layer (not shown), which may be of a polyimide, to effectively electrically insulate the conductive trace surfaces. Now, using photolithography, masking and applying resist, the contact pads 36,38 are plated up (to a height of 1 mil, for example) on the ends of traces 20. If deemed necessary or desirable the contact pads may be flash coated with a highly stable conductive material such as a nickel-gold flash coating.

Similarly, photolithography, employing suitable application of resist, development of the resist and removal of the undeveloped resist, is then employed to first sputter a thin metal coating on inner layer 14 in the desired pattern of connecting pads 32 which then may be copper plated to provide a plurality of connecting pads (about 1 mil high) that extend in closely spaced relation circumferentially around the periphery of the inner side of the membrane probe, as can be best seen in FIG. 1. Each of these pads is positioned at a metallized via 30 so that each pad is electrically connected via such via to an associated one of the traces 20. If deemed necessary or desirable when forming the connecting pads 32, additional ground traces or ground strips (not shown in FIGS. 1 and 2) may be formed on the surface of polyimide layer 14 or on an adjacent polyimide layer (not shown in FIGS. 1 and 2).

After forming the conductive traces on both sides of the membrane probe by suitable masking and application of resist, the aperture 12 is etched through the center of substrate 10 (and through the center of layer 14), resulting in the final probe configuration illustrated in FIGS. 1 and 2. The result is a thin, relatively rigid, self-supporting disc having a flat edge 40 for orientation by automatic handling equipment and a thin, flexible, taut, transparent central area 26 to the outer side of which are affixed the projecting probe contact pads 36,38 in a selected pattern that matches the pattern of pads on the die to be tested. The other side of the probe has an annular array of connecting pads 32, all lying in a single plane and a flat annular surface 39 (FIG. 1) between the connecting pads and aperture 12. Annular surface 39 is used for vacuum attachment of the probe, as will be described below.

The illustrated membrane probe may be used with many different types of testers. It is preferably used with application of a suitable pressure, such as a gas pressure, against the inner surface of the central portion 26 of the flexible transparent membrane. However, the probe illustrated is specifically designed for use in a test fixture to which the probe may be readily mechanically and electrically connected and disconnected, either manually or by automatic machines. In the illustrated probe configuration, both electrical and mechanical connection of the probe to a test fixture are accomplished in coordination with the configuration of the inner surface of the probe. This inner surface of the probe includes the co-planar connecting pads 32 that form a substantially circular array around the periphery of the inner side of the probe, and the flat annular inwardly facing surface 39 of polyimide layer 14 that extends radially between the connecting pads 32 and the boundary of the aperture 12 that extends through the substrate. This flat annular surface is configured and arranged to enable vacuum attachment of the membrane to a vacuum chamber 70 of the fixture 50, shown in FIGS. 3 and 3a, as will be described below.

Illustrated in FIG. 3 is a test fixture, generally indicated at 50, fixedly mounted to and above a support 52 that carries a movable work table 54 on which is mounted a test wafer 56 that is to be tested by a membrane probe 58. The latter may be of the configuration illustrated in FIGS. 1 and 2. The work table is movable in X,Y and Z, that is, in two perpendicular directions horizontally, and in one direction vertically by suitable manually controllable means (not shown).

As can be seen in FIG. 3, a rigid mounting plate 57 is fixedly carried on support 52 and has a central aperture defined by a radially inwardly directed lip 59 which supports circumferential radially outwardly extending flanges 60 of a gas chamber housing 62. Housing 62 is circular in horizontal section and includes an inner right circular cylindrical gas chamber 64 that is closed and sealed at its upper end by a clear, transparent glass window 68 held in place by a retainer ring 71. Chamber housing 62 has a planar annular lower surface defining a peripheral seating area 66 that is congruent with the annular portion 39 of substrate 10 of probe 58, between the connector pads 32 and the boundary of aperture 12 of the wafer probe.

An annular recess 70, formed in the bottom surface 66 of the housing, is connected by a conduit 74 to a source of vacuum (not shown) so as to firmly affix the probe 58 to the bottom surface of housing 62 in a gas tight sealing relation when vacuum is applied through the conduit. Thus the membrane probe is securely mechanically attached in a readily attachable and detachable fashion to the test fixture.

An angulated gas conduit 76, formed at and extending through one side of the housing 62, is adapted to be connected by means of a fitting 78 to a source of pressurized gas, such as air, which will apply a pressure within sealed chamber 64 in the order of two to four pounds per square inch, thereby causing flexible membrane layer 16 to flex outwardly.

For readily detachable and attachable electrical connection of the wafer probe to the test fixture, a printed circuit board 80 is fixedly secured to the fixture mounting plate 57 as by mechanical fasteners, clamps or adhesive (not shown). Printed circuit board 80 has coaxial electrical cables 82,84 connecting circuit elements on the board 80 to test circuitry (not shown). Leads on the printed circuit board 80 are connected to an elastomeric electrical connector 88 in the form of a wrap-around metal-on-elastomer or wrap-around MOE. The wrap-around MOE comprises an annulus 90 of a suitable elastomer, such as a silicon sponge, that has a plurality of circumferentially spaced, closely positioned, narrow metal contacting strips 92 (FIG. 3a ) wrapped entirely around the elastomer. The circumferential spacing of the contact strips 92 on the MOE is the same as that of the connector pads 32 on the membrane probe. The two sets of connecting strips and pads, the connector strips 92 of the MOE and the connector pads 32 of the probe, are positioned to mate with one another when the membrane probe is mechanically secured by the vacuum of annular recess 70 to the test fixture housing 60.

An alternate configuration of the elastomeric probe connector or wrap-around MOE 88 is shown in FIG. 4. In FIG. 4 the probe tester mounting plate 57, test fixture housing 60, glass window 68, and retainer 71 are the same as those illustrated in FIG. 3. FIG. 4 shows these same parts in a pictorial view with parts broken away. However, in the arrangement of FIG. 4, an elastomeric probe connector in the form of a single sided metal on elastomer or single sided MOE 104 is used instead of the wrap-around MOE of FIGS. 3 and 3a. The single sided MOE is embedded in a multi-level printed circuit board 102 (see the enlarged detail of FIG. 4a). The multi-level printed circuit board is formed of an upper layer of copper plate 106, an intermediate layer of Teflon 108, and a lowermost printed circuit board of polyimide or glass epoxy 110. A pattern of ground traces or ground strips 112 is sandwiched between the copper and Teflon and a pattern of signal traces 114 is sandwiched between the Teflon and polyimide or glass epoxy. The intermediate Teflon layer 108 is radially set back to provide a recess, defined between the outer layers 106 and 110, that receives the single sided MOE 104. MOE 104 includes elongated electrically conductive pads 116 on its lower surface which contact the connector pads 32 of the membrane probe and also the signal leads 114 of the multilevel printed circuit board. The MOE also includes elongated contact pads 118 on its upper surface which contact the ground traces or strips 112 of the printed circuit board, thereby electrically connecting the membrane probe to the test fixture. Suitable electrical connections in the form of vias (not shown) extending through the MOE connect the elongated pads 118 on its upper surface to associated connecting pads 32 on the membrane probe. As in the arrangement of FIG. 3, the signal leads 114 and ground leads 112 of the circuit board are coupled to testing circuitry by means of coaxial connecting cables 120,122.

Also shown in the pictorial view of FIG. 4 are the test probe 58 and the work table 54. The table temporarily but fixedly supports the wafer 56 which is to be tested. The small rectangles indicated at 130 on the wafer 56 represent die pads of the chips that are to be tested. The die pads define a pattern that is precisely matched by the contact pads of the wafer probe 58. It will be readily understood that the contact pads may be made in a pattern and number sufficient to test a single group of die pads so that testing of all groups of die pads on a wafer will be achieved by testin