Chroma processor including a look-up table or memory

Claims

We claim:

1. A digital chroma processor for providing first output chrominance signals and second output chrominance signals in response to first input chrominance signals and second input chrominance signals, the chroma processor comprising:

means for selecting color modification parameters;

chrominance look-up table means for storing data representative of the first output chrominance signals and the second output chrominance signals, wherein the chrominance look-up table means is configured to address the data and provide the first output chrominance signals and the second output chrominance signals in response to application of the first input chrominance signals and the second input chrominance signals to the look-up table means wherein the first output chrominance signals and the second output chrominance signals are predefined; and

processing means for configuring the data representative of the first output chrominance signals and the second output chrominance signals in the look-up table means in accordance with the color modification parameters.

2. The chroma processor of claim 1 wherein the means for selecting color modification parameters comprises a software user interface.

3. The chroma processor of claim 2 wherein the software user interface includes a flare suppression control for selecting at least one color modification parameter.

4. The chroma processor of claim 2 wherein said software user interface includes a vector scope for selecting the color modification parameters.

5. The chroma processor of claim 4 wherein the user interface is configured for selecting wedge-shaped or circular regions from the vector scope.

6. The chroma processor of claim 1 further comprising:

key look-up table means for holding key signals for the first input chrominance signals and the second input chrominance signals, the key look-up table means providing the key signals when addressed by the first input chrominance signals and the second input chrominance signals;

wherein the processing means generates the key signals in accordance with the selected color modification parameters for the first input chrominance signals and the second input chrominance signals, the processing means loading the key look-up table means with the key signals.

7. The chroma processor of claim 1, wherein the first input chrominance signals and the second input chrominance signals are U and V chrominance signals.

8. The chroma processor of claim 1, wherein the chrominance look-up table means includes a first address input which receives the first input chrominance signals and the second input chrominance signals, a data input coupled to the processing means, and a second address input coupled to the processing means.

9. The chroma processor of claim 8, wherein the means for selecting color modification parameters includes a flare suppression control and the processing means generates the first output chrominance signals and the second output chrominance signals in accordance with flare suppression parameters provided by the flare suppression control.

10. A digital chroma processor for generating first key signals in response to first chrominance signals, and second chrominance signals, the chroma processor comprising:

user interface means for selecting color modification parameters;

memory means for holding the first key signals for the first and second chrominance signals, the memory means providing the first key signals when addressed by the first and second chrominance signals; and

processing means for generating the first key signals in accordance with the selected color modification parameters, the processing means loading the memory means with the first key signals.

11. The digital chroma processor of claim 10 wherein the digital chroma processor further receives luminance signals, and wherein the memory means is further addressed by the luminance signals.

12. The chroma processor of claim 10 wherein the digital chroma processor further receives luminance signals, and the digital chroma processor further comprises:

addressing means for providing address signals in response to the first key signals and the luminance signals; and

second memory means for storing second key signals, the second memory means providing the second key signals when addressed by the address signals, the processing means generating the second key signals in accordance with the selected color modification parameters and loading the second memory means with the second key signals.

13. The digital chroma processor of claim 12 wherein the addressing means generates the address signals b concatenating a plurality of most significant bits from the first key signals and a plurality of most significant bits from the luminance signals.

14. The digital chroma processor of claim 12 wherein the addressing means is comprised of conductors coupled to the memory means and the second memory means.

15. The chroma processor of claim 10 wherein the user interface means is a software user interface.

16. The chroma processor of claim 10 wherein the user interface means includes a softness control for selecting at least one color modification parameter.

17. The chroma processor of claim 10, further comprising a second memory means for storing new key signals, the second memory means providing the new key signals when addressed by address signals;

a matte signal input for receiving second key signals; and

a multiplexer for receiving the second key signals from said matte signal input and the first key signals from the memory means, the multiplexer selecting the second key signals or the first key signals to provide the address signals, the processing means generating the new key signals for a plurality of values of the first key signals and second key signals and loading the second memory means with the new key signals.

18. A digital chroma processor for providing new luminance signals in response to first chrominance signals, second chrominance signals, and luminance signals, the chroma processor comprising:

means for generating color modification parameters;

first look-up table means for storing the new luminance signals for a plurality of the first chrominance signals, the second chrominance signals, and the luminance signals, the first look-up table means providing the new luminance signals when addressed by the first and second chrominance signals and the luminance signals; and

processing means for generating the new luminance signals in accordance with the color modification parameters and loading the first look-up table means with the new luminance signals.

19. The chroma processor of claim 18 wherein the means for generating color modification parameters includes a luminance control.

20. The chroma processor of claim 19, wherein the means for generating color modification parameters includes a softness control for providing one of the color modification parameters.

21. The chroma processor of claim 19, further comprising:

a luminance input for receiving the luminance signals; and

a multiplexer having a first input coupled to the luminance input and a second input coupled to the first look-up table means, the multiplexer conveying the luminance signals or the new luminance signals in response to a control signal.

22. A digital chroma processor, comprising:

a first input for receiving first chrominance values;

a second input for receiving second chrominance values;

a user interface;

a processor coupled to the user interface, wherein the processor produces a new first chrominance value and a new second chrominance value for each first and second chrominance value in a set of first and second chrominance values in response to commands from the user interface;

a memory having data outputs and first address inputs and data inputs, the first address inputs and data inputs coupled to the processor, the memory storing the new first and new second chrominance values on the data inputs for each first and second chrominance value in the set of first and second chrominance values at memory locations addressed by corresponding ones of the first and second chrominance values of the set of the first and second chrominance values, the memory having second address inputs coupled to the first input and the second input for receiving the first and second chrominance values, the memory providing the new first and second chrominance values at the data outputs in response to the first and second chrominance values on the second address inputs.

23. The chroma processor of claim 22 further comprising:

a key memory having key data outputs and first key address inputs, second key address inputs and key data inputs, the first key address inputs and key data inputs being coupled to the processor, the key memory storing key values on the key data inputs at locations addressed by a second set of the first and second chrominance values, the key memory having the second key address inputs coupled to the first input and the second input, the key memory providing the key values on the key data outputs in response to the first and second chrominance values on the second key address inputs, the processor including an algorithm for producing the key values for each first and second chrominance value in the second set.

24. The chroma processor of claim 23 further comprising:

a third input for receiving an original key signal; and

a key multiplexer having a first multiplexer input coupled to the key data outputs and a second multiplexer input coupled to the third input, the key multiplexer having a control input for selecting the key values or the original key signal.

25. The chroma processor of claim 23 wherein the memory is a dual port SRAM.

26. A digital chroma processor, comprising:

a first input for receiving first chrominance values;

a second input for receiving second chrominance values;

a user interface;

a processor coupled to the user interface, wherein the processor produces key values for each first and second chrominance value in a set of first and second chrominance values in response to commands from the user interface;

a memory having data outputs and first address inputs and data inputs, the first address inputs and the data inputs being coupled to the processor, the memory storing the key values on the data inputs for each first and second chrominance value in the set of first and second chrominance values at memory locations addressed by corresponding ones of the first and second chrominance values of the set of the first and second chrominance values, the memory having second address inputs coupled to the first and second inputs, the memory providing the key values at the data outputs in response to the first and second chrominance values on the second address inputs.

27. The digital chroma processor of claim 26 further comprising:

a third input for receiving luminance values;

a key memory having key data outputs and first key address inputs, and key data inputs, the key data inputs and first key address inputs being coupled to the processor, the key memory storing second key values on the key data inputs at memory locations addressed by a second set of the key values and the luminance values, the key memory having second key address inputs coupled to the data outputs of the memory and the third input, the key memory providing the second key values on the key data outputs in response to the key values and the luminance values on the second key address inputs;

the processor including an algorithm for producing the second key value for each key value and luminance value in the second set.

28. The digital chroma processor of claim 26 further comprising:

a third input for receiving an original key signal; and

a key multiplexer having a first input coupled to the key data outputs and a second input coupled to the third input, the key multiplexer having a control input for selecting the key values or the original key signal.

29. A digital chroma processor for providing first output chrominance signals and second output chrominance signals in response to first input chrominance signals and second input chrominance signals, the chroma processor comprising:

a user interface;

a processor;

a memory, the memory storing the first output chrominance signals and the second output chrominance signals, the memory providing the first output chrominance signals and the second output chrominance signals in response to the first input chrominance signals and the second input chrominance signals; and

wherein the processor is coupled to the user interface, the processor producing the first output chrominance signals and the second output chrominance signals for storage in the memory in response to commands from the user interface.

30. A digital chroma processor for generating key signals in response to first input chrominance signals and second input chrominance signals, the chroma processor comprising:

a user interface;

a processor;

a memory, the memory storing the key signals, the memory providing the key signals in response to the first input chrominance signals and the second input chrominance signals; and

wherein the processor is coupled to the user interface, the processor producing the key signals for storage in the memory in response to commands from the user interface.

31. A digital chroma processor for generating key signals in response to input luminance signals, the chroma processor comprising:

a user interface;

a processor;

a memory, the memory storing the key signals, the memory providing the key signals in response to the input luminance signals; and

wherein the processor is coupled to the user interface, the processor producing the key signals for storage in the memory in response to commands from the user interface.

FIELD OF THE INVENTION

This invention relates to video systems, and in particular to digital chroma processors capable of performing keying functions and color correction functions.

BACKGROUND OF THE INVENTION

Video keying may be performed with high speed video switches ("keyers") which select between two picture sources (video signals) during one frame period. By selectively switching between video signals, a composite video image may be produced. Generally, a keyer includes a switch and circuitry for generating a control (key) signal for the switch. The keyer selects between video signals based upon the status of the key signal.

Developments in the design of keyers have allowed relatively sophisticated combinations of two video signals. For instance, it is known in the art to utilize a key signal which represents a ratio of the first signal to the second signal. This type of key signal can be a function of various criteria. This signal allows the transition between the two video signals to be softened. A softened transition provides a more realistic composite image and reduces problems such as aliasing.

Video signals are generally comprised of two color difference signals and a luma signal. These signals are interconvertible with RGB representations. Various other types of video signals may also be used to provide a picture. In video signals, the symbol Y represents the luminance value and the symbols U and V represent two chrominance values. Generally, the U and V components represent the axes of a two dimensional space called the color plane. The practical range of the Y, U and V signals is preferably from -128 to +128 Which represents -3.5 volts to +3.5 volts in the analog domain with 8 bits per sample per component. The available values are 0-255. As per CCIR 601-2, "Encoding Parameters of Digital Television for Studios" parameter #8, the luminance signal will have 220 quantization levels with the black level corresponding to level 16 and peak white corresponding to level 235. Each color difference signal will have 225 quantization levels in the center part of the quantization scale with zero signal corresponding to level 128. Under this specification (CCIR 601-2), the Y channel analog signal will be 0V at 16 and +700 mV (milli-volts) at 235. Each color difference signal will be 0V at 128 and a negative -350 mV at 16 and a positive +350 mV at 240.

In order to provide a key signal that represents ratios of the first signal to the second signal (a signal that is more than bi-level (ON/OFF)), the combination of the two video signals must be by means of a multiplicative computation rather than a simple switching operation. This type of key signal is sometimes called a matte signal.

A circuit for providing a key signal or matte signal is discussed in "The Digital Chroma-Key" by V. G. Devreux (BBC Research Department, U.K.). In this reference, the chroma processor derives a key signal from the U and V signals. The circuit utilizes analog components for providing a multiplicative computation which generates the key signal.

"Digital Production Switchers" by Jacques Vallee (Thompson Video Equipment) discloses a digital chroma processor. The digital chroma processor includes a chroma key generator which utilizes digital multipliers and adders to develop a key signal. Similarly, U.S. Pat. No. 4,240,104 issued to Taylor et al. on Dec. 16, 1980 discloses a chroma key generator which is coupled to the U and V inputs. The generator receives the U and V signals from the first video signals and digitally performs various arithmetic manipulations to create a key signal. These generators are disadvantageous because the arithmetic computations by digital components are often inherently slow and because the processors can only be used with a single region of the color spectrum without adding additional hardware components.

In addition to keying, chroma processors also may perform a color correction operation. This operation allows a user to select certain colors in a video scene and then substitute new colors for the selected colors. In this application, U and V signals representative of the selected colors are chosen and the chroma processor replaces the U and V signals with U and V signals representative of the substitute colors. Also, the chroma processor may allow the user to select certain Y, U and V signals and replace the selected signals with different Y, U and V signals.

In U.S. Pat. No. 4,096,523, the color correction operation is performed by arithmetic processors which generate different Y, U and V values. Other prior art systems such as U.S. Pat. No. 4,727,412 utilize analog devices for providing color correction.

Analog prior art chroma processors are expensive and have limited accuracy and flexibility. Analog equipment is prone to drift and recalibration. Conventional digital prior art systems cannot process key signals and color correction data for different color regions without additional hardware. Accordingly, to have a competitive and acceptable system it is important to produce a system which is flexible.

SUMMARY OF THE INVENTION

The present invention relates to a digital chroma processor for receiving first and second input chrominance signals. The chroma processor includes a means for selecting color modification parameters, a chrominance look-up table means, and a processing means. The chrominance look-up table means stores data representative of a plurality of first output chrominance signals and second chrominance signals where the look-up table means is configured to address data and output predefined output chrominance signals in response to application of the input first and second chrominance signals. The processing means configures the data representative of a plurality of the output chrominance signals in the look-up table in accordance with a set of color modification parameters and the input chrominance signals.

The present invention relates to a digital chroma processor for generating first key signals in response to first chrominance signals and second chrominance signals. The chroma processor includes the user interface means for selecting color modification parameters, a memory means, and a processing means. The processing means generates the first key signals in accordance with the selected color modification parameters. The processing means also loads the memory means with the first key signals. The memory means holds the first key signals for the plurality of the first and second chrominance signals, and provides the first key signals when addressed by the first and second chrominance signals.

The present invention also relates to a digital chroma processor for providing new luminance signals in response to first chrominance signals, second chrominance signals and luminance signals. The chroma processor includes means for generating color modification parameters, a first look-up table means, and a processing means. The first look-up table means stores the new luminance signals for a plurality of the first chrominance signals, second chrominance signals, and the luminance signals. The first look-up table means also provides the new luminance signals when addressed by the first and second chrominance signals and the luminance signals. The processing means generates the new luminance signals in accordance with the selected color correction parameters and loads the look-up table means with the new luminance signals.

The present invention also relates to a digital chroma processor including a first input for receiving first chrominance values, a second input for receiving second chrominance values, user interface, a processor and a memory. The processor is coupled to the user interface. The processor produces a new first chrominance value and a new second chrominance value for each first and second chrominance value in a set of first and second chrominance values in response to commands from the user interface. The memory has data outputs and address inputs and data inputs coupled to the processor. The memory stores the new first and new second chrominance values for each first and second chrominance value in the set of first and second chrominance values on the data input at memory locations addressed by corresponding ones of the first and second chrominance values of the set of the first and second chrominance values. The memory has second address inputs coupled to the first and second inputs for receiving the first and second chrominance values. The memory provides the new first and second chrominance values at the data output in response to the first and second chrominance values on the second address inputs.

The invention also relates to a digital chroma processor including a first input for receiving first chrominance values, a second input for receiving second chrominance values, a user interface, a processor and a memory. The processor is coupled to the user interface. The processor produces key values for each first and second chrominance value in a set of first and second chrominance values in response to commands from the user interface. The memory has data outputs and address inputs and data inputs coupled to the processor. The memory stores the key values for each first and second chrominance value in the set of first and second chrominance value on the data inputs at memory locations addressed by corresponding ones of the first and second chrominance values of the set of the first and second chrominance values. The memory has second addressed inputs coupled to the first and second inputs. The memory provides the key values at the data outputs in response to the first and second chrominance values on the second address inputs.

DESCRIPTION OF THE DRAWINGS

The features of the present invention which are believed to be novel are set forth with particularity in the appended claims. The invention, together with further objects and advantages thereof, may best be understood by making reference to the following description taken in conjunction with the accompanying drawings in the several Figures, wherein like designations denote like elements, and wherein:

FIG. 1 is a block diagram of a video system in accordance with a preferred exemplary embodiment of the present invention;

FIG. 2 is a block diagram of the system computer including a chroma processor configured in accordance with the preferred exemplary embodiment of the present invention;

FIG. 3 is a block diagram of a portion of the chroma processor in accordance with the preferred exemplary embodiment of the present invention;

FIG. 4 is a block diagram which illustrates the manner in which the look-up tables are loaded in accordance with a preferred embodiment of the present invention;

FIG. 5 is a first schematic drawing of a software user interface including a vector scope in accordance with features of the present invention; and

FIG. 6 is a second schematic drawing of another software user interface including a vector scope in accordance with other features of the present invention.

DETAILED DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a video system 20 in accordance with a preferred exemplary embodiment of the present invention. The video system 20 includes a live video source 21, a video storage unit 22, and a video processing system 25. The live video source 21, which may be a camera, is coupled to the system 25 and video storage unit 22 by a foreground bus 26 and a background bus 27. The video storage unit may be a hard disk, tape recorder, or other storage device.

The video processing system 25 includes a system computer 28, a function monitor or screen 160, a processor a computer 150, a user interface 170 and an image display 38. The user interface 170 includes a keyboard 35 and a tablet 36. The system computer 28 is coupled to the foreground bus 26 and the background bus 27. The system computer 28 is coupled to the image display 38. The system computer 28 is also coupled to the computer 150. The computer 150 is coupled to the screen 160, the keyboard 35, and the tablet 36. The computer 150 is preferably a 486 based AT computer. The system computer 28 preferably is an Intel.RTM. i860 processor which is part of the DP/MAX system manufactured by ColorGraphics of Madison, Wis.

In operation, the video system 20, receives a foreground image from the video storage unit 22, or the live video source 21 on the bus 26 and a background image from the live video source 21, or the storage unit 22 on the bus 27. The system computer 28 manipulates these signals in accordance with color modification parameters provided from the computer 150. The computer 150 utilizes the screen 160, the keyboard 35 and the tablet 36 in order to enter color modification parameters. The system computer 28 provides a composite image in accordance with the color modification parameters to the image display 38. With the exception of portions of the system computer 28, the video system 25 is preferably comprised of the DP/MAX system.

With reference to FIG. 2, a block diagram of the system computer 28 includes a foreground chroma processor 50 and a mixer 40. The foreground chroma processor 50 is coupled to the mixer 40 by a luminance (Y) data bus 92, a first chrominance (U) data bus 97, and a second chrominance (V) data bus 98. A foreground matte data bus 93 couples the processor 50 to a matte signal adjustment circuit 44 which receives background matte signals from a da