 |
Description  |
|
|
CROSS-REFERENCE TO RELATED PATENT APPLICATIONS
The present application is related to U.S. patent application Ser. No.
752,419, filed on Aug. 30, 1991, by Furtek and Camarota for PROGRAMMABLE
LOGIC CELL AND ARRAY, which is a continuation-in-part of U.S. patent
application Ser. No. 07/608,415, filed on Nov. 2, 1990.
Both of the above-cited related applications are hereby incorporated by
reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to user programmable integrated
circuit devices and, in particular, to a mechanism that allows three-state
busses to be routed from any core cell in a configurable logic array to
any other core cell in the array.
2. Discussion of the Prior Art
A configurable logic array (CLA) is a matrix of interconnected,
programmable logic cells. The individual logic function and the active
inputs and outputs of each logic cell are determined by parameter
flip-flops and logic gates within the cell, rather than by physically
customizing the array during manufacture. Thus, the individual cell
functions and the interconnections between cells are dynamically
programmable to provide a wide variety of functions. The greater the
number of cells in the array, the greater the functional flexibility of
the CLA device.
The configurable logic array concept was first introduced by Sven E.
Wahlstrom in 1967. Wahlstrom, Electronics, Dec. 11, 1967, pp. 90-95.
Since then, Xilinx Inc., Actel Inc., Pilkington Micro-electronics Ltd. and
Concurrent Logic, Inc., among others, have proposed implementations of CLA
devices.
The basic Xilinx CLA architecture is disclosed in U.S. Pat. No.
4,870,302which issued to Ross H. Freeman on Feb. 19, 1988.
The CLA device described by the Xilinx '302 patent and shown in FIG. 1
includes an array of configurable logic elements that are variably
interconnected in response to control signals to perform selected overall
logic functions. Each configurable element in the array is capable of
performing a number of logic functions depending upon the control
information provided to that element. The array can have its function
varied at any time by changing its control information.
FIG. 2 shows a CLA interconnect structure currently utilized in the Xilinx
array. In addition to the single-length interconnect lines between logic
elements, as shown in FIG. 2, the Xilinx array utilizes lines that connect
switch matrices, e.g., two vertical and two horizontal double-length lines
per logic-element column. The Xilinx array also utilizes "global"
interconnect lines, e.g., six vertical global lines and six horizontal
global lines per logic-element column, for clocks, resets and other global
signals. Two of the horizontal global lines may be placed in a high
impedance.
FIG. 3 shows a logic-element currently utilized in the Xilinx array. The
Xilinx logic element has three function generators, two flip-flops, and
several multiplexers. The first two function generators can perform a
Boolean function of four inputs. The function generators are implemented
as memory look-up tables. The outputs of these two function generators are
provided to the multiplexers and to a three-input function generator which
can perform a Boolean function of G', F', and an external input. The
output of the third function generator is also provided to the
multiplexers. The multiplexers select whether the signals are provided to
the output of the logic element or to the input of the flip-flops. The
flip-flops have common clock, enable, and set or reset inputs. The
configuration bits that determine the function of the logic element also
determine how the C1 through C4 inputs are mapped into the four inputs H1,
DIN, S/R, and EC.
The basic Pilkington CLA architecture is disclosed in U.S. Pat. No.
4,935,734, which issued to Kenneth Austin on Sep. 10, 1986.
An implementation of the CLA architecture disclosed in the Pilkington '734
patent is shown in FIG. 4. Each logic element in the Pilkington array
accepts inputs from four other logic elements in the illustrated pattern.
Each logic element output drives multiple other elements as illustrated.
In the array disclosed in the '734 patent, there is no additional wiring.
However, the Plessey Company, under license from Pilkington, has marketed
a product wherein bus wiring is added as shown in FIG. 4; i.e. in every
third column, a bus provides inputs to every right-direction logic element
in that column, and every third row has a bus providing inputs to every
left-direction logic element in that row.
FIG. 5 shows a logic cell currently utilized in the FIG. 4 array. As shown
in FIG. 5, each of the two inputs to a NAND gate are provided by a user
configured multiplexer the inputs of which are provided by other logic
elements or inputs. Plessey has also added circuitry to the logic element
to permit it to be a latch or a 2-input NAND gate.
The basic Actel CLA architecture is disclosed in U.S. Pat. No. 4,873,459,
issued to El Gamal et al on Oct. 10, 1989.
The Actel architecture relies on one-time programmable anti-fuses for
configurability and, thus, is not re-programmable.
The Concurrent Logic, Inc. (CLI) CLA architecture, which is most relevant
to the present invention, is discussed below in conjunction with FIGS.
6-17. Features of the CLI CLA architecture are disclosed in the following
U.S. patents issued to Frederick C. Furtek: U.S. Pat. No. 4,700,187,
issued Oct. 13, 1987; U.S. Pat. No. 4,918,440, issued Apr. 17, 1990; and
U.S. Pat. No. 5,019,736, issued May 28, 1991.
As discussed in above-cited related application Ser. No. 07/608,415, a CLA
may be viewed as an array of programmable logic on which a flexible
bussing network is superimposed. As shown in FIG. 6, the heart of the CLI
CLA 10 is a two-dimensional array of logic cells 12 each of which receives
inputs from and provides outputs to its four adjacent neighbors. The core
logic cell 12, which is shown in detail in FIG. 7, can be programmed to
provide all the wiring and logic functions needed to create any digital
circuit.
Each logic cell 12 in the array, other than those on the periphery,
receives eight inputs from and provides eight outputs to its North (N),
East (E), South (S), and West (W) neighbors. These sixteen inputs and
outputs are divided into two types, "A" and "B", with an A input, an A
output, a B input and a B output for each neighboring cell 12. Between
cells 12, an A output is always connected to an A input and a B output is
always connected to a B input.
As further shown in FIG. 7, within a cell 12, the four A inputs enter a
user-configurable multiplexer 14, while the four B inputs enter a second
user-configurable multiplexer 16. The two multiplexer outputs feed the
logic components of the cell 12. In logic cell 12, these components
include a NAND gate 18, a register 20, an XOR gate 22, and two additional
user-configurable multiplexers 24 and 26.
The two four-input multiplexers 24 and 26 are controlled in tandem (unlike
the input multiplexers), giving rise to four possible logic
configurations, shown in FIGS. 8A-8D.
In the FIG. 8A configuration, corresponding to the "0" inputs of the
multiplexers 24 and 26, the A outputs are connected to a single A input
and the B outputs are connected to a single B input.
In the FIG. 8B configuration, corresponding to the "1" inputs of the
multiplexers 24 and 26, the A outputs are connected to a single B input
and the B outputs are connected to a single A input.
In the FIG. 8C configuration, corresponding to the "2" inputs of the
multiplexers 24 and 26, the A outputs provide the NAND and the B outputs
the XOR of a single A input and a single B input. This is the equivalent
of a half adder circuit.
In the FIG. 8D configuration, corresponding to the "3" inputs of the
multiplexers 24 and 26, the Q output of edge-triggered D flip-flop 20 is
connected to the A outputs, the D input of the flip-flop 20 is connected
to a single A input, the enable (EN) input of the flip-flop 20 is
connected to a single B input and the B outputs provide the logical
constant "1". A global clock input and register reset are provided for
this configuration, but are not illustrated in FIG. 8D. This configuration
is equivalent to a one bit register.
The cell 12 thus provides the most fundamental routing and logic functions:
extensive routing capabilities, NAND and XOR (half adder), a one-bit
register, the logical constant "1", and fan-out capabilities.
These functions permit the basic CLA array 10 to implement arbitrary
digital circuits. A register and half adder (NAND and XOR) included in
each cell 12, together with a high cell density, make the array 10 well
adapted for both register-intensive and combinatorial applications. In
addition, signals passing through a cell 12 are always regenerated,
ensuring regular and predictable timing.
Although the basic logic array 10 is completely regular, routing wires
through individual cells 12 can cause increased delays over long
distances. To address this issue, the neighboring interconnect provided by
the array 10 is augmented with three types of programmable busses: local,
turning, and express.
Local busses provide connections between the array of cells and the bussing
network. They also provide the wired-AND function.
Turning busses provide for 90.degree. turns within the bussing network,
enabling T-intersections and corners. Turning busses provide faster
connections than do local busses, since they do not have the delays
associated with using a cell as a wire.
Express busses are designed purely for speed. They are the fastest way to
cover straight-line distances.
There is one bus of each type described above for each row and each column
of logic cells 12 in the array 10. Connective units, called repeaters, are
spaced every eight cells 12 and divide each bus into segments spanning
eight cells 12. Repeaters are aligned into rows and columns, thereby
partitioning the basic array 10 into 8.times.8 blocks of cells 12 called
"superblocks". FIG. 9 illustrates a simplified view of a bussing network
containing four superblocks. Cell-to-cell connections are not shown.
As shown in FIG. 10, each local bus segment 13 is connected to eight
consecutive cells 12. As shown in FIG. 11, each turning bus segment 15 is
connected to eight orthogonal turning busses through programmable turn
points. As shown in FIG. 12, each express bus segment 17 is connected only
to the repeaters at either end of the 8.times.8 superblock. FIG. 13 shows
the three types of busses combined to form the bussing network of the
array 10.
In order for the bussing network to communicate with the array 10, each
core logic cell 12 is augmented as shown in FIG. 14 to permit the reading
and writing of local busses L. The cell 12 reads a horizontal local bus
through the "L.sub.x " input of the B input multiplexer 16 and reads a
vertical local bus through the "L.sub.y " input of the B input multiplexer
16. The cell 12 writes to a local bus through the driver 28 connected to
the A output.
While the cell 12 may read either a horizontal or a vertical bus under
program control, the cell 12 may write to only one bus of fixed
orientation. Whether a cell 12 writes to a horizontal or vertical bus is
determined by its location with the array 10. Referring back to FIG. 10,
the cell 12 in the upper-left corner of the illustrated superblock writes
to a horizontal local bus. If a particular cell 12 writes to a horizontal
local bus, then its four immediate neighbors write to vertical local
busses, and vice versa.
As shown in FIG. 13, the two types of cells 12 are thus arranged in a
checker-board pattern where the black cells 12 write to horizontal busses
and the white cells 12 write to vertical busses.
The CLA busses can be driven by the bus driver 28 in two ways. The bus
driver 28 has two control bits, "TS" and "OC", which provide high
impedance and open-collector capabilities, respectively. The tri-state
capability, which is independently programmable for each cell 12, allows
the bus driver to be disconnected from the bus when the cell 12 is not
being used to write to the bus.
The open-collector capability provides the wired-AND function when multiple
cells 12 are driving the same local bus simultaneously. Unlike the high
impedance function, which is controlled at the cell level, the
open-collector function is controlled at the bus level; all cells 12
driving the same local bus are in the same open-collector state. The
programming environment insures that if there is exactly one driver 28
driving a local bus, then that driver 28 provides active pull-up and
active pull-down. (The open-collector capability is turned off.) In all
other cases, the drivers 28 driving a local bus provide passive pull-up
and active pull-down. (The open-collector capability is turned on.)
In the special case when there are no drivers 28 driving a local bus (that
is, when the bus is not used), the open-collector capability is turned on
and the bus is pulled high through the passive pull-up resistor. An unused
local bus, therefore, provides a logical "1" to those cells reading the
bus.
As stated above, repeaters provide connections between busses. Each
repeater is programmable so that any bus on one side of a repeater can be
connected to any bus on the other side of the repeater, as shown in FIG.
15. Each connection is unidirectional (direction is not depicted in FIG.
15) since repeaters always provide signal regeneration. The direction,
like the connection itself, is programmable. Including direction, there
are 18 (2.times.9) repeater configurations providing one connection, 72
(4.times.18) providing two connections, and 48 (8.times.6) providing three
connections.
As shown in FIG. 16, logic 19 for distributing clock signals to the D
flip-flops 20 in the logic cells 12 is located along one edge of the array
10. The distribution network is organized by column and permits columns of
cells 12 to be independently clocked. At the head of each column is a
user-configurable multiplexer 30 providing the clock signal for that
column. There are four inputs to each multiplexer 30: an external clock
supplied from off chip, the logical constant "0", the express bus adjacent
to the distribution logic, and the A output of the cell 12 at the head of
the corresponding column.
Through the global clock, the network provides low-skew distribution of an
externally supplied clock to any or all of the columns of the array 10.
The constant "0" is used to reduce power dissipation in columns containing
no registers. The express bus is useful in distributing a secondary clock
to multiple columns when the external clock line is used as a primary
clock. The A output of a cell is useful in providing a clock signal to a
signal column.
All D flip-flops 20 of the cells 12 of the array 10 may be globally reset
through an externally supplied signal entering the RESET control pin.
The CLA array 10 provides a flexible interface between the logic array,
configuration control logic and the I/O pads of the CLA device. As shown
in FIG. 17, two adjacent cells, an "exit" cell 12a and an "entrance" cell
12b, on the perimeter of the logic array are associated with each I/O pad
32. The A output of the exit cell 12a is connected, under program control,
to an output buffer 34. The edge-facing A input of the adjacent entrance
cell 12b is connected to an input buffer 36. The output of the output
buffer 34 and the input to the input buffer 36 are both connected to the
I/O pad 32. Control of the I/O logic is provided by various control
signals and bits, as shown in FIG. 17.
While the CLA array 10 described above provides a wide range of
configuration options, it would be desirable to have available a CLA
device that provides an even greater level of programmable flexibility.
The present invention provides a configurable logic array that includes a
plurality of individually configurable logic cells arranged in a matrix
that includes a plurality of rows of logic cells and a plurality of
columns of logic cells. The array further includes at least one
horizontally aligned local bus running between adjacent rows of logic
cells, the logic cells in the adjacent rows being connectable thereto, and
at least one vertically aligned local bus running between adjacent columns
of logic cells, the logic cells in the adjacent columns being connectable
thereto. The array also includes means for configuring the array such that
any logic cell A in the array can write to a local bus which can be linked
through the array's bussing network so that logic cell A can be read by
any other logic cell B; correspondingly, logic cell B can write to a local
bus which is linked through the same components such that data written by
logic cell B can be read by logic cell A. Whether a logic element is
reading from or writing to a local bus in controlled by a logic function
created in the array. The configuration capability is due to means for
placing the bus drivers in a high impedance state, means for bidirectional
bussing capability due to extra passgates in the array repeaters, and
means for connecting horizontal busses to vertical busses through the use
of a core cell to bus interface.
A better understanding of the features and advantages of the present
invention will be obtained by reference to the following detailed
description and accompanying drawings which set forth an illustrative
embodiment in which the principles of the invention are utilized.
DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram illustrating a portion of a first type of
conventional configurable logic array architecture.
FIG. 2 is a schematic diagram illustrating a cell-to-cell interconnect
structure utilizable in the FIG. 1 CLA array.
FIG. 3 is a logic diagram illustrating a logic cell utilizable in the FIG.
1 CLA array.
FIG. 4 is a logic diagram illustrating a portion of a second type of
conventional configurable logic array architecture.
FIG. 5 is a logic diagram illustrating a logic cell utilizable in the FIG.
4 CLA array.
FIG. 6 is a block diagram illustrating a portion of third type of
conventional configurable logic array.
FIG. 7 is a logic diagram illustrating a logic cell utilizable in the FIG.
6 CLA array.
FIGS.8A-8D are simple logic diagrams illustrating four possible logic
configurations of the FIG. 7 logic cell.
FIG. 9 is a schematic diagram illustrating a bussing network for the FIG. 6
CLA array.
FIG. 10 is a schematic diagram illustrating local bus segments for the FIG.
9 bussing network.
FIG. 11 is a schematic diagram illustrating turning bus segments for the
FIG. 9 bussing network.
FIG. 12 is a schematic diagram illustrating express bus segments for the
FIG. 9 bussing network.
FIG. 13 is a schematic diagram illustrating the combination of the local,
turning and express bus segments of the FIG. 9 bussing network.
FIG. 14 is a schematic diagram illustrating the FIG. 7 logic cell augmented
to permit read/write of local busses.
FIG. 15 illustrates the multiple possible repeater configurations for
inter-bus connections in the FIG. 9 bussing network.
FIG. 16 is a block diagram illustrating clock distribution logic utilizable
in the FIG. 6 CLA array.
FIG. 17 is a logic diagram illustrating "exit" and "entrance" cells
associated with each I/O pad of the FIG. 6 CLA array.
FIG. 18 is a block diagram illustrating a portion of a configurable logic
array in accordance with the present invention.
FIG. 19 is a block diagram illustrating the bus turning capability of a
logic cell of the FIG. 18 CLA array.
FIG. 20 is a schematic representation illustrating the interface between a
cell and local busses in the FIG. 18 CLA array.
FIG. 20A is a schematic representation illustrating an alternate interface
between a cell and the local busses of the FIG. 18 CLA array.
FIG. 21 is a schematic representation illustrating the implementation of
individual control of the local busses in the FIG. 18 CLA array.
FIG. 22 is a block diagram illustrating express busses in the FIG. 18 CLA
array.
FIG. 23A is a schematic representation illustrating utilization of
repeaters in the FIG. 18 CLA array.
FIG. 23B is a schematic representation illustrating repeaters utilized in
the FIG. 18 CLA array.
FIG. 24 is a schematic representation illustrating diagonal connections
between abutting logic cells in the FIG. 18 CLA array.
FIG. 25 is a schematic representation illustrating diagonal local busses in
the FIG. 18 CLA array.
FIG. 26 is a functional diagram illustrating a logic cell utilizable in the
FIG. 18 CLA array.
FIG. 27 illustrates sixteen basic configurations of the FIG. 26 logic cell.
FIG. 28 is a schematic representation of a possible modification to the
FIG. 26 logic cell.
FIG. 29 is a logic diagram illustrating an alternate embodiment of a logic
cell utilizable in the FIG. 18 CLA array.
FIG. 30 is a logic diagram illustrating a tristatable output buffer circuit
utilizable in the FIG. 18 CLA array.
FIG. 31 is a schematic representation of the sequential configuration of
multiple CLA arrays of the type shown in FIG. 18.
FIG. 32 is a schematic diagram illustrating a power up sensing circuit
utilizable in the FIG. 18 CLA array.
FIG. 33 is a graph illustrating the hysteresis of the FIG. 32 power up
sensing circuit.
FIG. 34 is a block diagram illustrating edge core cells and I/O cells in
the FIG. 18 CLA array.
FIG. 35 is a block diagram illustrating express bus I/O cells in the FIG.
18 CLA array.
FIG. 36 is a block diagram illustrating configuration logic for the FIG. 18
CLA array.
FIG. 37 is a schematic representation illustrating the loading of a
configuration file into the internal configuration SRAM within the FIG. 18
CLA array.
FIG. 38 is a schematic representation illustrating the bit sequential,
internal clock configuration mode of the FIG. 18 CLA array.
FIG. 39 is a schematic representation illustrating the bit sequential,
external clock configuration mode of the FIG. 18 CLA array.
FIG. 40 is a schematic representation illustrating the cascaded
configuration of multiple CLAs of the type shown in FIG. 18.
FIG. 41 is a schematic representation illustrating the parallel
configuration of multiple CLAs of the type shown in FIG. 18.
FIG. 42 is a schematic representation illustrating the address count-up,
external clock configuration mode of the FIG. 18 CLA array.
FIG. 43 is a schematic representation illustrating the address count-up,
external clock configuration mode of the FIG. 18 CLA array.
FIG. 44 is a schematic representation illustrating the byte-sequential,
external clock configuration mode of the FIG. 18 CLA array.
DETAILED DESCRIPTION OF THE INVENTION
FIG. 18 shows a configurable logic array 100 comprising a matrix of
individual programmable logic cells 102. As shown by the "typical" logic
cell 102 in FIG. 18, each logic cell 102 receives eight inputs from and
provides eight outputs to its North (N), East (E), South (S) and West (W)
neighbors.
These sixteen inputs and outputs are divided into two types, "A" and "B",
with an A input, an A output, a B input and a B output for each
neighboring cell. Between cells 102, an A output is always connected to an
A input and a B output is always connected to a B input.
As further shown in FIG. 18, the CLA array 100 includes two local busses
L.sub.N, L.sub.S in the x direction and two local buses L.sub.E, L.sub.W
in the y direction running between each row and column of cells 102,
respectively, in the array 100. Thus, each cell 102 has access to four
local busses. The local busses allow efficient interconnections between
cells 102 that are not nearest neighbors cells in the same row or column.
Any of these local busses may be active within any given cell 102. However,
a cell's connections to local busses must be selected either only as
inputs or only as outputs if they are used at all by the cell 102, except
when used as a bus-to-bus connection or when the FIG. 21 alternative
scheme, described below, is used. If selected as inputs, then only one of
the local busses can be enabled. If selected as outputs, then a cell 102
can drive up to all four of its accessible local busses.
As shown in FIG. 19, a cell 102 may allow a turn from a local bus L.sub.N,
L.sub.S running in the x direction to a local bus L.sub.E, L.sub.W running
in the y direction. This type of connection is useful when two
non-neighboring cells 102 must be connected to one another and the cells
102 are not in the same row or the same column. In this case, the cell 102
that facilitates the turn cannot use the local busses as an input or an
output. If a cell 102 is using its local busses for anything other than an
input, then the output of the local bus input mux (Lin in FIG. 26) is
forced to a "1".
FIG. 20 shows the functional implementation of the interface between a cell
102 and the local busses.
As shown in FIG. 20, a cell 102 can drive signal A onto any combination of
its associated local busses, L.sub.N, L.sub.S, L.sub.E and L.sub.W by
activating various combinations of the transmission gates controlled by
signals CL.sub.N, CL.sub.S, CL.sub.E, CL.sub.W and CL.sub.OUT. A cell 102
can receive input from any one of its associated local busses L.sub.N,
L.sub.S, L.sub.E and L.sub.W by activating the transmission gate
controlled by signal CL.sub.IN along with activating one of the
transmission gates controlled by signals CL.sub.N, CL.sub.S, CL.sub.E, and
CL.sub.W. If signal CL.sub.IN disables its transmission gate, then
p-channel pullup transistor P provides a logic "1" level on signal Lin.
If the transmission gates controlled by signals CL.sub.OUT and CL.sub.IN
are both disabled, then the local bus interface shown in FIG. 20 can
facilitate a connection from any of its associated local busses to any or
all others. This capability allows turns from a horizontal local bus to a
vertical local bus.
The cell/bus connection scheme shown in FIG. 20 can be extended to
accommodate a larger number of busses and to allow multiple simultaneous
turns between horizontal and vertical busses.
FIG. 20A illustrates an interface scheme that assumes four horizontal local
buses (EW0, EW1, EW2 and EW3) and four vertical local buses (NS0, NS1, NS2
and NS3). For each pair of corresponding busses, e.g. NS0 and EW0, there
are three bidirectional pass gates connected in a tree, as illustrated.
Each of the eight upper pass gates, i.e. those connected directly to the
busses, are controlled by a separate configuration bit. The four lower
pass gates, i.e. those connected directly to the cell, may be controlled
either by individual bits or, in order to conserve configuration bits, by
control signals derived from the configuration bits controlling the upper
pass gates.
For example, assume that "A" and "B" are the configuration bits controlling
the upper pass gates associated with NS0 and EW0, respectively. Then
either A XOR B or A NAND B can be used to control the corresponding lower
pass gate. Note that, in both cases, the lower pass gate is turned off
when both upper pass gates are turned on--this is a bus turn. Note also
that when exactly one of the upper pass gates is turned on, the lower pass
gate is also turned on--this is either a read or a write to the cell. When
both upper pass gates are turned off, the state of the lower pass gate is
a "don't care".
As in the FIG. 20 scheme, the FIG. 20A scheme uses the same pass gates for
both reading and writing. In addition, however, it is now possible to have
up to four simultaneous bus turns when the cell is not accessing the bus,
or up to three simultaneous turns when the cell is accessing the bus.
Alternatively, as shown in FIG. 21, rather than constraining all four local
bus connections to all being inputs or all being outputs, configuration
memory and multiplexors can be added so that the bus connections can be
individually controlled. In this way, one bus connection could be an input
and, simultaneously, another bus connection could be an output in
situations other then bus-to-bus connections. This would reduce the number
of cells 102 required for routing in the array 100.
As shown in FIG. 22, in addition to the local busses described above, the
array 100 includes two express busses X.sub.N, X.sub.S running in the x
direction and two express busses X.sub.E, X.sub.W running in the y
direction between each row and column, respectively, of cells 102 in the
array 100. Each express bus is associated with one local bus. Entry
to/from an express bus is only possible from/to its associated local bus
at the repeater.
As shown in FIG. 23A, repeaters R are spaced eight cells 102 apart. A block
of cells 102 surrounded by repeaters R is referred to as a "superblock".
An express bus allows a signal to travel a distance of eight cells 102
without additional variable loads, giving it the highest speed possible
for the full length of the superblock.
Repeaters R are used to regenerate bus signals and to drive the different
bus segments at the superblock interface. A repeater R is shown in FIG.
23B. Under configuration control, the following paths in the repeater are
possible:
______________________________________
Description: Path in FIG. 23B
______________________________________
Local Bus L1 drives Local Bus L2
D1-PG3
Local Bus L2 drives Local Bus L1
D3-PG6
Express Bus X1 drives Express Bus X2
D2-PG5
Express Bus X2 drives Express Bus X1
D4-PG8
L1 drives Local Bus L2 & Express Bus X2
D1-PG3 & PG2
L2 drives Local Bus L1 & Express Bus X1
D3-PG6 & PG7
X1 drives Express Buss X2 & Local Bus L2
D2-PG5 & PG4
X2 drives Express Buss X1 & Local Bus L1
D4-PG8- & PG9
Local Busses L1 & L2 are single
PG1
bidirectional bus
(This latter path can be used to make a long busses
spanning multiple repeaters.)
______________________________________
Additionally, as shown in FIG. 24, the CLA array 100 can include diagonal
interconnections between abutting cells 102. With diagonal cell
interconnection, a substantially smaller number of cells 102 are used by
certain macros for interconnections, thereby improving performance and
gate array utilization and increasing the interconnect resources.
As shown in FIG. 24, data flows diagonally from left to right. Each cell
102 requires an additional input to the input mux and an additional output
to the bottom right. The diagonal interconnect concept can be extended to
data flowing diagonally from right to left (top to bottom), left to right
(bottom to top) and right to left (bottom to top).
As shown in FIG. 25, and in accordance with another aspect of the present
invention, the array 100 can include an additional set of local vertical
buses and an additional set of local horizontal busses. However, instead
of these busses being purely vertical and horizontal, as in the case of
the local busses discussed above, this second set of local busses runs
diagonally. Thus, as shown in FIG. 25, one set of these busses attaches to
the cell's East side and one attaches the cell's South side. In this
architecture, every cell 102 is capable of driving each of the busses to
which it is attached. In this arrangement, each cell 102 in the array 100
can connect more easily to nearby cells 102 in a diagonal direction, a
very useful feature in compute-intensive algorithms and in random logic.
Each programmable function of the CLA 100 is controlled by one or more
transistor pass gates, each of which as its pass-or-block state determined
by the state of a memory bit, either directly or through a decoder. All of
these registers are collectively referred to as SRAM Configuration Data
Storage. The advantage of an SRAM (Static Random Access Memory), as
opposed to a ROM (Read Only Memory), in this application, is that the
configuration data can be changed a virtually unlimited number of times by
simply rewriting the data in the SRAM.
The functional diagram for an embodiment of the logic cell 102 is shown in
FIG. 26. It consists of five 4:1 muxes, (shown in pass-gate form), cell
function logic, and 4 high impedance local bus connectors (also shown in
pass-gate form) drivers. Three of the 4:1 muxes determine the A, B, and L
inputs to be used by the cell function logic. If no input to a mux is
selected, then the output of the mux is forced to a logical "1" state. The
cell function logic implements the function to be applied to the A, B and
L inputs and supplies the result to the A and B output muxes. The four
pass gates connecting the cell to the local busses allow the cell 102 to
drive its corresponding local busses or receivers signals from the busses.
The application of the illustrated technology uses 16 bits of SRAM for each
cell's configuration memory address space to define the functionality of
the FIG. 26 logic cell 102. Fourteen bits are used for input and output
multiplex control. The remaining two bits are used to determine the cell's
use of its associated local busses. These two bits (BUS0, BUS1), combined
with the number of local busses enabled for a given cell, determine the
function of the local busses within the cell, as shown in Table I below.
If BUS0 is a "1", then either 1 or 2 of the local busses must be selected.
Otherwise, any number of local busses may be selected, within the dictates
of Table I.
TABLE I
______________________________________
L's local bus
en- function TRI-STATE
BUS0 BUS1 abled within cell
Li Control
______________________________________
0 0 0 not used
"1" "0"(disabled)
0 0 1-4 output "1" "0"(enabled
0 1 0 not used
"1" "0"
0 1 1-4 output "1" Bin
1 0 1 input enabled L
"0"
1 0 2 x/y turn
"1" "0"
1 1 1 mux select
enabled L
"0"
1 1 2 x/y turn
"1" "0"
______________________________________
The function of the cell's control/configuration bits is described in Table
II below.
TABLE II
______________________________________
SIGNALS # OF BITS DESCRIPTION
______________________________________
CAN,CAS 4 A Input mux selects (zero
CAE,CAW or one enabled)
CBN,CBS 4 B Input mux selects (zero
CBE,CBW or one enabled)
CLN,CLS 4 L enables (any number, per
CLE,CLW Table I)
BUS0,BUS1 2 Determines local bus function
within cell
CFUN0,CFUN1
2 A and B output function select
______________________________________
Thus, there are sixteen primary functional configurations of the CLA cell
102, based on the sixteen possible combinations at signals CFUN1, CFUN2,
BUS0 and BUS1. FIG. 27 shows the functional diagrams of these sixteen
configurations.
Other applications of this technology may use more (or less) than 16 SRAM
configuration bits per cell, e.g. to switch the connections of additional
busses.
FIG. 28 shows a possible modification to the FIG. 26 logic cell 102 that
allows the high impedance control signal to be input over the local bus
through the L mux. Additionally, both the local bus input and the B input
of the cell can be used for control of the high impedance state. This
allows the user the flexibility of using either of the inputs for high
impedance control, thereby saving cells used for wiring. As shown in FIG.
28, the high impedance control signal is provided by the output of OR gate
104. The L-mux and B-mux outputs, with the high impedance enable signal,
are inputs to the OR gate 104. This facilitates using either the local bus
inputs (through the L-mux) or the B inputs (through the B-mux) as the high
impedance control signal.
FIG. 29 shows an alternative embodiment of logic cell 102. The alternate
cell utilizes six-state output muxes, giving the user the flexibility of
obtaining the outputs of the XOR, Flip-Flop, NAND and AND functions on
either the A output or B output of t | | |
