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Claims  |
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What is claimed is:
1. An active filter circuit, comprising:
a first differential pair constructed to include first and second
transistors;
a first capacitive load connected to a collector of said second transistor
of said first differential pair;
a first negative feed-back transistor for feeding-back an output at said
collector of said second transistor to a base of said second transistor;
a second differential pair constructed to include third and fourth
transistors;
a second capacitive load connected to a collector of said fourth transistor
of said second differential pair;
a second negative feed-back transistor for feeding-back an output at said
collector of said fourth transistor to a base of said first transistor
constituting said first differential pair;
fifth and sixth transistors for forming a first current mirror circuit
which is connected to said collector of said second transistor;
seventh and eighth transistors for forming a second current mirror circuit
which is connected to said collector of said fourth transistor; and
biasing means formed in association with at least one of said first and
second differential pairs for applying bias voltage to bases of two
transistors constituting said at least one of the differential pairs, said
biasing means including resistor voltage-dividing means for applying a
divided voltage to respective bases of said two transistors as said bias
voltages.
2. An active filter circuit, comprising:
a first differential pair constructed to include first and second
transistors;
a first capacitive load connected to a collector of said second transistor
of said first differential pair;
a second differential pair constructed to include third and fourth
transistors;
a fifth transistor for supplying an output at said collector of said second
transistor of said first differential pair to a base of said fourth
transistor of said second differential pair;
a second capacitive load connected to said collector of said fourth
transistor;
a negative feed-back transistor for feeding-back an output at said
collector of said fourth transistor to a base of said first transistor
constituting said first differential pair;
sixth and seventh transistors for forming a first current mirror circuit
which is connected to said collector of said second transistor;
eighth and ninth transistors for forming a current mirror circuit which is
connected to said collector of said fourth transistor; and
biasing means formed in association with at least one of said first and
second differential pairs for applying bias voltages to bases of two
transistors constituting said at least one of the differential pairs, said
biasing means including resistor voltage-dividing means for applying a
divided voltage to respective bases of said two transistors as said bias
voltages.
3. An active filter circuit in accordance with claim 1 or 2, further
comprising current changing means for correlatively changing circuit
amounts of said first and second differential pairs in response to a given
control voltage.
4. An active filter circuit in accordance with claim 1, wherein said
resistor voltage-dividing means includes a first resistor series
connection having a series connecting point connected to the base of one
of said two transistors, and a second resistor series connection having a
series connecting point connected to the base of another of said two
transistors.
5. An active filter circuit in accordance with claim 4, wherein said
biasing means includes a bias voltage source, and respective one ends of
the two resistor series connections are connected to said bias voltage
source.
6. An active filter circuit in accordance with claim 4, wherein said first
and second resistor series connections include a common resistor which is
interconnected between the bases of said two transistors.
7. A filter controlling circuit, comprising:
a filter for receiving an input and for outputting an output with a phase
characteristic, said phase characteristic of said filter changing in
accordance with a control voltage;
means, coupled to said filter, for outputting a direct current voltage
component having a level based on said phase characteristic of said output
of said filter;
level comparing means for comparing said level of said direct current
voltage component with a reference voltage; and
means for applying said control voltage to said filter based upon an output
of said level comparing means.
8. A filter controlling circuit in accordance with claim 7, wherein said
filter includes:
a first differential pair constructed to include a first and second
transistors;
a first capacitive load connected to an output of said second transistor of
said first differential pair;
a first negative feed-back path for feeding-back an output of said second
transistor to an input thereof;
a second differential pair constructed to include a third and fourth
transistors;
a second capacitive load connected to an output of said fourth transistor
of said second differential pair;
a second negative feed-back path for feeding-back an output of said fourth
transistor to an input of said first transistor constituting the first
differential pair; and
current changing means for correlatively changing current amounts of said
first and second differential pairs in response to said control voltage.
9. A filter controlling circuit in accordance with claim 7, wherein said
filter include:
a first differential pair constructed to include a first and second
transistors;
a first capacitive load connected to an output of said second transistor of
said first differential pair;
a second differential pair constructed to include a third and fourth
transistors;
a connecting path for connecting an output of said second transistor of
said first differential pair to an input of said fourth transistor of said
second differential pair;
a second capacitive load connected to an output of said fourth transistor;
a negative feed-back path for feeding-back an output of said fourth
transistor to an input of said first transistor constituting said first
differential pair; and
current changing means for correlatively changing current amounts of said
first and second differential pairs in response to said control voltage.
10. A filter controlling circuit comprising:
a filter, a center frequency of said filter being able to be changed in
accordance with a control voltage;
amplifying means having a gain of 1 or more for feeding-back an output of
said filter to an input of said filter;
phase comparing means receiving the output of said filter and a further
input signal; and
means for applying said control voltage to said filter based upon an output
of said phase comparing means, wherein said filter includes,
a first differential pair constructed to include first and second
transistors;
a first capacitive load connected to a collector of said second transistor
of said first differential pair;
a first negative feed-back path for feeding-back an output at said
collector of said second transistor to a base of said second transistor;
a second differential pair constructed to include third and fourth
transistors;
a second capacitive load connected to a collector of said fourth transistor
of said second differential pair;
a second negative feed-back path for feeding-back an output at said
collector of said fourth transistor to a base of said first transistor
constituting said first differential pair;
current changing means for correlatively changing current amounts of said
first and second differential pairs in response to said control voltage;
and
biasing means formed in association with at least one of said first and
second differential pairs for applying bias voltages to bases of two
transistors constituting said at least one of the differential pairs, said
biasing means including resistor voltage-dividing means or applying a
divided voltage to respective bases of said two transistors as said bias
voltages.
11. A filter controlling circuit comprising:
a filter, a center frequency of said filter being able to be changed in
accordance with a control voltage;
amplifying means having a gain of 1 or more for feeding-back an output of
said filter to an input of said filter;
phase comparing means receiving the output of said filter and a further
input signal; and
means for applying said control voltage to said filter based upon an output
of said phase comparing means, wherein said filter includes,
a first differential pair constructed to include first and second
transistors;
a first capacitive load connected to a collector of said second transistors
of said first differential pair;
a second differential pair constructed to include third and fourth
transistors;
a connecting path for connecting said collector of said second transistor
of said first differential pair to a base of said fourth transistor of
said second differential pair;
a second capacitive load connected to said collector of said fourth
transistor;
a negative feed-back path for feeding-back said collector of said fourth
transistor to a base of said first transistor constituting said first
differential pair;
current changing means for correlatively changing current amounts of said
first and second differential pairs in response to said control voltage;
and
biasing means formed in association with at least one of said first and
second differential pairs for applying bias voltages to bases of two
transistors constituting said at least one of the differential pairs, said
biasing means including resistor voltage-dividing means for applying a
divided voltage to respective bases of said two transistors as said bias
voltages.
12. A filter controlling circuit in accordance with claim 7, wherein said
filter includes:
a first differential pair constructed to include first and second
transistors;
a first capacitive load connected to an output of said second transistor of
said first differential pair;
a first negative feed-back path for feeding-back an output of said second
transistor to an input thereof;
a second differential pair constructed to include third and fourth
transistors;
a second capacitor load connected to an output of said fourth transistor of
said second differential pair;
a second negative feed-back path for feeding-back an output of said fourth
transistor to an input of said first transistor constituting the first
differential pair;
current changing means for correlatively changing current amounts of said
first and second differential pairs in response to said control voltage;
and
biasing means formed in association with at least one of said first and
second differential pairs for applying bias voltages to bases of two
transistors constituting said at least one of the differential pairs, said
biasing means including resistor voltage-dividing means for applying a
divided voltage to respective bases of said two transistors as said bias
voltages.
13. A filter controlling circuit in accordance with claim 7, wherein said
filter includes:
a first differential pair constructed to include first and second
transistors;
a first capacitive load connected to an output of said second transistor of
said first differential pair;
a second differential pair constructed to include third and fourth
transistors;
a connecting path for connecting an output of said second transistor of
said first differential pair to an input of said fourth transistor of said
second differential pair;
a second capacitive load connected to an output of said fourth transistor;
a negative feed-back path for feeding-back an output of said fourth
transistor to an input of said first transistor constituting said first
differential pair;
current changing means for correlatively changing current amounts of said
first and second differential pairs in response to said control voltage;
and
biasing means formed in association with at least one of said first and
second differential pairs for applying bias voltages to bases of two
transistors constituting said at least one of the differential pairs, said
biasing means including resistor voltage-dividing means for applying a
divided voltage to respective bases of said two transistors as said bias
voltage.
14. An active filter circuit in accordance with claim 2, wherein said
resistor voltage-dividing means includes a first resistor series
connection having a series connecting point connected to the base of one
of said two transistors, and a second resistor series connection having a
series connecting point connected to the base of another of said two
transistors.
15. An active filter circuit, comprising:
a first differential pair constructed to include first and second
transistors;
a first capacitive load connected to a collector of said second transistor
of said first differential pair;
a first negative feed-back transistor for feeding-back an output at said
collector of said second transistor to a base of said second transistor;
a second differential pair constructed to include third and fourth
transistors;
a second capacitive load connected to a collector of said fourth transistor
of said second differential pair;
a second negative feed-back transistor for feeding-back an output at said
collector of said fourth transistor to a base of said first transistor
constituting said first differential pair;
fifth and sixth transistors for forming a first current mirror circuit
which is connected to said collector of said second transistor; and
seventh and eighth transistors for forming a second current mirror circuit
which is connected to said collector of said fourth transistor.
16. An active filter circuit according to claim 15, further comprising a
third current mirror circuit for determining currents of said first
current mirror circuit, said second current mirror circuit, said first
differential pair and said second differential pair.
17. An active filter circuit according to claim 16, further comprising a
terminal for inputting a control signal, a current of said third current
mirror circuit being controlled by said control signal such that a filter
characteristic of said active filter can be changed.
18. An active filter circuit, comprising:
a first differential pair constructed to include first and second
transistors;
a first capacitive load connected to a collector of said second transistor
of said first differential pair;
a second differential pair constructed to include third and fourth
transistors;
a fifth transistor for supplying an output at said collector of said second
transistor of said first differential pair to a base of said fourth
transistor of said second differential pair;
a second capacitive load connected to a collector of said fourth
transistor;
a negative feed-back transistor for feeding-back an output at said
collector of said fourth transistor to a base of said first transistor
constituting said first differential pair;
sixth and seventh transistors for forming a current mirror circuit which is
connected to said collector of said second transistor; and
eighth and ninth transistors for forming a current mirror circuit which is
connected to said collector of said fourth transistor.
19. An active filter circuit according to claim 18, further comprising a
third current mirror circuit for determining currents of said first
current mirror circuit, said second current mirror circuit, said first
differential pair and said second differential pair.
20. An active filter circuit according to claim 19, further comprising a
terminal for inputting a control signal, a current of said third mirror
circuit being controlled by said control signal such that a filter
characteristic of said active filter circuit can be changed.
21. A filter controlling circuit as claimed in claim 7 wherein said means
for outputting a direct current voltage component includes a multiplier
and a low-pass filter. |
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Claims |
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Description |
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BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an active filter circuit. More
specifically, the present invention relates to an active filter circuit
suitable for an integration circuit (IC).
2. Description of the Prior Art
In a case where a filter is to be incorporated in an integrated circuit,
due to variations of elements in the IC, a fluctuation takes place in a
filter characteristic. Conventionally, in order to compensate for such a
fluctuation, there was one method in which a dummy reference filter is
provided in the IC and a reference signal is input thereto, and a
feed-back control is applied to the reference filter so that a value of an
output of the reference filter becomes a desired value. Based upon an idea
that since a filter to be controlled comprises resistors and capacitors
being the same as or correlative to that of the reference filter and
therefore, a filter characteristic of the filter to be controlled can be
adjusted to the same as or correlative to the characteristic of the
reference filter if and when the same or correlative control signal is
applied thereto, this method is a method for controlling the other filter
to be controlled within the IC.
A prior art shown in FIG. 1 is one example of a case where a cut-off
frequency fc of a lowpass filter is automatically controlled. First, a
reference signal having a predetermined reference frequency Fref is input
to a reference filter, and a level of a signal that is obtained by
amplifying an output of the reference filter is compared with an output
level of a reference frequency signal oscillator, a control voltage Vc by
which both the levels are become coincident with each other is out, and
the control voltage is applied to a variable capacitance diode Cv so that
the filter characteristic is changed. By applying this feed-back control,
when an attenuation amount at the reference frequency in the filter
becomes equal to a gain of the amplifier, both levels becomes equal to
each other and thus the filter is brought into an adjusted state.
In the conventional method shown in FIG. 1, it is not necessary to apply a
signal externally to adjust the filter incorporated in the IC; however,
since a dummy reference filter is to be provided in the IC, not only the
number of elements in the IC increases but also the reference signal
oscillator is needed.
One example of a filter circuit suitable for an IC is disclosed in, for
example, Japanese Patent Publication No. 61-55860 published on Nov. 29,
1986.
In a filter circuit disclosed in Japanese Patent Publication No. 61-55806,
in order to implement a high-pass filter circuit, it is necessary to add a
subtracter, and therefore, there was a problem that not only the number of
circuit components increases but also a circuit configuration becomes
complex.
SUMMARY OF THE INVENTION
Therefore, a principal object of the present invention is to provide a
novel active filter circuit.
Another object of the present invention is to provide an active filter
circuit having a simple circuit configuration and suitable for an IC.
The other object of the present invention is to provide various kinds of
filter controlling circuits which utilize such a novel active filter
circuit.
An active filter circuit in accordance with the present invention
comprises: a first differential pair constructed to include a first and
second transistors; a first capacitive load connected to an output of the
second transistor of the first differential pair; a first negative
feed-back path for feeding-back an output of the second transistor to an
input thereof; a second differential pair constructed to include a third
and fourth transistors; a second capacitive load connected to an output of
the fourth transistor of the second differential pair; and a second
negative feed-back path for feeding-back an output of the fourth
transistor to an input of the first transistor constituting the first
differential pair.
In this invention, by the first and second negative feed-back paths, both
of the first and second differential pairs operate in the vicinity of a
center of a linear region thereof, and therefore, the first and second
differential pairs cooperates to function as a secondary active filter
circuit.
In another aspect, an active filter circuit in accordance with the present
invention comprises: a first differential pair constructed to include a
first and second transistors of first capacitive load connected to an
output of the second transistor of the first differential pair; a second
differential pair constructed to include a third and fourth transistors; a
connecting path for connecting an output of the second transistor of the
first differential pair to an input of the fourth transistor of the second
differential pair; a second capacitive load connected to an output of the
fourth transistor; and a negative feed-back path for feeding-back an
output of the fourth transistor to an input of the first transistor
constituting the first differential pair.
In this aspect, by the connecting path and the negative feed-back path,
both of the first and second differential pairs operate in the vicinity of
a center of a linear region thereof, and therefore, the first and second
differential pairs cooperate to function as a secondary active filter
circuit.
In accordance with the present invention, since it is not necessary to
provide additional circuits such as a subtracter and etc., it is possible
to obtain an active filter circuit suitable for an IC without the increase
of the number of circuit components and the complication of the circuit
configuration.
Furthermore, in accordance with the present invention, since different
kinds of filters can be constructed by the same circuit configuration,
respective filters are very correlative with each other, and therefore, it
is possible to adjust the filters very easy.
The objects and other objects, features, aspects and advantages of the
present invention will become more apparent from the following detailed
description of the embodiments of the present invention when taken in
conjunction with accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a circuit diagram showing a conventional method for automatically
controlling a cut-off frequency of a lowpass filter.
FIG. 2A to FIG. 2C are circuit diagrams showing differential pairs which
can be utilized in the present invention.
FIG. 3 is a circuit diagram showing one embodiment in accordance with the
present invention.
FIG. 4 is a circuit diagram showing FIG. 3 embodiment in detail.
FIG. 5 is a circuit diagram showing another embodiment in accordance with
the present invention.
FIG. 6 is a circuit diagram showing FIG. 5 embodiment in detail.
FIG. 7 is a circuit diagram showing a modified example of FIG. 4
embodiment.
FIG. 8 is a circuit diagram showing a modified example of FIG. 7
embodiment.
FIG. 9 is a circuit diagram showing a further modified example of FIG. 4
embodiment.
FIG. 10 is a circuit diagram showing a modified example of FIG. 9
embodiment.
FIG. 11 is a circuit diagram showing a modified example of FIG. 6
embodiment.
FIG. 12 is a circuit diagram showing a modified example of FIG. 11
embodiment.
FIG. 13 is a circuit diagram showing a further modified example of FIG. 6
embodiment.
FIG. 14 is a circuit diagram showing a modified example of FIG. 13
embodiment.
FIG. 15A to FIG. 15D are circuit diagrams respectively showing other
embodiments in accordance with the present invention.
FIG. 16A to FIG. 16D are circuit diagrams respectively showing embodiments
shown in FIG. 15A to FIG. 15D in detail.
FIG. 17 is a block diagram showing an embodiment of a phase locked loop
(PLL) which utilizes an active filter circuit in accordance with the
present invention.
FIG. 18 and FIG. 19 are block diagrams respectively showing modified
examples in each of which a crystal filter is added to FIG. 17 embodiment.
FIG. 20 is a block diagram showing a chroma circuit as another embodiment
in accordance with the present invention.
FIG. 21 is a block diagram showing a quadrature detecting circuit as
another embodiment in accordance with the present invention.
FIG. 22 is a block diagram showing a VIF and SIF circuit as another
embodiment in accordance with the present invention.
FIG. 23 is a block diagram showing an FM circuit as the other embodiment in
accordance with the present invention.
DETAIL DESCRIPTION OF THE PREFERRED EMBODIMENTS
Prior to a description of specific active filter circuits in accordance
with the present invention, first, a differential pair, which includes a
pair of transistors and which can be utilized as active filter circuits,
will be described.
In a differential pair 1 composed of transistors Q1 and Q2 as shown in FIG.
2A, assuming that a load resistor is RL, a collector voltage V0 of the
transistor Q2 is represented by the following equation (1);
V0=gm.multidot.RL.multidot.(V3-V2) (1)
where gm is a mutual conductance.
Assuming that a charge of an electron is q, Boltzmann's constant is k, a
current is I1, and an absolute temperature is T, a relationship
represented by the following equation (2) is established.
##EQU1##
In addition, an emitter resistor, that is, differential resistor re of each
of the transistors Q1 and Q2 constituting the differential pair 1 is given
by the following equation (3).
##EQU2##
Therefore, the above equation (1) can be modified as the following equation
(4).
##EQU3##
Next, as shown in FIG. 2B, if the load resistor RL is replaced with a
constant current source having a current amount of I1 and a capacitor C
which serves as a capacitive load is connected to a collector of the
transistor Q2, since an impedence of the constant current source can be
regarded as infinity and an impedence l/j.omega.C due to the capacitor C
is corresponding to the load resistor RL, the equation (4) can be modified
as the following equation (5).
##EQU4##
Now, as shown in FIG. 2B, if a voltage source having an output voltage of
V1 is further connected between the capacitor C and the ground, the
following equation (6) is obtainable.
##EQU5##
Next, as shown in FIG. 2C, when a emitter follower is constructed by a
transistor Q3, and an emitter voltage of the transistor Q3 can be given by
the following equation (7) because an input voltage and an output voltage
are equal to each other in the emitter follower.
##EQU6##
In the differential pair 1 as shown in FIG. 2B or 2C, a base input of the
transistor Q1 serves as a plus (+) input and a base input of the
transistor Q2 serves as a minus (-) input, and an output voltage is
withdrawn from the collector of the transistor Q2. Therefore, in the
example of FIG. 2C, the output voltage V0 is fed-back to the (-) input
through the emitter follower Q3.
With reference to FIG. 3, an active filter circuit 10 of this embodiment
utilizes two differential pairs 12 and 14 each having the same
configuration as that of the differential pair 1 described in FIG. 2A to
2C. An output voltage V3 of a second differential pair 14 is applied to a
(+) input of a first differential pair 12 (corresponding to the base input
of the transistor Q1 in FIG. 2C), and an output voltage V2 of the first
differential pair 12 is fed-back to a (-) input thereof (corresponding to
the base input of the transistor Q2 in FIG. 2C). Voltages V1 and V4 are
respectively applied to capacitive loads of the differential pairs 12 and
14, that is, capacitors C1 and C2. To a (+) input of the second
differential pair 14 (corresponding to the base input of the transistor Q1
in FIG. 2B), a voltage V5 is applied, and the output voltage V2 of the
first differential pair 12 is fed-back to a (-) input thereof
(corresponding to the base input of the transistor Q2 in FIG. 2B).
The active filter circuit 10 shown in FIG. 3 is specifically shown in FIG.
4. With reference to FIG. 4, the active filter circuit 10 includes the
first differential pair 12 constructed to include a first and second
transistors Q11 and Q12, and the second differential pair 14 constructed
to include a third and fourth transistors Q21 and Q22.
Emitters of the transistors Q11 and Q12 constituting the first differential
pair 12 are commonly connected to a collector of a transistor Q13
constituting the above described constant current source. A collector of
the transistor Q11 is supplied with a power source voltage (+B) from a
terminal 16. A collector of the transistor Q12 is connected to a constant
current source, that is, a collector of a transistor Q15 and a base of a
transistor Q14 constituting the above described emitter follower of the
first differential pair 12, which is also connected to a terminal 18
through the capacitor C1 constituting the capacitive load. To a base input
of the transistor Q11 constituting the (+) input of the first differential
pair 12 of FIG. 3, an output of a transistor Q24 constituting the above
described emitter follower of the second differential pair 14 is
connected, and a base input of the transistor Q12 constituting the (-)
input is connected to the output of the transistor Q14, that is, a
terminal 20. In addition, a current amount of the constant current source
constructed by the transistor Q13 is set as 2I1 that is double a current
amount I1 of the constant current source constructed by the transistor
Q15.
Emitters of the transistors Q21 and Q22 constituting the second
differential pair 14 are commonly connected to the above described
constant current source constructed by a transistor Q23 which constitutes
a current mirror circuit together with the previous transistor Q13. A
collector of the transistor Q21 is applied with the power source voltage
(+B) from the terminal 16. A collector of the transistor Q22 is connected
to a constant current source constructed by a transistor Q25 and a base of
a transistor Q24 as the emitter follower, which is also connected to a
terminal 22 through the capacitor C2 that is the capacitive load. A base
input of the transistor Q22 constituting the (-) input of the second
differential pair 14 of FIG. 3 circuit is connected to the output of the
first differential pair 12, that is, the terminal 20, and a base input of
the transistor Q21 constituting the (+) input is connected to a terminal
24. In addition, as similar to the previously described first differential
pair 12, in the second differential pair 14, a current amount of the
constant current source constructed by the transistor Q25 is set as 212
that is double a current amount I2 of the constant current source
constructed by the transistor Q25.
Transistors Q16 and Q26 are paired with each other, respective collectors
of which are supplied with the power source voltage (+B) via suitable
resistors. A collector of the transistor Q16 is connected to a base
thereof and a constant current source constructed by a transistor Q17.
Similarlily, a collector of the transistor Q26 is connected to a base
thereof and a constant current source constructed by a transistor Q27.
In addition, the transistors Q13, Q23, Q17 and Q27 constituting the above
described constant current sources are connected in parallel with each
other to construct a current mirror circuit, and the bases thereof are
commonly connected to a terminal 26. By applying a control voltage Vc to
the terminal 26, current amounts of the respective transistors are
changed, whereby a filter characteristic of this active filter circuit 10
can be adjusted or controlled.
Now, it is assumed that voltages at the terminal 18, the output of the
transistor Q14, that is, the terminal 20, the output of the transistor
Q24, the terminal 22 and the terminal 24 are respectively set as V1, V2,
V3, V4 and V5.
When the voltage V5 at the terminal 24 increases, a collector current of
the transistor Q22 decreases, and a current of the transistor Q24
increases by that decreased amount, and therefore, the output voltage V3
of the transistor Q24 increases. When the voltage V3 increases, a
collector current of the transistor Q12 decreases, and a current of the
transistor Q14 increases by that decreased amount, and therefore, the
voltage V2 at the terminal 20 increases. When the voltage V2 increases,
the decrease of the collector currents of the transistors Q12 and Q22 are
suppressed so that operations of the first and second differential pairs
12 and 14 become stable. Therefore, each of the first and second
differential pairs 12 and 14 always operates in the vicinity of a center
of a linear region thereof, and therefore, no distortion of the signals
occurs and a good filter characteristic is obtainable.
In the active filter circuit 10 shown in FIG. 4, on the assumption that the
emitter resistor of each of the transistors Q11 and Q12 is re1, current I1
flowing each of the transistors Q11 and Q12 of the first differential pair
12 is given by the following equation (8).
##EQU7##
In addition, a signal voltage of the capacitor C1 is given by the following
equation (9).
##EQU8##
Based upon the equations (8) and (9), in association with the first and
second differential pairs 12 and 14 of the active filter circuit 10 shown
in FIG. 4, the above described equation (7) is established, and therefore,
the following equations (10) and (11) are obtainable;
##EQU9##
where re2 is a differential resistor, that is, emitter resistor of each of
the transistors Q21 and Q22 of the second differential pair 14.
In accordance with the above described equations (10) and (11), if the
voltage V3 is eliminated while j.omega.=S, the following equation (12) is
obtained.
##EQU10##
Now, if the terminals 18 and 22 are connected to ground and a signal is
input to the terminal 24, V1=V4=0 and V5=Vin are obtained, and therefore,
a transfer function T.sub.(s) of the active filter circuit 10 of FIG. 4 is
given by the following equation (13).
##EQU11##
The equation (13) shows a secondary low-pass function. A cut-off frequency
.omega.c thereof is given by the following equation (14) and Q is given by
the following equation (15).
##EQU12##
Thus, the active filter circuit 10 of FIG. 4 is implemented as a secondary
lowpass filter.
Similarly, when a signal is input to the terminal 18 and the terminals 22
and 24 are connected to the ground, V1=Vin and V4=V5=0 are obtained, and
therefore, a transfer function T.sub.(s) thereof is given by the following
equation (16) which shows a secondary highpass function. Then, a cut-off
frequency .omega.c is given by the following equation (17) and Q is given
by the following equation (18).
##EQU13##
Thus, the active filter circuit 10 of FIG. 4 is implemented as a secondary
highpass filter.
In addition, if the terminals 18 and 24 are connected to ground a signal is
input to the terminal 22, V1=V5=0 and V4=Vin are obtained, and therefore,
a secondary band-pass filter having a center frequency .omega.o and Q
respectively represented by the following equations (19) and (20) is
obtainable.
##EQU14##
In addition, if a signal is simultaneously input to the terminals 18 and 24
and the terminal 22 is connected to ground, V1=V5=Vin and V4=0 are
obtained, and therefore, it is possible to obtain a secondary band
elimination filter having a center frequency .omega.o and Q respectively
represented by the following equations (21) and (22).
##EQU15##
Furthermore, if a signal is simultaneously input to the terminals 18 and 24
and a signal reversed in phase is input to the terminal 22, V1=V5=Vin and
V4=Vin are obtained, and therefore, it is possible to implement a
secondary phase-shifting circuit having a center frequency .omega.o, Q and
a phase characteristic respectively represented by the following equations
(23), (24) and (25).
##EQU16##
Thus, in accordance with FIG. 4 embodiment, different kinds of secondary
filter circuits can be implemented by the same circuit configuration.
Therefore, in a case where a plurality of different kinds of filter
circuits are incorporated within the same IC, if the control voltages Vc
to be applied to the terminals 26 of the respective filters are linked
with each other by adjusting only a single control voltage, it is possible
to adjust all the filter circuits without any fluctuations.
With reference to FIG. 5, an active filter circuit 10' of this embodiment
utilizes two differential pairs 12 and 14 each having the same
configuration as that of the differential pair 1 described in FIG. 2A to
2C | | |
