An analog line store comprises a bank of storage capacitors n in number, an n:1 read multiplexer for sequentially sampling from the n storage capacitors as part of a read-then-write operation, a 1:n write multiplexer for sequentially sampling to the n storage capacitors as a further part of the read-then-write operation, and a scanning register for generating control signals for the write multiplexer and the read multiplexer. The storage capacitors have similar capacitances that are substantially invariant with change in stored charge. Such an analog line store is integrated together with a solid-state imager array to provide for the cancellation of fixed pattern noise from the imager video output signal.
A method and apparatus are provided for canceling crosstalk noise arising on signal lines output from an image sensor. More specifically, the crosstalk noise is canceled by a current mirror that is coupled to the signal line. The current mirror adjusts the voltage level on the signal line by drawing a current therefrom that is proportional to the amount and polarity of the crosstalk noise. The amount of crosstalk noise is determined by an amount of coupling within an A/D converter coupled to the signal lines. The current mirrors can further adjust the voltage on the signal line by drawing a current therefrom that is proportional to crosstalk arising due to a voltage level on another signal line. Such a current mirror allows pixel data to be conveyed to the A/D converter, via the signal lines, without imparting aberrations due to crosstalk noise.
A photosensor signal processing apparatus is used in combination with an image sensor comprised of a matrix of pixels or photosensors capable of producing an output as a linear function and a logarithmic function of incident illumination. The apparatus includes a correction data storage device which stores therein a set of data about the respective photosensors for the correction of individual outputs of the photosensors, and a correcting device for correcting the respective output values of the photosensors on the basis of the correction data. Thus, even when the individual outputs of the photosensors generate have different characteristics, the output characteristic variation between the photosensors are corrected such that the output characteristics of all the photosensors agree with a reference output characteristic. A fixed pattern noise resulting from the pixel-to-pixel output characteristic variation can be suppressed.
Fixed pattern noise of an analog memory is reduced. Transfer paths of an address selection signal (SL) between an address generation unit (10) and respective storage elements (21) for storing an analog signal are constructed to have a substantially uniform electric characteristic in driving the storage elements (21) by the address selection signal (SL) to such an extent that the output signal of the analog memory is free from fixed pattern noise. A buffer unit (50) for temporarily storing and outputting the address selection signal is provided between the address generation unit (10) and the respective storage elements (21), and the buffer unit (50) is constructed to have an output characteristic substantially uniform between the storage elements (21). Also, lines between the buffer unit (50) and the storage elements (21) are constructed to have substantially the same electric characteristic. In this manner, charge feed through noise of the respective storage elements (21) are made substantially uniform, resulting in suppressing the fixed pattern noise.
A column amplifier for high fixed pattern noise reduction. The column amplifier includes a switching capacitor amplifier, a sample and hold stage, and an output buffer. The switching capacitor amplifier receives signals from a bit line that is coupled to a column of active pixel sensors. The switching capacitor amplifier is capacitively coupled to the bit line from a column of active pixel sensors and is able to cancel the common mode offset in the bit line. The common mode can also be adjusted in the switching capacitor amplifier, such that the last stage of the column amplifier (e.g., the buffer stage) is not limited by the common mode level of the active pixel sensors. The switching capacitor amplifier includes an input capacitor and a feedback capacitor. The gain of the switching capacitor amplifier amplifies the pixel signals so that the fixed pattern noise introduced by stages after the switching capacitor amplifier will comprise a lower proportion of the total signal.
An on-chip FPN calibration method and circuits scheme applying a reference voltage signal to an array of calibration pixels coupled to a sensor matrix. Two data values are read from each bit line and used to calculate an offset and a gain error for a pixel column. A reference offset and a reference gain error value are then generated by computing the average offset and the average gain error from the collected offset and gain error values of each bit line. Calibration data for each bit line then comprises an offset difference and a gain error difference, the offset difference comprising the difference between the offset value for that bit line and the reference offset, and the gain error difference comprising the gain error difference between the gain error for that bit line and the reference gain error. The calibration data for each bit line is then stored in on-chip volatile memory and is used later under normal operation to compensate for the FPN effect.
