A first user re-programmable interconnect architecture is provided wherein N switching elements are connected between selected interconnect conductors. The switching elements are controlled by M active storage elements, where M<N. A group of N switching elements are controlled by a group of M active storage elements, where M<N. The states of the M active storage elements are collectively decoded to identify the one of N switching elements to be turned on. A second user re-programmable interconnect architecture is provided wherein a group of N switching elements are connected between selected interconnect conductors and are partially selected by decoding the states of m.sub.1 active storage elements. The group of N switching elements are also partially selected by decoding the states of m.sub.2 active storage elements. The decoding is arranged such that t the states of m.sub.1 and m.sub.2 active storage elements each are decoded to provide a partial address to identify one of the N switching elements to be turned to its "on" state. The sum of m.sub.1 and m.sub.2 is less than N.
A memory cell section is divided into a data storage area and a data management information storage area in a column direction. The number of memory cells of each of NAND strings of the data management information storage area is smaller than that of memory cells of each of NAND strings of the data storage area. Word lines are connected in common to NAND strings arranged in the column direction in the data storage area, and two of them extend to be connected in common to the NAND strings arranged in the column direction in the data management information storage area. Bit lines are connected in common to the NAND strings arranged in the row direction.
A field programmable interconnect device (FPID) selectively routes signals between signal ports in response to commands from a host controller. Each command includes an address and data. The FPID includes an array of switch cells, each interconnecting a separate pair of the ports and each having first and second control signal inputs. When the first and second control signals are both asserted, the switch cell provides a signal path between the pair of the ports it interconnects. The FPID includes first and second sets of memory cells for storing data. Each first memory cell corresponds to a separate one of the switch cells and selectively asserts or deasserts the first control signal input to the corresponding switch cell according to its stored data. Each second memory cell corresponds to a separate group of switch cells and selectively asserts or deasserts the second control signal input to each switch cell of the corresponding group according to its stored data. The FPID further includes a memory controller for receiving each command from the host controller and for writing data included in the command into each memory cell of a particular subset of the first and second memory cells upon receipt of the command. The address included in the command indicates the particular subset into which the controller is to write the data. The number of memory cells included in the particular subset is a variable function of the address.
A programmable high speed routing switch is provided which has a lower ON-resistance so as to increase its gate oxide reliability. The routing switch includes a non-volatile memory cell (12) having a floating gate (FG). The floating gate is selectively charged and discharged to provide either a net positive potential or a net negative potential. The routing switch also includes a memory transistor (14), a pass gate transistor (16), and a poly load element (18). The source of the memory transistor is connected to a first power supply potential. The gate of the memory transistor is connected to the floating gate of the memory cell, and the drain thereof is connected to the gate of the pass gate transistor and to a first end of the poly load element. The drain of the pass gate transistor is connected to a first signal line (PG1) and the source of the pass gate transistor is connected to a second signal line (PG2). The second end of the poly load element is connected to a second power supply potential.
A pin-configurable frequency synthesizer for providing a choice of physical pin assignments/configurations without costly design and/or bonding changes. A functional block, having a plurality of functional conductors, is provided. The pin-configurable frequency synthesizer is housed in a chip package that includes a plurality of physical pins. A configuration matrix having a plurality of transmission circuits for connecting the functional conductors to the physical pins is also provided. A control circuit for controlling the transmission circuits of the configuration matrix is further provided. This control circuit includes programming logic and a logic array for generating control signals for each of the transmission circuits of the configuration matrix. These control signals direct the transmission circuits to selectively couple each functional conductor to a respective physical pin in accordance with a desired pin assignment. A user uses the programming logic to program the logic array in accordance with the desired pin assignment.
A user-programmable interconnect architecture, which may be used for logic arrays for digital and analog system design, is disclosed. In one embodiment, a plurality of logic cells or modules in a matrix are connected by vertical and horizontal wiring channels. The wiring channels may in turn be programmed by the user to interconnect the various logic cells to implement the required logic function. The wiring channels comprise wiring segments connected by normally open programmable. Elements situated at the intersection of any two segments to be connected.
