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Integrated circuit I/O using high performance bus interface    
United States Patent5319755   
Link to this pagehttp://www.wikipatents.com/5319755.html
Inventor(s)Farmwald; Michael (Berkeley, CA); Horowitz; Mark (Palo Alto, CA)
AbstractAn apparatus for storing and retrieving data is described. The apparatus includes a circuitry for initiating data transmission, a first memory, a second memory, and a multiline bus for transferring control information, addresses, and the data. The control information includes information for selecting one of the first and second memories without using any separate memory select line. Configuration circuitry is provided for assigning a first identification value to the first memory and a second identification value to the second memory. The configuration circuitry includes a first reset line for coupling the circuitry for initiating data transmission to the first memory, a second reset line for coupling the first memory to the second memory, a first identification register for the first memory, a second identification register for the second memory, circuitry for generating a first reset signal and a second reset signal and for sending the first and second reset signals to the first identification register, circuitry for propagating the first and second reset signals from the first identification register to the second identification register, circuitry for resetting the first and second identification registers in response to the first reset signal, and circuitry for setting the first identification register to the first identification value and the second identification register to the second identification value in response to the second reset signal.
   














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Drawing from US Patent 5319755
Integrated circuit I/O using high performance bus interface - US Patent 5319755 Drawing
Integrated circuit I/O using high performance bus interface
Inventor     Farmwald; Michael (Berkeley, CA); Horowitz; Mark (Palo Alto, CA)
Owner/Assignee     Rambus, Inc. (Mountain View, CA)
Patent assignment
All assignments
Publication Date     June 7, 1994
Application Number     07/954,945
PAIR File History     Application Data   Transaction History
Image File Wrapper   Patent Term   Fees
Litigation
Filing Date     September 30, 1992
US Classification     710/104
Int'l Classification     G06F 013/00
Examiner     Fleming; Michael R.
Assistant Examiner     Auve; Glenn A.
Attorney/Law Firm     Blakely, Sokoloff, Taylor & Zafman
Address
Parent Case     This is a continuation of application Ser. No. 07/510,898, filed Apr. 18, 1990, now abandoned.
Priority Data    
USPTO Field of Search     395/325 395/425 395/725 364/240.3 364/240.1 364/243 364/DIG. 1 364/935.47 364/940.2 364/964 364/DIG. 2
Patent Tags     integrated circuit i/o high performance bus interface
   
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Market Size
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$5B - $10B
$2B - $5B
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Market Share
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2 - 4.99%
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