A processor apparatus for use in a multiprocessor computer system having a main memory storing a plurality of data items and being coupled to a bus operating according of a SNOOPY protocol. The processor apparatus includes a processor, a primary cache, a backup cache and a bus interface. The backup cache memory a first TAG store comprising a plurality of VALID indicators, one VALID indicator for each of the data items currently contained in the backup cache memory. The primary cache memory includes a second TAG store comprising a plurality of address indicators and a plurality of VALID indicators, one address indicator and one VALID indicator for each of the data items currently contained in the primary cache memory. The interface includes a duplicate TAG store coupled to the primary cache memory, the duplicate TAG store consisting of a copy of the address indicators of the second TAG store. The bus interface is coupled to the processor, the backup cache memory and to the bus. The bus interface operates in accordance with a SNOOPY protocol to monitor transactions on the bus for write transactions affecting data items in the corresponding backup cache memory having set VALID indicators. The bus interface will invalidate or update each VALID data item of the backup cache memory when there is a write transaction affecting data item and assert an invalidate signal for an affected data item indicated by the address indicators of the duplicate TAG store. The invalidate signal causes the VALID indicator in the second TAG store for the affected data item to be cleared.
A cache memory system includes a cache memory having a plurality of entries associated with a plurality of information storage units. Each of the information storage units is configured to store part of the information stored in a main memory. Reference bit storage units store a use status of entry data for a certain period of time. A hit detection circuit is connected to the information storage units. The hit detection circuit generates a hit signal to each of the reference bit storage units when the entry data is determined to satisfy use conditions.
A write-back coherency system, including FLUSH/INVAL and LOCK protocols, is used, in an exemplary embodiment, in a microprocessor used in a computer system that selectively provides to the processor FLUSH and INVAL signals to implement a limited write-back protocol. The FLUSH/INVAL protocol is used by the computer system to control export and invalidate operations. In response to a FLUSH signal, the microprocessor exports dirty data from the cache. If INVAL is also asserted, the cache is also invalidated (i.e., if FLUSH is asserted and INVAL is not asserted, no invalidation is performed). With the LOCK protocol, LOCKed reads are serviced out of the cache for read hits--however, to maintain compatibility with computer systems that expect a LOCK operation to involve a read followed by a write access to external memory, the microprocessor will still run the external LOCKed read cycle, ignoring the returned data.
According to this invention, a dual-memory managing apparatus is applied to a system in which a plurality of memories and a plurality of processors are connected to each other through a data bus, and the dual-memory managing apparatus is a dual-memory managing apparatus for performing control performed when a memory copy operation from at least one first memory to at least one second memory system. The dual-memory managing apparatus includes a means for performing the memory copy operation for each word, and when write access from the plurality of processors to the plurality of memories is performed at almost the same timing as that of the memory copy operation, a control means for parallelly performing the memory write access and the memory copy operation when an address of the write access is different from an address subjected to the memory copy operation, and for preferentially performing the write access when the address of the write access is identical to the address subjected to the memory copy operation.
A multiprocessor computer architecture containing processor caches that are kept coherent, and in particular, a duplicate cache tag subsystem and method for maintaining duplicate cache tags, are disclosed. The tag width of duplicate cache tags for a processor cache is tailored to available integrated circuit surface area, or to device pin count, without significantly sacrificing system performance. Such partial duplicate tag width may also be reduced at any time during the integrated circuit design phase, should the available integrated circuit surface area or pin-availability decrease. The method disclosed involves requesting data from memory; reading a partial duplicate cache tag list to determine if there is a partial hit; taking the data from the memory if there is no match between a requested address and the partial duplicate cache tag list; holding the data in memory or a requestor module if there is a match between the requested address and the partial duplicate cache tag list; and interrupting processor operation to confirm that the partial duplicate cache tag corresponds to an actual cache tag. The data are taken from the cache if the partial duplicate cache tag matches the actual cache tag and cache status indicates that the data have been modified. The data are taken from memory if the partial duplicate cache tag does not match the actual cache tag or cache status indicates that the data have not been modified.
A memory circuit that allows for short retransmit recovery times by implementing a read cache memory in a FIFO device. A circuit comprising a memory array, a cache memory and a logic circuit. The memory array includes a read pointer, a write pointer and a plurality of memory rows. The cache memory is configured to store one or more memory data bits. The logic circuit is further configured to control the output of the circuit by presenting either (i) an output from the memory array or (ii) an output from the cache memory.
