 |
Description  |
|
|
REFERENCE TO RELATED APPLICATION
The present invention is related to U.S. patent application Ser. No.
07/937,064, filed on Aug. 27, 1992 and entitled DISK DRIVE USING PRML
CLASS IV SAMPLING DATA DETECTION WITH DIGITAL ADAPTIVE EQUALIZATION, the
disclosure of which is hereby incorporated herein by reference.
FIELD OF THE INVENTION
The present invention relates to methods and apparatus for asynchronous
peak detection of information embedded within a partial response, class
IV, maximum likelihood (hereinafter referred to as "PR4,ML") synchronous
detection data channel. More particularly, the present invention relates
to asynchronous peak detection of embedded servo and sync field
information within a data stream of a PR4,ML data channel of a high
performance magnetic disk data storage subsystem.
BACKGROUND OF THE INVENTION
Conventional disk drives have employed peak detection techniques in order
to recover digital data written as saturation recording onto a
magnetizable surface media of a rotating disk. With peak detection
techniques, it is necessary to space flux transitions sufficiently apart
so that analog peaks in the recovered data stream may be identified and
the corresponding data recovered. In order to achieve reasonable
bandwidths in data channels, it has been customary to employ data coding
techniques. One such technique has been to use a (1,7) RLL code. In this
code, flux transitions can be no closer together than every other clock
bit time period ("bit cell") nor farther apart than eight clock bit cells.
(1,7) RLL codes are known as "rate two-thirds" codes, in the sense that
two data bits are coded into three code bits. Thus, with a rate two-thirds
code, one third of the user storage area of the storage disk is required
for code overhead.
One way to decrease the code overhead is to employ a code in which flux
transitions are permitted in adjacent bit cells. One such code is a
(0,4,4) code. The (0,4,4) code can be implemented as a rate eight-ninths
code, meaning that nine code bits are required for eight incoming data
bits. (Theoretically, the (0,4,4) code ratio is somewhat higher,
approaching 0.961.) Thus, this code is significantly more efficient than a
rate two-thirds code, such as (1,7) RLL. Use of a (0,4,4) code results in
a significantly greater net user data storage capacity on the disk
surface, given a constant bit cell rate. However, when flux transitions
occur in adjacent bit cells, as is the case with a (0,4,4) code,
intersymbol interference ("ISI") results. Conventional peak detection
techniques are not effective or reliable in recovering data coded in an
eight-ninths code format, such as (0,4,4).
The zero in the (0,4,4) code denotes that flux transitions may occur in
directly adjacent bit cells of the coded serial data stream. The first "4"
denotes that a span of no more than four zeros occurs between ones in the
encoder output. The second "4" signifies that the bit cell stream has been
divided into two interleaves: an even interleave, and an odd interleave;
and, it denotes that there can be a span of no more than four zeros
between ones in the encoder output of either the odd interleave or the
even interleave.
It is known that partial response signalling enables improved handling of
ISI and allows more efficient use of the bandwidth of a given channel.
Since the nature of ISI is known in these systems, it may be taken into
account in the decoding/detection process. Partial response transmission
of data lends itself to synchronous sampling and provides an elegant
compromise between error probability and the available spectrum. The
partial response systems described by the polynomials 1+D, 1-D, and
1-D.sup.2 are known as duobinary, dicode and class IV (or "PR4"),
respectively, where D represents one bit cell delay and D.sup.2 represents
2 bit cell delays (and further where D=e.sup.-j.omega.T, where .omega. is
a frequency variable in radians per second and T is the sampling time
interval in seconds). The PR4 magnitude response plotted in FIG. 1 hereof
and given the notation .vertline.1-D.sup.2 .vertline. emphasizes midband
frequencies and results in a read channel with increased immunity to noise
and distortion at both low and high frequencies. In magnetic recording PR4
is a presently preferred partial response system, since there is a close
correlation between the idealized PR4 spectrum as graphed in FIG. 1, and
the natural characteristics of a magnetic data write/read channel.
In order to detect user data from a stream of coded data, not only must the
channel be shaped to a desired partial response characteristic, such as
the PR4 characteristic, but also a maximum likelihood ("ML") sequence
estimation technique is needed. The maximum likelihood sequence estimation
technique determines the data based upon an analysis of a number of
consecutive data samples taken from the coded serial data stream, and not
just one peak point as was the case with the prior peak detection methods.
One maximum likelihood sequence estimation algorithm is known as the
Viterbi detection algorithm, and it is well described in the technical
literature. Application of the Viterbi algorithm to PR4 data streams
within a magnetic recording channel is known to improve detection of
original symbol sequences in the presence of ISI and also to improve
signal to noise ratio over comparable peak detection techniques.
In an article entitled "Viterbi Detection of Class IV Partial Response on a
Magnetic Recording Channel" appearing in IEEE Trans. on Communications,
vol. Com-34, No. 5, May 1986, pp. 434-461, authors Wood and Peterson
explain the derivation of PR4 as being formed by subtracting waveforms two
bit intervals apart, thereby forming an analog domain ternary "eye"
pattern graphed herein in FIG. 2.
The Viterbi algorithm provides an iterative method of determining the
"best" route along the branches of a trellis diagram, such as the one
shown in FIG. 3 hereof, for example. If, for each trellis branch, a metric
is calculated which corresponds to the logarithm of the probability for
that branch, then the Viterbi algorithm may be employed to determine the
path along the trellis which accumulates the highest log probability,
i.e., the "maximum likelihood" sequence. Since the Viterbi algorithm
operates upon a sequence of discrete samples {y.sub.k }, the read signal
is necessarily filtered, sampled, and equalized.
While PRML has been employed in communications signalling for many years,
it has only recently been applied commercially within magnetic hard disk
drives. One recent application is described in a paper by Schmerbeck,
Richetta, and Smith, entitled "A 27 MHz Mixed Analog/Digital Magnetic
Recording Channel DSP Using Partial Response Signalling with Maximum
Likelihood Detection", Proc. 1991 IEEE International Solid State Circuits
Conference, pp. 136-137, 304, and pp. 96, 97 and 265 Slide Supplement.
While the design reported by Schmerbeck et al. appears to have worked
satisfactorily, it has drawbacks and limitations which are overcome by the
present invention. One drawback of the reported approach was its design
for transducers of the ferrite MiG type or of the magnetoresistive type
which simplified channel equalization requirements. Another drawback was
the use of a single data transfer rate which significantly simplified
channel architecture. A further drawback was the use of a dedicated servo
surface for head positioning within the disk drive, thereby freeing the
PR4, ML data channel from any need for handling of embedded servo
information or for rapid resynchronization to the coded data stream
following each embedded servo sector.
Prior Viterbi detector architectures and approaches applicable to
processing of data sample sequences taken from a communications channel or
form a recording device are also described in the Dolivo et al. U.S. Pat.
No. 4,644,564. U.S. Pat. No. 4,504,872 to Peterson describes a digital
maximum likelihood detector for class IV partial response signalling. An
article by Roger W. Wood and David A. Peterson, entitled: "Viterbi
Detection of Class IV Partial Response on a Magnetic Recording Channel"
IEEE Trans. on Comm. Vol. Com-34, No. 5, May 1986, pp. 454-466 describes
application of Viterbi detection techniques to a class IV partial response
in a magnetic recording channel. An article by Roger Wood, Steve Ahigrim,
Kurt Hallarnasek and Roger Stenerson entitled: "An Experimental Eight-Inch
Disc Drive with One-Hundred Megabytes per Surface", IEEE Trans. on
Magnetics, Vol. Mag-20, No. 5, September 1984, pp 698-702 describes
application of class IV partial response encoding and Viterbi detection
techniques as applied within an experimental disk drive. A digital Viterbi
detector capable of withstanding lower signal to noise ratios is described
in Matsushita et al. U.S. Pat. No. 4,847,871. These documents are
representative examples of the known state of the prior art.
When zoned data recording techniques, embedded servo sectors, and e.g.
thin-film heads are employed in a high performance, very high capacity,
low servo overhead disk drive, the prior approaches are not adequate, and
a hitherto unsolved need has arisen for an approach incorporating PR4,ML
techniques into a high capacity, high performance, low cost disk drive
architecture including architectural features such as e.g. thin-film
heads, embedded sector servo based head positioning, and
zone-data-recording techniques.
In particular, a hitherto unsolved need has arisen for an efficient,
effective way to detect the embedded sector servo identification
information which is asynchronous with the coded user data. Ordinarily, in
a conventional peak detection channel, the embedded servo sector
identification field is detected by the analog peak detector. In a
sampling detection system, such as PR4,ML, an analog peak detector is not
present, because the data samples are processed digitally.
In addition, before the data samples are valid, it is necessary to
establish the beginning of a data field. Typically, the beginning of a
data field, or field segment within a split data field pattern, is marked
with a sync pattern. Since in a detector that uses a digital adaptive
equalizer such as a FIR filter, the equalizer may not be optimized (e.g.
before training or adaptation thereof is complete) when reading the sync
pattern, robust detection of the sync pattern without using the equalizer
is required.
In disk drives using embedded servo sectors, the effective bandwidth of the
data fields is much greater than the effective bandwidth of the embedded
servo fields. Therefore, if the same analog low pass filter is used alone
for both the data fields and the embedded servo fields, very noisy signals
may result while reading the servo field, particularly if the analog low
pass filter is adapted to the PR4,ML spectrum, FIG. 1, and zoned data
recording techniques are used. Thus, a hitherto unsolved need has remained
for effective asynchronous detection of embedded information, such as
servo position information, within a PR4,ML synchronous detection data
channel.
SUMMARY OF THE INVENTION
A general object of the present invention is to provide an improved,
efficient method and enabling apparatus for detecting asynchronously servo
and sync information within a data stream of disk drive read channel
employing PRML techniques, embedded servo sectors, and zoned data
recording techniques in a manner overcoming limitations and drawbacks of
the prior art.
One more object of the present invention is to provide an improved,
efficient method and enabling apparatus for detecting asynchronously servo
and sync information which makes effective use of an adaptive equalizer
including a digital finite impulse response ("FIR") filter of a PR4, ML
disk drive data channel and which is programmable "on-the-fly" for
asynchronous detection of the servo and sync information embedded within,
and periodically interrupting the coded data stream.
Yet one more object of the present invention is to provide a filter
coefficient adaptation circuit for programming an FIR filter within a PR4,
ML disk drive data channel which lends itself to programmability for
asynchronous detection of embedded servo and sync information as well as
for continuous adaptation to various data channel characteristics to
facilitate synchronous, maximum likelihood detection of coded user data
samples.
A related object of the present invention is to provide a digital FIR
filter and a digital filter coefficient adaptation circuit for adapting
the digital FIR filter to a desired particular response of a PR4,ML disk
drive data channel, including the ability to load a preprogrammed filter
setting, or settings, for detecting embedded servo and sync information.
Another object of the present invention is to provide a method for using a
PR4, ML data channel in an asynchronous mode in order to recover head
position servo information within servo sectors embedded within concentric
data tracks of a disk drive wherein the servo information is recorded at a
different frequency and phase than the coded user data elsewhere recorded
in the data track.
Another object of the present invention is to provide a digital peak
detector for asynchronous detection of servo information and/or sync
pattern information embedded in a data track of a disk drive employing a
PR4, ML data channel.
One more object of the present invention is to provide a data ID field sync
pattern detection method with improved fault tolerance within a PR4,ML
disk drive data channel.
In accordance with principles of the present invention, a digital peak
detection circuit asynchronously detects embedded overhead information
within a PR4,ML synchronous data detection channel of a magnetic disk
drive. The channel includes an analog to digital converter clocked by a
data clock operating asynchronously with respect to playback of the
embedded overhead information in the channel for converting an analog data
stream into raw data samples, and an adaptive digital FIR filter for
conditioning the raw data samples into conditioned data samples in
accordance with programmable filter coefficients. The digital peak
detection circuit includes:
a filter adaptation circuit for programming the digital FIR filter to a
bandwidth characteristic selected for the embedded overhead information,
a plurality of tapped clock delays each connected in tandem to receive and
progressively by a period related to said data clock to delay conditioned
data samples of the embedded overhead information,
a first comparison logic array connected to predetermined taps of said
tapped data clock period delays for comparing said conditioned data
samples of the embedded overhead information at said taps and for
generating a first logical condition therefrom,
a second comparison logic array connected to a predetermined tap of said
tapped clock delay means and to a threshold-providing circuit for
comparing the conditioned data samples of the embedded overhead
information at the taps with threshold values provided by the
threshold-providing circuit and for generating a second logical condition
therefrom, and
a digital combining circuit for combining the first logical condition and
the second logical condition in order to detect and put out the embedded
overhead information.
In one aspect of the invention, the data detection channel further
comprises a programmable analog filter-equalizer upstream of the analog to
digital converter, and programming circuitry for programming the analog
filter-equalizer to a bandwidth characteristic selected for the embedded
overhead information.
In another aspect of the invention, the plurality of tapped clock delays
comprises three single clock period delay circuits connected in tandem,
the predetermined taps provide y.sub.k, y.sub.k-1 and y.sub.k-2 data
samples, and the embedded overhead information comprises embedded servo
information.
In a further aspect of the invention, the plurality of tapped clock delays
comprises five single clock period delay circuits connected in tandem, the
predetermined taps provide y.sub.k, y.sub.k-2 and y.sub.k-4 data samples,
and the embedded overhead information comprises user data field sync
pattern information in the form of a single magnetic flux transition
signal located generally in the middle of a predetermined interval of
non-transition in the write-current input waveform.
In yet another aspect of the invention, the first comparison logic array
determines the first logical condition as a flux transition (logic one
value) being present if one of the following is true: y.sub.k-1
.gtoreq.y.sub.k and y.sub.k-1 >y.sub.k-2, or y.sub.k-1 .ltoreq.y.sub.k and
y.sub.k-1 <y.sub.k-2 ; and otherwise no flux transition (a logical zero
value) being present.
In one more aspect of the invention the second comparison logic array is
connected to a tap providing a y.sub.k-1 data sample and determines the
second logical condition as a flux transition (logical one value) being
present if an absolute value of the y.sub.k-1 data sample is greater than
or equal to the threshold value, and otherwise no flux transition (a
logical zero value) being present.
In still one more aspect of the invention the first comparison logic array
determines the first logical condition as a flux transition (logical one
value) being present if y.sub.k-1 .gtoreq.y.sub.k and y.sub.k-1
>y.sub.k-2, and otherwise no flux transition (a logical zero value) being
present; the second comparison logic array is connected to a tap providing
a y.sub.k-1 data sample and determines the second logical condition as a
flux transition (logical one value) being present if an absolute value of
the y.sub.k-1 data sample is greater than or equal to a the threshold
value, and otherwise no flux transition (a logical zero value) being
present; and, the digital combining circuit comprises an AND gate for
ANDing the first logical condition and the second logical condition.
As one more aspect of the invention, a data field sync pattern detection
circuit is connected to receive and detect the user data field sync
pattern information and the first comparison logic circuit determines the
first logical condition as a flux transition (logical one value) being
present if one of the following is true: y.sub.k-2 .gtoreq.y.sub.k and
y.sub.k-2 >y.sub.k-4 or y.sub.k-2 .ltoreq.y.sub.k and y.sub.k-2
<y.sub.k-4. As an associated aspect of the invention, the second
comparison logic circuit is connected to a tap providing a y.sub.k-2 data
sample and determines the second logical condition as a flux transition
(logical one value) being present if an absolute value of the y.sub.k-2
data sample is greater than or equal to a set threshold value, and
otherwise determines that no flux transition (a logical zero value) is
present.
As a further related aspect of the invention, the data field sync pattern
detection circuit comprises a series of tapped clock delays, each being
connected in tandem to receive and to delay progressively by a period
related to the data clock data samples comprising data field sync pattern.
A sync pattern logic array is connected to taps along the series of delays
for detecting a predetermined sequence of the data samples comprising a
valid user data field sync pattern information. In a further related
aspect, the data field sync pattern detection circuit is fault-tolerant
within plus or minus one clock period in detecting as valid the user data
field sync pattern information.
As one more aspect of the present invention, embedded overhead information
comprises embedded servo information and embedded sync pattern information
and the predetermined taps provide y.sub.k, y.sub.k-1, y.sub.k-2,
y.sub.k-3 and y.sub.k-4 data samples; and selection circuitry responsive
to a servo field/sync field control signal selects between y.sub.k,
y.sub.k-1 and y.sub.k-2 data samples for servo detection, and y.sub.k,
y.sub.k-2 and y.sub.k-4 data samples for sync detection.
These and other objects, advantages, aspects and features of the present
invention will be more fully understood and appreciated upon consideration
of the following detailed description of a preferred embodiment, presented
in conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
In the drawings:
FIG. 1 is a graph of an idealized PR4 channel magnitude response spectrum.
FIG. 2 is an exemplary ternary or "eye" diagram illustrating detection of
signal levels in a PR4 channel.
FIG. 3 is a trellis diagram employed by a Viterbi detector in detecting a
maximum likelihood data sequence occurring within one interleave of a PR4
data stream.
FIG. 4 is a simplified overall system block diagram of a disk drive
including a PR4, ML write/read channel architecture incorporating
principles and aspects of the present invention.
FIG. 5 is a simplified diagram of a recording pattern formed on a data
storage surface of the FIG. 4 disk drive, illustrating data zones and
embedded servo sector patterns.
FIG. 6 is an enlarged lineal depiction of a segment of one data track
within the multiplicity of data tracks defined within the FIG. 5 data
layout plan, illustrating one data field which has been split into
segments by regularly occurring embedded servo sectors.
FIG. 7 is a detailed block diagram of a programmable analog
filter/equalizer circuit within the FIG. 4 disk drive architecture.
FIG. 8 is a detailed block diagram of a nine-tap programmable digital FIR
filter of the FIG. 4 disk drive architecture in accordance with aspects of
the present invention.
FIG. 9 is a block diagram of an FIR filter coefficient adaptation circuit
for adapting the FIG. 8 FIR filter to read channel conditions within the
FIG. 4 disk drive architecture.
FIG. 10 is a detailed block diagram of a portion of the filter coefficient
adaptation circuit block shown in FIG. 9.
FIG. 11 is a detailed block diagram of one of nine processing circuits
within the FIG. 10 filter coefficient adaptation circuit block.
FIG. 12 is a block diagram of a coefficients multiplexer array used
selectively to provide coefficient values to the FIG. 8 FIR filter.
FIG. 13 is a more detailed block diagram of a data ring circuit block shown
in FIG. 9.
FIG. 14 is an overview block diagram of a portion of the FIG. 4 PR4,ML disk
drive architecture relating to detection and decoding of embedded servo
information within the FIG. 5 data surface recording plan, in accordance
with aspects of the present invention.
FIG. 15 is a waveform graph illustrating asynchronous sampled data
detection of embedded servo track/block identification information within
embedded servo sectors of the FIG. 5 data surface recording plan.
FIG. 16 is a detailed block diagram of the servo/sync digital peak detector
included within the FIG. 40 servo circuit block diagram.
FIG. 17A is a waveform graph of an analog data stream including a sync
pattern in accordance with aspects of the present invention. FIG. 17B is
an idealized data quantization obtained from the FIG. 17A analog signal
pattern.
FIG. 18 is a table illustrating fault tolerance in detection of the FIG.
17A sync pattern in accordance with aspects of the present invention.
FIG. 19 is a detailed block diagram of logic circuitry implementing the
FIG. 18 fault tolerance detection patterns for the FIG. 17 sync pattern.
In the electrical block diagrams briefly described above, various vertical
boxes containing hatching sometimes appear. In some but not all instances,
these boxes are described in the following text. In all cases, these boxes
represent clock cycle delay registers. Thus, by counting the number of
vertical hatched boxes within a particular block or path, the reader will
determine the number of clock cycle delays.
SYSTEM OVERVIEW
With reference to FIG. 4, an exemplary high performance, high data
capacity, low cost disk drive 10 incorporating a programmable and adaptive
PR4,ML write/read channel in accordance with the principles of the present
invention includes e.g. a head and disk assembly ("HDA") 12 and at least
one electronics circuit board (PCB) 14. The HDA 12 may follow a wide
variety of embodiments and sizes. One example of a suitable HDA is given
in commonly assigned U.S. Pat. No. 5,027,241. Another suitable HDA is
described in commonly assigned U.S. Pat. No. 4,669,004. Yet another
suitable HDA is described in commonly assigned U.S. Pat. No. 5,084,791.
Yet another HDA arrangement is illustrated in commonly assigned, copending
U.S. patent application Ser. No. 07/881,678, filed on May 12, 1992, and
entitled "Hard Disk Drive Architecture". The disclosures of these patents
and this application are incorporated herein by reference thereto.
The electronics PCB 14 physically supports and electrically connects the
circuitry for an intelligent interface disk drive subsystem, such as the
drive 10. The electronics circuitry contained on the PCB 14 includes an
analog PR4, ML read/write channel application-specific integrated circuit
(ASIC) 15, a digital PR4, ML read/write channel ASIC 17, a data sequencer
and cache buffer controller 19, a cache buffer memory array 21, a high
level interface controller 23 implementing a bus level interface
structure, such as SCSI II target, for communications over a bus 25 with a
SCSI II host initiator adapter within a host computing machine (not
shown). A micro-controller 56 includes a micro-bus control structure 55
for controlling operations of the sequencer 19, interface 23, a servo loop
24, a spindle motor controller 27, a programmable analog filter/equalizer
40, adaptive FIR filter 48, Viterbi detector 50, and a digital timing
control 54 as well as a digital gain control 64. The micro-controller 56
is provided with direct access to the DRAM memory 21 via the
sequencer/memory controller 19 and may also include on-board and outboard
read only program memory, as may be required or desired.
The printed circuit board 14 also carries circuitry related to the head
positioner servo 24 including e.g. a separate microprogrammed digital
signal processor (DSP) for controlling head position based upon detected
actual head position information supplied by a servo peak detection
portion of the PR4,ML read channel and desired head position supplied by
the microcontroller 56. The spindle motor control circuitry 27 is provided
for controlling the disk spindle motor 18 which rotates the disk or disks
16 at a desired angular velocity.
The HDA 12 includes at least one data storage disk 16. The disk 16 is
rotated at a predetermined constant angular velocity by a speed-regulated
spindle motor 18 controlled by spindle motor control/driver circuitry 27.
An e.g. in-line data transducer head stack assembly 20 is positioned e.g.
by a rotary voice coil actuator 22 which is controlled by the head
position servo loop circuitry 24. As is conventional, a data transducer
head 26 of the head stack assembly 20 is associated in a "flying"
relationship over a disk surface of each disk 16. The head stack assembly
20 thus positions e.g. thin film data transducer heads 26 relative to
selected ones of a multiplicity of concentric data storage tracks 71
defined on each storage surface of the rotating disk 16. While thin film
heads are presently preferred, improvements in disk drive performance are
also realized when other types of heads are employed in the disclosed PR4,
ML data channel, such as MiG heads or magneto-resistive heads, for
example.
The heads 16 are positioned in unison with each movement of the actuator
and head stack assembly 20, and the resulting vertically aligned, circular
data track locations are frequently referred to as "cylinders" in the disk
drive art. The storage disk may be an aluminum alloy or glass disk which
has been e.g. sputter-deposited with a suitable multi-layer magnetic thin
film and a protecting carbon overcoat in conventional fashion, for
example. Other disks and magnetic media may be employed, including plated
media and or spin-coated oxide media, as has been conventional in drives
having lower data storage capacities and prime costs.
A head select/read channel preamplifier 28 is preferably included within
the HDA 12 in close proximity to the thin film heads 26 to reduce noise
pickup. As is conventional, the preamplifier 28 is preferably mounted to,
and connected by, a thin flexible plastic printed circuit substrate. A
portion of the flexible plastic substrate extends exteriorly of the HDA 12
to provide electrical signal connections with the circuitry carried on the
PCB 14. Alternatively, and equally preferably, the preamplifier 28 may be
connected to the other circuitry illustrated in FIG. 4 exteriorly of the
HDA 12 in an arrangement as described in the referenced copending U.S.
patent application Ser. No. 07/881,678, filed on May 12, 1992, and
entitled "Hard Disk Drive Architecture".
A bidirectional user data path 30 connects the digital integrated circuit
17 with the data sequencer and memory controller 19. The data path 30 from
the sequencer 19 enters an encoder/decoder ("ENDEC") 32 which also
functions as a serializer/deserializer ("SERDES"). In this preferred
embodiment, the ENDEC 32 converts the binary digital byte stream into
coded data sequences in accordance with a predetermined data coding
format, such as (0,4,4) code. This co | | |
