Multi-channel echo canceler - Patent Review 5323459

What is claimed is:

1. In a conversation system including one or more speech sources, a plurality of loudspeakers and a plurality of microphones, a multi-channel echo canceler for canceling echoes generated as a result of propagation of plurality of received signals along a spatial acoustic path from said loudspeaker to said microphones from plurality of mixed signals in one-to-one correspondence to said microphones containing speech source signals and echoes inputted through said microphones, said multi-channel echo canceler comprising a delay time difference estimation circuit for receiving said plurality of received signals as input signals and estimating a set of a plurality of delay time differences corresponding to respective signal sets of each of two signals selected from said received signals, a received signal selection circuit for outputting a designation signal designating a shortest-delay-time one of said plurality of received signals, a first selector for selecting said shortest-delay-time one of said plurality of received signals according to said designation signal, a filter coefficient set selection circuit for selecting a set of filter coefficients among a plurality of preliminarily prepared sets of filter coefficients on the basis of a predetermined first algorithm according to the result of estimation in said delay time difference estimation circuit, a cross-correlation function value estimation circuit for estimating a plurality of cross-correlation values between two received signals among said plurality of received signals, a second selector for selecting, among said estimated cross-correlation function values, a cross-correlation function value corresponding to the delay time difference between said two received signals, an absolute value calculation circuit for calculating the absolute value of said selected cross-correlation function value, a power level estimation circuit for estimating the average power level of said two received signals, a normalization circuit for normalizing said absolute value of said selected cross-correlation function value with said estimated average power level of the received signals, a coefficient updating control circuit for outputting updating information about the updating of said selected set of filter coefficients according to the result of said normalization and said power level estimation, a plurality of adaptive filters in one-to-one correspondence to said mixed signals each for receiving said shortest-delay-time received signal selected by said first selector as the input and producing an echo replica corresponding to the echoes contained in said mixed signal and minimizing the difference between said mixed signal and said echo replica according to said updating information, a plurality of subtracters in one-to-one correspondence to said mixed signals each for outputting as output signal the result of subtraction of said echo replica corresponding to the echoes contained in the same mixed signal from said mixed signal.

2. The multi-channel echo canceler according to claim 1, wherein said coefficient set updating control circuit outputs one signal indicative of "updating" of said set of filter coefficients as said updating information if said normalization result is in a predetermined range, and outputs another signal indicative of "non-updating" of said set of filter coefficients as said updating information if said normalization result is not in said range, said adaptive filters each updates the set of filter coefficients selected by said filter coefficient set selection circuit such as to minimize the level of the corresponding output signal if said filter coefficient updating information is indicative of "updating".

3. The multi-channel echo canceler according to claim 1, wherein said coefficient set updating control circuit outputs one signal indicative of "updating" of said set of filter coefficients as said updating information if said normalization result is in a predetermined range and also if the estimated power level from said power level estimation circuit is higher than a predetermined threshold level, and outputs another signal indicative of "non-updating" of said set of filter coefficients as said updating information if said normalization result is not in the predetermined range or if the estimated power level is not higher than the predetermined threshold level, said adaptive filters each updates the set of filter coefficients selected by said filter coefficient set selection circuit such as to minimize the level of the corresponding output signal if said filter coefficient updating information is indicative of "updating".

4. The multi-channel echo canceler according to claim 1, wherein said coefficient set updating control circuit outputs a step size as said updating information indicative of the extent of one updating of the set of coefficients on the basis of a predetermined algorithm according to said normalization result, said adaptive filters each updates the set of filter coefficients selected by said filter coefficient set selection circuit according to the step size indicated by said updating information such as to minimize the level of the corresponding output signal.

5. The multi-channel echo canceler according to claim 1, wherein said coefficient set updating control circuit outputs a step size as said updating information indicative of the extent of one updating of the set of coefficients on the basis of a predetermined algorithm according to said normalization result from said normalization circuit and said estimated power level from said power level estimation circuit, said adaptive filters each updates the set of filter coefficients selected by said filter coefficient set selection circuit according to the step size indicated by said updating information such as to minimize the level of the corresponding output signal.

6. The multi-channel echo canceler according to claim 1, wherein said cross-correlation function value estimation circuit includes a first tapped delay line for delaying said first received signal, a second tapped delay line for delaying said second received signal, a first multiplier group consisting of a plurality of multipliers each for multiplying each tapped output of said first tapped delay line by said second received signal, a first integrator group consisting of a plurality of integrators in one-to-one correspondence to said multipliers in said first multiplier group and each for integrating the output of each said multiplier, a second multiplier group consisting of a plurality of multipliers each for multiplying each tapped output of said second tapped delay line by said first received signal, a second integrator group consisting of a plurality of integrators in one-to-one correspondence to said multipliers in said second multiplier group and each for integrating the output of each said multiplier, a first multiplier for multiplying said first and second received signals by each other, and a first integrator for integrating the output of said first multiplier.

7. The multi-channel echo canceler according to claim 6, wherein said integrator includes a tapped delay line for delaying the input signal to said integrator, a plurality of coefficient multipliers each for multiplying each tapped output of said tapped delay line by a constant, and an adder for obtaining the sum of the outputs of said coefficient multipliers and outputting the sum as result of integration.

8. The multi-channel echo canceler according to claim 6, wherein said integrator includes a first delay line for delaying the input signal to said integrator, a second delay line for storing the preceding output signal of said integrator by one sampling period, and an adder for outputting as said output signal obtained by subtracting the output of said first delay line from the sum of the output of said second delay line and said input signal, said output signal being stored in said second delay line.

9. The multi-channel echo canceler according to claim 6, wherein said integrator includes a first coefficient multiplier for multiplying the input signal to said multiplier by a constant, a tapped delay line for delaying the output signal of said integrator, a plurality of multipliers each for multiplying each tapped output of said tapped delay line by a constant, and an adder for obtaining the sum of the outputs of said coefficient multipliers and said first coefficient multiplier, the sum being made the output of said integrator and stored in said tapped delay line.

10. The multi-channel echo canceler according to claim 1, wherein said delay time difference estimation circuit includes a plurality of two-signal delay time difference estimation circuits for receiving said plurality of received signals as the inputs and estimating the delay time difference between two received signals among said plurality of received signals, a controller for receiving the results of said two-signal delay time difference estimation circuits and controlling said two-signal delay time difference estimation circuit so as to estimate all necessary two-signal delay time differences and outputting said two-signal delay time differences for receiving as input said first received signal and estimating said second received signal, a second transversal adaptive filter for receiving as input said second received signal and estimating said first received signal, a first absolute value calculation circuit group consisting of a plurality of absolute value calculation circuits each for obtaining the absolute value of a coefficient of said first adaptive filter, a second absolute value calculation circuit group consisting of a plurality of absolute value calculation circuits each for obtaining the absolute value of a coefficient of said second adaptive filter, and a judging circuit for estimating the delay time difference between said first and second received signals according to the output of each said absolute value calculation circuit in said first and second absolute value calculation circuit groups.

11. The multi-channel echo canceler according to claim 10, wherein said two-signal delay time difference estimation circuit includes a first selector for receiving said plurality of received signals as the input and selecting one of the two received signals designated by said controller as a first received signal, a second selector for receiving said plurality of received signals as the input and selecting other one of the two received signals designated by said controller as a first received signal, a first transversal filter for estimating the cross-correlation function values corresponding to a plurality of predetermined time differences between said first and second received signals, an absolute value calculation circuit group consisting of a plurality of absolute value calculation circuits for obtaining the absolute values of said cross-correlation function values corresponding to the plurality of time differences, and a judging circuit for the time difference corresponding to the maximum absolute value among the absolute values of said cross-correlation function values as an estimated time delay difference between said first and second received signals according to the output of each said absolute value calculation circuit in said absolute value calculation circuit group.

12. The multi-channel echo canceler according to claim 10, wherein said two-signal delay time difference estimation circuit includes a first selector for receiving said plurality of received signals as the input and selecting one of the two received signals designated by said controller as a first received signal, a second selector for receiving said plurality of received signals as the input and selecting other one of the two received signals designated by said controller as a second received signal, a cross-correlation function value estimation circuit for estimating the cross-correlation function values corresponding to a plurality of predetermined time differences between said first and second received signals, an absolute value calculation circuit group consisting of a plurality of absolute value calculation circuits for obtaining the absolute values of said cross-correlation function values corresponding to the plurality of time differences, and a judging circuit for the time difference corresponding to the maximum absolute value among the absolute values of said cross-correlation function values as an estimated time delay difference between said first and second received signals according to the output of each said absolute value calculation circuit in said absolute value calculation circuit group.

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BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to echo cancelers and, more particularly, to a multi-channel echo canceler for canceling multi-channel echo, which is generated as a result of the propagation of a plurality of received signals through a spatial acoustic path, from a transmitted signal.

2. Detailed Description of the Invention

In conversation systems involving a plurality of received signals and a single transmitted signal or a plurality of transmitted signals, regarding the method or apparatus for multi-channel echo canceling, i.e., canceling of echo which is generated as a result of the propagation of a received signal through a spatial acoustic path, a cascade connection type and a linear combination type are proposed in the Technical Report of Institute of Electronics, Information and Communication Engineers of Japan, Vol. 84, No. 330, pp. 7-4, CS-84-178 (hereinafter referred to as Literature No. 1), and also a multi-channel echo canceler, with a single adaptive filter per channel, is proposed in Proceedings of the 1991 Institute of Electronics, Information and Communication Engineers, Spring Conference, Vol. 1, pp. 202, A-202 (hereinafter referred to as Literature No. 2). However, In the Proceedings of the 6-th Digital Signal Processing Symposium, pp. 144-149, A5-3 (hereinafter referred to as Literature No. 3), it is pointed out that the cascade connection type and linear combination type lead to large. hardware size because the hardware size is proportional to the square of the number of channels, that the convergence of the adaptive filter is retarded when there is strong cross-correlation among received signals, and that the adaptive filter coefficients may fail to converge to the optimum value. Further, in Proceedings of the 1992 Institute of Electronics, Information and Communication Engineers, Spring Conference , Vol. 1, pp. 158, A-158 (hereinafter referred to as Literature No. 4), it is pointed out that in a multi-channel echo canceler with a single adaptive filter per channel, it takes a long time from the instant of movement or change of the talker till the re-convergence of the filter coefficients to the optimum value and that during this time the echo cancellation performance is deteriorated. To solve this problem, in the Literature No. 4 a compact multi-channel echo canceler is proposed, which can fast track the movement or change of the talker. The compact multi-channel echo canceler proposed in the Literature No. 4 will now be described in connection with its application to a television conference system, in which both the received and transmitted signals are of two channels.

FIG. 16 is a block diagram showing an audio part of a conventional 2-channel television conference system connecting two television conference rooms 30 and 31. Here, acoustic echo cancellation in the first television conference room 30 will be considered.

It is assumed that a second and a third talker 18 and 19 are present in the second television conference room 31.

Speeches 20 and 22 from the respective second and third talkers 18 and 19 are led through the spatial acoustic path so as to be inputted in a third microphone 24 and supplied to a second echo canceler 130.sub.2. The speeches inputted in the third microphone 24 are transmitted as a first received signal 1 to the first television conference room 30. Likewise, speeches 21 and 23 generated from the respective second and third talkers 18 and 19 are led through the spatial acoustic path so as to be inputted in a fourth microphone 25 and supplied to the second echo canceler unit 130.sub.2. The speeches inputted in the fourth microphone 25 are transmitted as a second received signal 2 to the first television conference room 30.

In the first television conference room 30, a first echo 5, which is generated as the first received signal 1 is reproduced by a first loudspeaker 3 and led through the spatial acoustic path to a first microphone 9, a second echo 6, which is generated as the second received signal 2 is reproduced by a second loudspeaker 4 and led through the spatial acoustic path to the first microphone 9, and a first transmitted signal 12, which is the speech of a first talker 11 reaching the first microphone 9, are added together to form a first mixed signal 14. Likewise, a third echo 7, which is generated as the first received signal 1 is reproduced by the first loudspeaker 3 and led through the spatial acoustic path to a second microphone 10, a fourth echo 8, which is generated as the second received signal 2 is reproduced by the second loudspeaker 4 and led through the spatial acoustic path to the second microphone 10, and a second transmitted signal 13, which is the speech of the first talker 11 reaching the second microphone 10, are added together to form a second mixed signal 15. For the canceling of the echoes 5 to 8 contained in the first and second mixed signals 14 and 15, a first echo canceler unit 130.sub.1 is used.

A delay time difference estimation circuit 101 receives the first and second received signals 1 and 2 as input signals and estimates the delay time difference between the two received signals, the result of estimation being supplied to a received signal selection circuit 102 and a filter coefficient set selection circuit 104. The received signal selection circuit 102 detects the received signal having a shorter delay time from the two received signals 1 and 2 according to the result of estimation in the delay time difference estimation circuit 101, the result of detection being supplied to a selector 103. The selector 103 receives the first and second received signals 1 and 2 as input signals and selectively supplies the received signal having the shorter delay time from the two received signals 1 and 2 to a first and a second adaptive filter 122 and 123 according to the result of detection in the received signal selection circuit 102. The filter coefficient set selection circuit 104 selects a set of filter coefficients among a plurality of preliminarily prepared sets of filter coefficients used in the first and second adaptive filters 122 and 123, the result of selection being supplied to the first and second adaptive filters 122 and 123 according to the result of estimation in the delay time difference estimation circuit 101.

The first adaptive filter 122 receives the received signal selected by the selector 103 as an input signal and generates an echo replica corresponding to the echo contained in the first mixed signal 14 by using the filter coefficient selected by the filter coefficient selection circuit 104, the generated echo replica being supplied to a first subtracter 107. The first subtracter 107 subtracts the echo replica as the output of the first adaptive filter 122 from the first mixed signal 14 to produce a first output signal 16. The first adaptive filter 122 is controlled such as to minimize the first output signal 16.

The second adaptive filter 123 receives the received signal selected by the selector 103 as an input signal and generates an echo replica corresponding to the echo contained in the second mixed signal 15 by using the filter coefficient selected by the filter coefficient selection circuit 104, the generated echo replica being supplied to a second subtracter 108. The second subtracter 108 subtracts the echo replica as the output of the second adaptive filter 123 from the second mixed signal 15 to produce a second output signal 17. The second adaptive filter 123 is controlled such as to minimize the second output signal 17.

The delay time difference estimation circuit 101 estimates the delay time difference between the first and second received signals 1 and 2 by using a cross-correlation function between the first and second received signals 1 and 2. Denoting the first and second signals 1 and 2 at instant n by x.sub.1 (n) and x.sub.2 (n), respectively, the cross-correlation function R.sub.12 (n, m) at the instant n corresponding to the delay time difference m is defined as:

R.sub.12 (n, m)=E[x.sub.1 (n)x.sub.2 (n+m)] (1)

E[.multidot.] is the ensemble average of .multidot.. It is difficult, however, to calculate the ensemble average as defined. Usually, therefore, it is approximated by a time average. For example, using the first order recursive integral it is calculated as:

R.sub.12 (n, m)=(1-.alpha.)x.sub.1 (n)x.sub.2 (n+m)+.alpha.R.sub.12 (n-1,m)(2)

where .alpha. is a constant given as

0<.alpha.<1 (3)

By increasing .alpha., the integration period is increased to increase the accuracy of the delay time difference estimation. However, the tracking speed to the movement or change of the talker is reduced. By reducing .alpha., on the other hand, the integration period is reduced to increase the tracking speed to the movement or change of the talker. In this case, the accuracy of the delay time difference estimation is reduced.

In other words, increasing .alpha. for increasing the accuracy of the delay time difference estimation results in delay of detection of the movement or change of the talker. During the period from the movement or change of the talker till the actual detection of such movement or change, an erroneous set of filter coefficients is selected, thus increasing the residual echo so as to increase the amount of filter coefficient update. Such erroneous filter coefficient updating results in the production of a filter coefficient set having a great coefficient error. If such a filter coefficient set with great coefficient error is selected again, after it is recognized that the talker has moved or changed, the performance of echo cancellation is deteriorated.

On the other hand, reducing a for increasing the tracking speed to the movement or change of the talker results in reduction of the accuracy of the delay time difference estimation. In this case, the estimated delay time difference is changed frequently so as to bring about frequent filter coefficient switching, thus deteriorating the performance of echo cancellation.

As shown, the prior art method and apparatus for multi-channel echo cancellation as described above, pose problems such that increasing the accuracy of the delay time difference estimation results in a delay in the detection of the movement or change of the talker so as to increase the filter coefficient error in the adaptive filters, while increasing the tracking speed to the movement or change of the talker results in reduction of the accuracy of the delay time difference estimation so as to bring about frequent filter coefficient switching, thus deteriorating the performance of echo cancellation.

SUMMARY OF THE INVENTION

An object of the invention is to provide a multi-channel echo canceler, which is free from echo cancellation performance deterioration due to delay in the detection of the movement or change of the talker a reduction of the accuracy of delay time difference estimation.

To attain the above object of the invention, there is provided a multi-channel echo canceler for canceling echoes, which are generated as a result of propagation of 2-channel received signals along a spatial acoustic path from a first and a second loudspeaker to a first and second microphone, from mixed signals containing a speech source signal and the echoes inputted through the first and the second microphone. The multi-channel echo canceler comprises a delay time difference estimation circuit for receiving a first and a second received signal as inputs and for estimating the delay time difference between the 2-channel received signals, a received signal selection circuit for outputting a designation signal designating the shorter-delay-time one of the first and second received signals, a first selector for selecting the shorter-delay-time one of the first and second received signals according to the designation signal, a filter coefficient set selection circuit for selecting a set of filter coefficients among a plurality of preliminarily prepared sets of filter coefficients on the basis of a predetermined first algorithm according to the result of estimation in the delay time difference estimation circuit, a cross-correlation function value estimation circuit for estimating a plurality of cross-correlation function values between the two received signals by using a predetermined method, a second selector for selecting, among the estimated cross-correlation function values, the cross-correlation function value corresponding to the delay time difference between the two received signals, an absolute value calculation circuit for calculating the absolute value of the selected cross-correlation function value, a power level estimation circuit for estimating the average power level of the two received signals, a normalization circuit for normalizing the absolute value of the selected cross-correlation function value with the estimated average power level of the received signals, a coefficient updating control circuit for outputting updating information about the updating of the selected set of filter coefficients according to the result of the normalization, a first adaptive filter for receiving the shorter-delay-time received signal selected by the first selector as an input, generating a first echo replica corresponding to echo contained in the first mixed signal and minimizing the difference between a first mixed signal and a first echo replica according to the updating information, a first subtracter for outputting the result of subtraction of the first echo replica from the first mixed signal as the first output signal, a second adaptive filter for receiving the shorter-delay-time received signal selected by the first selector as an input, generating a second echo replica corresponding to echo contained in the second mixed signal and minimizing the difference between a second mixed signal and a second echo replica according to the updating information, and a second subtracter for outputting the result of subtraction of the second echo replica from the second mixed signal as the second output signal.

According to the invention, with the above construction it is possible to obtain highly accurate delay time difference estimation and also the quick detection of the movement or change of the talker. Right after the movement or change of the talker, the filter coefficient set updating is stopped, or step size is updated. Deterioration of the echo cancellation performance does not occur that might otherwise result from delay of the detection of the movement or change of the talker or reduction of accuracy of estimated delay time difference.

The above and other objects, features and advantages of the invention will become more apparent from the following description when the same is read with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing a first embodiment of the multi-channel echo canceler according to the invention, in which 2-channel received and transmitted signals are dealt with;

FIG. 2 is a block diagram showing a delay time difference estimation circuit in a case in which the received signal in the first embodiment is a M-channel signal;

FIG. 3 is a block diagram showing a two-signal delay time difference estimation circuit in the first embodiment;

FIG. 4 is a block diagram showing a cross-correlation function value estimation circuit in the first embodiment;

FIG. 5 is a block diagram showing a transversal integrator used in the first embodiment;

FIG. 6 is a block diagram showing a first and a second adaptive filters in the first and second embodiments;

FIG. 7 is a block diagram showing an example of operational circuits shown in FIG. 6;

FIG. 8 is a block diagram showing a different example of two-signal delay time difference estimation circuit;

FIG. 9 is a block diagram showing a different example of integrators shown in FIG. 4;

FIG. 10 is a block diagram showing a further example of integrators shown in FIG. 4;

FIG. 11 is a block diagram showing a second embodiment of the multi-channel echo canceler according to the invention, in which received and transmitted signals are 2-channel signals;

FIG. 12 is a block diagram showing a third embodiment of the multi-channel echo canceler according to the invention, in which received and transmitted signals are 2-channel signals;

FIG. 13 is a block diagram showing an example of first and second adaptive filters in the third and fourth embodiments;

FIG. 14 is a block diagram showing a fourth embodiment of the multi-channel echo canceler according to the invention, in which received and transmitted signals are 2-channel signals;

FIG. 15 is a block diagram showing an embodiment of the multi-channel echo canceler according to the invention, in which M-channel received and transmitted signals are dealt with; and

FIG. 16 is a block diagram showing a speech part of a conventional 2-channel television conference system.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Preferred embodiments of the invention will now be described with reference to the accompanying drawings.

FIGS. 1 to 7 illustrate a first embodiment of the invention applied to cancellation of acoustic echo generated when a received signal is propagated from loudspeakers through spatial acoustic paths and recorded in microphones.

FIG. 1 is a block diagram showing a first embodiment of the multi-channel echo canceler according to the invention, in which received and transmitted signals are 2-channel signals. A delay time difference estimation circuit 101 receives a first and a second received signal 1 and 2 as input signals and estimates the delay time difference between the two received signals 1 and 2, the result of the estimation being supplied to a received signal selection circuit 102, a filter coefficient set selection circuit 104 and a second selector 110. The received signal selection circuit 102 detects the shortest-delay-time received signal according to the result of estimation in the delay time difference estimation circuit 101 and supplies the result of the detection to a first selector 103. In the case where the received signals are 2-channel signals, it is possible to determine the shorter-delay-time one of the two signals according to the sign of the delay time difference. Where the received signals are 3- or more channel signals, the shortest-delay-time received signal is selected by using a set of a plurality of delay time differences between two signals. In this case, an operation of selecting two signals among the plurality of received signals, determining the longer-delay-time one of the two signals according to the sign of the delay time difference between the two signals, and removing the received signal determined to be delayed longer from the subject of judgment, may be repeatedly executed until the shortest-delay-time received signal remains. The first selector 103 selectively supplies the shortest-delay-time one of the received signals 1 and 2 to a first and a second adaptive filter 105 and 106 according to the result of detection in the received signal selection circuit 102.

The filter coefficient set selection circuit 104 selects a set of filter coefficients among a plurality of sets of filter coefficients used by the first and second adaptive filters 105 and 106 according to the result of estimation in the delay time difference estimation circuit 101 and supplies the result of the selection to the first and second adaptive filters 105 and 106. Where the received signals are 2-channel signals, the following method is used for the filter coefficient set selection. In the discrete time process, it can be assumed that the delay time difference t between two signals takes one of 2t.sub.max +1 integral values -t.sub.max, . . . , 0, . . . , t.sub.max without loss of generality. Thus, 2t.sub.max +1 sets of filter coefficients are prepared, and the (t+t.sub.max +1)-th set of filter coefficients may be used. In the case, in which the received signal is of M-channels (M>2), the following method may be used for the filter coefficient set selection. The delay time of each received signal behind the shortest-delay-time received signal according to the result of estimation in the delay time difference estimation circuit 101. Denoting the delay times t.sub.1, t.sub.2, . . . , t.sub.M, it can be assumed that these delay times may take either of the integral values 0, 1, . . . , t.sub.max. Since there are (t.sub.max +1).sup.M series of selecting M integral values among the integral values 0, 1, . . . , t.sub.max by permitting repetition (t.sub.max +1).sup.M sets of filter coefficients may be prepared, and a set of filter coefficients given as: ##EQU1## may be used.

A cross-correlation function value estimation circuit 109 estimates cross-correlation function values of the two received signals 1 and 2 and supplies the result of the estimation to the second selector 110. The second selector 110 selectively supplies a value corresponding to the delay time difference between the two received signals 1 and 2 estimated by the delay time difference estimation circuit 101, which is among the cross-correlation function values estimated by the cross-correlation function value estimation circuit 109, to an absolute value calculation circuit 111. The absolute value calculation circuit 111 calculates the absolute value of the cross-correlation function value selected by the second selector 110 and supplies the resultant absolute value to a normalizing circuit 113. A power level estimation circuit 112 estimates the average power level of the two received signals 1 and 2 and supplies the result of the estimation to the normalizing circuit 113. The normalizing circuit 113 normalizes the absolute value obtained in the absolute value calculation circuit 111 with the average power level of the received signals as estimated by the power level estimation circuit 112, and supplies the result of the normalization to a coefficient updating control circuit 114. The coefficient updating control circuit 114 makes a decision according to the result of normalization in the normalizing circuit 113 as to whether the filter coefficient set is to be updated according to the value of a formula (18) to be described later and supplies the result of the decision to the first and second adaptive filters 105 and 106.

The first adaptive filter 105 receives the received signal selected by the first selector 103 as an input signal and produces a first echo replica corresponding to echo contained in a first mixed signal 14 by using the set of filter coefficients selected by the filter coefficient set selection circuit 104, the produced first echo replica being supplied to a first subtracter 107. The first subtracter 107 subtracts the first echo replica as the output of the first adaptive filter 105 from the first mixed signal 14 and provides the result as a first output signal 16. When the coefficient set updating control circuit 114 decides that updating of the filter coefficient set is required, the first adaptive filter 105 updates the filter coefficient set selected by the filter coefficient set selection circuit 104 such as to minimize the first output signal 16. The algorithm underlying this operation will be described later in connection with a formula (13).

The second adaptive filter 106, likewise, receives the received signal selected by the first selector 103 as an input signal and produces a second echo replica corresponding to echo contained in the second mixed signal 15 by using the filter coefficient set selected by the filter coefficient set selection circuit 104, the produced second echo replica being supplied to a second subtracter 108. The second subtracter 108 subtracts the second echo replica as the output of the second adaptive filter 106 from the second mixed signal 15 and provides the result as a second output signal 17. When the coefficient set updating control circuit 114 decides that filter coefficient set updating is required, the second adaptive filter 106 updates the filter coefficient set selected by the filter coefficient set selection circuit 104 such as to minimize the second output signal 17.

FIG. 2 is a block diagram showing the delay time difference estimation circuit in the first embodiment, in which the received signal has M-channels. The delay time difference estimation circuit 101 includes K (K>1) two-signal delay time difference estimation circuits 210.sub.1, 210.sub.2, . . . , 210.sub.K and a controller 205, and it receives a plurality of received signals 201.sub.1, 201.sub.2, . . . , 201.sub.M as the inputs and outputs delay time difference information 202, which is a set of a plurality of delay time differences corresponding to respective signal sets for each of two signals selected from the plurality of received signals 201.sub.1, 201.sub.2, . . . , 201.sub.M. The K two-signal delay time difference estimation circuits 210.sub.1, 210.sub.2, . . . , 210.sub.K all are of the same structure and operate in the same way. Thus, in the following description of each two-signal delay time difference estimation circuit, the subscript i is omitted, and reference is made as two-signal-delay time difference estimation circuit 210, control signal 204 and two-signal delay time difference 203.

Two-signal delay time difference estimation circuit 210 receives as input signals the M channels received signals 201.sub.1, 201.sub.2, . . . , 201.sub.M and estimates delay time difference 203 between two signals among the received signals 201.sub.1, 201.sub.2, . . . , 201.sub.M that are designated by control signal 204, the result of the estimation being supplied to the controller 205.

The controller 205 receives two-signal delay time differences 203.sub.1, 203.sub.2, . . . , 203.sub.K output from the K two-signal delay time difference estimation circuits 210.sub.1, 210.sub.2, . . . , 210.sub.K as the input and supplies control signals 204.sub.1, 204.sub.2, . . . , 204.sub.K each for designating a set of received signals for two-signal delay time difference estimation to each of the two-signal delay time difference estimation circuits 210.sub.1, 210.sub.2, . . . , 210.sub.K. The controller 205 outputs as the delay time difference information 202 all the two-signal delay time differences corresponding to the sets of two signals selected from the plurality of received signals 201.sub.1, 201.sub.2, . . . , 201.sub.M.

In the delay time difference estimation circuit 101, it is possible to use a single circuit repeatedly in place of the two-signal delay time difference estimation circuits 210.sub.1, 210.sub.2, . . . , 210.sub.K. Where the received signals are of M-channels, by preparing M(M-1)/2 two-signal delay time difference estimation circuits and effecting simultaneous two-signal delay time estimation with respect to all the sets of two channels selected from the M-channels of received signals, there is no need of repeatedly using each two-signal delay time difference estimation circuit, and thus it is possible to reduce the time required for the estimation. Meanwhile, denoting the delay time difference between a first and a second received signal selected from the M-channels of received signals by t.sub.12, the delay time difference between the second and a third signal by t.sub.23, the delay time difference t.sub.13 between the first and third received signals can be obtained as:

t.sub.13 =t.sub.12 +t.sub.23 (4)

Thus, it is possible to obtain a desired delay time difference between two signals on the basis of (M-1) two-signal delay time differences. Where received signals are of 2-channels, all the delay time differences can be estimated by using a single two-signal delay time difference estimation circuit only once.

FIG. 3 is a block diagram showing the two-signal delay time difference estimation circuit 210 in the first embodiment. This two-signal delay time difference estimation circuit 210 receives a plurality of received signals 201.sub.1, 201.sub.2, . . . , 201.sub.M as input signals and estimates the delay time difference between two signals designated by the control signal 204 from among these received signals.

Now, the principles underlying delay time difference estimation using a cross-correlation function of two signals will be described. Denoting the levels of a first and a second received signal 213 and 214 by x.sub.1 (n) and x.sub.2 (n), the cross-correlation function of two signals 10 with respect to time difference m at instant n is given as:

R.sub.12 (n,m)=E[x.sub.1 (n),x.sub.2 (n+m)] (5)

Assuming steady received signal x.sub.1 (n) and signal

x.sub.2 (n)=x.sub.1 (n)(n-n.sub.d), ##EQU2## and thus the cross-correlation function R.sub.12 (n, m) between x.sub.1 (n) and x.sub.2 (n) is

R.sub.12 (n,m)=1/2 [E[(x.sub.1.sup.2 (n)]+E[x.sub.2.sup.2 (n+m)]]-E[(x.sub.1 (n)-x.sub.1 (n-n.sub.d +m)).sup.2 ] (7)

If x.sub.1 (n) and x.sub.2 (n) are steady, received signal power levels E[x.sub.1.sup.2 (n)] and E[x.sub.2.sup.2 (n)] are constants. Thus, by setting the average power level of the received signals as:

P(n)=1/2 [E[(x.sub.1.sup.2 (n)]+E[x.sub.2.sup.2 (n+m)]] (8)

we obtain:

R.sub.12 (n,m)=P(n)-1/2 E[(x.sub.1 (n)-x.sub.1 (n-n.sub.d +m)).sup.2 ](9)

Thus, R.sub.12 (n, m) is maximum when m=n.sub.d.

When x.sub.1 (n) and x.sub.2 (n) are 180 degrees out of phase, that is, x.sub.2 (n)=-x.sub.1 (n-n.sub.d), from ##EQU3## R.sub.12 (n, m) is:

R.sub.12 (n,m)=-[P(n)-1/2]E[(x.sub.1 (n)-x.sub.1 (n-n.sub.d +m)).sup.2 ]](11)

Hence, when m=n.sub.d, R.sub.12 (n, m) is minimum, and the absolute value thereof is maximum.

From this fact, it will be seen that it is possible to estimate the delay time difference 208 between the first and second received signals 218 and 214 from the time difference m corresponding to the maximum absolute value of the cross-correlation function R.sub.12 (n, m).

Two signals for obtaining the delay time difference are selected by the respective selectors 211 and 212. More specifically, one of the two signals designated by the control signal 204, which designates the received signals as the subject of obtaining delay time difference, is selected as the first received signal 213 by the first selector 211, which receives a plurality of received signals 201.sub.1, 201.sub.2, . . . , 201.sub.M as the input. Likewise, the other one of the two signals designated by the control signal 204 is selected as the second received signal 214 by the second selector 212, which receives the received signals 201.sub.1, 201.sub.2, . . . , 201.sub.M as the input.

A cross-correlation function value estimation circuit 251 estimates values 252.sub.1, 252.sub.2, . . . , 252.sub.J corresponding to J predetermined time differences among the values of the cross-correlation function between the first and second received signals 213 and 214. An absolute value calculation circuit group consisting of J absolute value calculation circuits 253.sub.1, 253.sub.2, . . . , 253.sub.J which are in one-to-one correspondence to the cross-correlation function values 252.sub.1, 252.sub.2, . . . , 252.sub.J, calculates the absolute values 254.sub.1, 254.sub.2, . . . , 254.sub.J of the cross-correlation function values 252.sub.1, 252.sub.2, . . . , 252.sub.J.

A judging circuit 255 derives a time difference which maximizes the absolute values 254.sub.1, 254.sub.2, . . . , 254.sub.J of the cross-correlation function values 252.sub.1, 252.sub.2, . . . , 252.sub.J, the result being made the two-signal delay time difference 203.

FIG. 4 is a block diagram showing the cro