In a digital sigma-delta modulator with multi-phase operations by time-sharing including an adder to produce multiple integration, an arrangement includes switching circuitry for alternately establishing one of: a connection between a first input of the adder and an input of the modulator; and connections between the adder output and the first input of the adder by way of a first integration delay circuit, and the adder output and a second input of the adder by way of a second delay circuit.
For this system and for this equipment there has been provided a phase alignment device (30) which has an access for input data (50) applied to an access (51) at a rate of a first clock signal, and an access (70) for producing at the rate of a second clock signal applied to an access (71) a justifiable data stream, in which stream bits can be inserted or deleted. The data are written and read in and from a common memory (60) by means of a write counter (55) and a read counter (80), respectively. A comparing element (90) measures the difference of the contents of said counters (55) and (80). With each variation of this difference, intermediate steps are added with the elements (95), (97) and (98), so that the means (92) controlling the justification can be formed by a sigma-delta modulator which has a 0.5 threshold.
A D/A converter with an overflow detector for resetting a delaying unit when a digital signal overflows a specified bitprovided in a noise shaping circuit thereof.
A sampled data, analog computing method and circuit for producing an output voltage V.sub.OUT with a magnitude proportional to the root-mean-square value V.sub.RMS of a monopolar input voltage V.sub.DC, first demodulates or chops a time-varying monopolar input voltage V.sub.DC of interest to produce a demodulated or chopped voltage V.sub.CHOP, and then filters the chopped voltage V.sub.CHOP to produce an output voltage V.sub.OUT. The chopping operation is conducted at a duty ratio or modulation ratio proportional to the ratio of the monopolar input voltage V.sub.DC to the output voltage V.sub.OUT, with the result that the magnitude of the output voltage V.sub.OUT is proportional to the root-mean-square value V.sub.RMS of the monopolar input voltage V.sub.DC. The illustrated embodiment of the invention (i) rectifies a time-varying bipolar input voltage V.sub.AC of interest with a precision fullwave rectifier to produce the monopolar input voltage V.sub.DC, (ii) produces a pulse code modulated (PCM) signal with the required duty ratio utilizing an oversampling delta-sigma modulator, and (iii) produces the output voltage V.sub.OUT with an inverting second order low pass filter so that V.sub.OUT has the inverted polarity and greater magnitude compared to V.sub.DC that is required on the delta-sigma modulator reference node.
A .SIGMA..DELTA. digital/analog converter includes a signal reconstructing multirate low pass filter realized as a switched capacitor fully differential, double sampled structure. The input stage of the filter employs only two sampling capacitors, switched alternately on the two inputs of the stage. The input stage further includes two delay circuits (z.sup.-1) in the feed line of the bitstream towards one of the two inputs of the multistage SC filter. The zeroes introduced in the transfer function reduce the noise energy in the vicinity of frequencies f.sub.s /2.sup.n, preserving the SNR even with a relatively large mismatch between the capacitors.
The invention relates to a technique called "Internal Linear Feedback (ILF)" for the stabilization of high-order sigma-delta modulators. The ILF technique involves an overload detector and a selector. Once "overloaded" is detected by the overload detector, the selector is activated to make the modulator entering the ILF mode, in which additional internal linear feedback paths are employed to stabilize the modulator. Otherwise, the modulator operates in normal mode as a general high-order modulator.
