Video processing apparatus - Patent Review 5327158

We claim:

1. A video processing apparatus which displays a background picture, on display means having a display screen, composed of a plurality of pixels in a horizontal direction and a vertical direction, respectively, comprising:

position data generating means for generating first position data representative of a position in said horizontal direction and said vertical direction on said display screen;

parameter data applying means for applying parameter data for rotation of said background picture, said parameter data being sequentially changed within an angular range by which said background picture is to be rotated;

position data operation means for operating on second position data after performing said rotation on said display screen on the basis of said first position data and said parameter data;

first storage means for storing a plurality of character codes representative of a plurality of characters each composed of a plurality of pixels, said position operation means operating on said second position data for each of said plurality of pixels;

first reading means for generating a reading address for reading said character code from said first storage means on the basis of said second position data operated on by said position data operation means;

second storage means for storing color data of respective pixels constituting said character, said character having a plurality of pixels;

second reading means for reading said color data from said second storage means on the basis of the character code read by said first reading means and said second position data; and

video signal generating means for generating a video signal on the basis of the color data read by said second reading means.

2. A video processing apparatus for displaying a background picture, on display means having a display screen, composed of a plurality of pixels in a horizontal direction and a vertical direction, respectively, comprising:

position data generating means for generating first position data representative of a position in said horizontal direction and said vertical direction on said display screen;

parameter data applying means for applying parameter data for at least one of rotation, enlargement and reduction of said background picture, said parameter data for rotation being sequentially changed within an angular range by which said background picture is to be rotated;

position data operation means for operating on second position data, on the basis of said first position data and said parameter data, after performing said at least one of rotation, enlargement and reduction on said display screen;

first storage means for storing a plurality of character codes representative of a plurality of characters each composed of a plurality of pixels, said position operation means operating on said second position data for each of said plurality of pixels;

first reading means for generating a reading address for reading said character code from said first storage means on the basis of said second position data operated on by said position data operation means;

second storage means for storing color data of respective pixels constituting said character, said character having a plurality of pixels;

second reading means for reading said color data from said second storage means on the basis of the character code read by said first reading means and said second position data; and

video signal generating means for generating a video signal on the basis of the color data read by said second reading means.

3. A video processing apparatus in accordance with claim 1 or 2, wherein said first reading means accesses said first storage means on the basis of a portion of said second position data, and said second reading means accesses said second storage means on the basis of said character data and a remaining portion of said second position data.

4. A video processing apparatus in accordance with claim 2, wherein said parameter data applying means generates parameter data (A, B, C, D), and said position data generating means generates said first position data (x.sub.0, y.sub.0), and

said position data operation means includes center coordinate data generating means for generating center coordinate data (x.sub.0, y.sub.0) for at least one of said rotation, enlargement and reduction, and matrix operation means for performing a matrix operation according to the following equation on the basis of said first position data (x.sub.1, y.sub.1) and said center coordinate data (x.sub.0, y.sub.0) to evaluate said second position data (x.sub.2, y.sub.2) of the pixels after performing at least one of said rotation, enlargement and reduction on said display screen: ##EQU2## wherein, if a scaling factor in said horizontal direction for enlargement or reduction is .alpha., a scaling factor in said vertical direction for enlargement or reduction is .beta., and an angle to be rotated is .gamma., said parameter data A, B, C and D are respectively given by the following equations:

A=1/.alpha..multidot.cos.gamma.

B=1/.alpha..multidot.sin.gamma.

C=-1/.beta..multidot.sin.gamma.

D=1/.beta..multidot.cos.gamma..

5. A video processing apparatus in accordance with claim 3, wherein said first position data generating means generates said first position data (x.sub.1, y.sub.1) represented by x.sub.1 =H.sub.p +H.sub.c and y.sub.1 =V.sub.p +V.sub.c when offset data in said horizontal direction and said vertical direction are H.sub.p and V.sub.p and position data of said pixel in said horizontal direction and said vertical direction are H.sub.c and V.sub.c.

6. A video processing apparatus in accordance with claim 4, wherein said display means includes a raster scan display, and said operation means performs a portion of said matrix operation necessary for a next horizontal scanning period of said raster scan display during a horizontal blanking period and performs a remaining portion of said matrix operation operation during said next horizontal scanning period for each pixel.

7. A video processing apparatus in accordance with claim 6, wherein said first storage means including a storage area larger than a size of said display screen of said raster scan display, and

said data generating means includes means for generating data for designating character data of a character to be displayed out of the characters stored in said first storage means.

8. A video processing apparatus in accordance with claim 5, wherein said operation means operates on said second position data (x.sub.2, y.sub.2) according to the following equations:

x.sub.2 =A(H.sub.p -x.sub.0)+B(V.sub.p -y.sub.0)+x.sub.0 +A.multidot.H.sub.c +B.multidot.V.sub.c

y.sub.2 =C(H.sub.p -x.sub.0)+D(V.sub.p -y.sub.0)+x.sub.0 +C.multidot.H.sub.c +D.multidot.V.sub.c.

9. A video processing apparatus in accordance with claim 8, wherein said display means includes a raster scan display, said operation means performs terms "+A.multidot.H.sub.c " and "+C.multidot.H.sub.c " of said equations for each pixel during a horizontal scanning period of said raster scan display, and performs a remaining portion of said equations necessary for said horizontal scanning period during a horizontal blanking period before said horizontal scanning period.

10. A video processing apparatus which displays a background picture, on a raster scan display having a display screen, composed of a plurality of pixels in a horizontal direction and a vertical direction, respectively, comprising:

storage means for storing an image data of said background picture in an address corresponding to a display position of said background picture;

matrix operation means for performing a matrix operation for at least one of rotation, enlargement and reduction of said background picture, said matrix operation means performing an operation of a portion of said matrix operation necessary for a next horizontal scanning period of said raster scan display during a horizontal scanning period and an operation of a remaining portion of said matrix operation for each pixel during said next horizontal scanning period;

reading means for reading said image data from said storage means on the basis of operation results by said matrix operation means; and

video signal generating means for generating a video signal on the basis of the image data read by said reading means.

11. A video game system for playing video games which display both moving picture character symbols and a background picture, constituted by at least one of a plurality of background picture character symbols, and each of said character symbols being composed of a plurality of pixels, comprising:

a game machine including a central processing unit and a picture processing unit coupled to said central processing unit;

a game cartridge coupled in use to said game machine and including memory means for storing character data representative of a plurality of motion picture characters and background picture characters, and for storing at least one of rotation data, enlargement data, and reduction data respectively representative of an arbitrary rotation angle, enlargement rate, and reduction rate;

said central processing unit including means for accessing said memory means and for generating background picture processing parameters including at least one of a rotation parameter, enlargement parameter and reduction parameter necessary for operating on a background picture address on the basis of said rotation data, enlargement data, and reduction data;

said picture processing unit including a background picture address generating circuit for receiving said background picture processing parameters from said central processing unit and for calculating background picture address information for each of said plurality of pixels, whereby a background picture may be displayed in at least one of a rotated, enlarged, and reduced disposition.

12. A video game system in accordance with claim 11 further including a video memory having a first set of memory locations for storing data associated with a background picture to be displayed and a second set of memory locations for storing data associated with moving picture symbols to be displayed.

13. A video game system in accordance with claim 11, wherein said picture processing unit includes moving picture address control circuitry for receiving moving picture attribute data and for generating a video memory address for retrieving moving picture symbols to be displayed.

14. A video game system according to claim 13, said picture processing unit further including a moving picture processing circuit coupled to said moving picture address control circuitry for receiving and temporarily storing moving picture character symbol related data and a background picture processing circuit coupled to said background picture address control circuitry for receiving and temporarily storing background picture related data; a priority circuit for determining priority between moving picture data received from said moving picture processing circuit and background picture data received from said background picture processing circuit and for outputting the higher priority data; and video signal generating means, coupled to said priority circuit, for receiving data to be displayed from said priority circuit and for generating a video signal.

15. A video game signal according to claim 11, wherein said background picture address control circuit is coupled to central processing unit and includes register means for receiving said background picture processing parameters from said central processing unit.

16. A video game system according to claim 11, further including timing means for generating a plurality of timing signals, said background picture address control circuit includes a plurality of registers for storing at least rotation related address information, said registers being loaded in response to predetermined ones of said timing signals.

17. A video game system according to claim 11, wherein said background picture address control circuitry includes means for processing both background picture rotation and enlargement related address information.

18. A video game system according to claim 11, wherein said background picture address control circuitry includes means for processing both background picture rotation and reduction related address information.

19. A video game system according to claim 11, further including a video memory for storing data associated with a background picture to be displayed, wherein said background picture address control circuit calculates a video memory address in response to background picture offset data.

20. A video game system according to claim 11, further including a video memory for storing data associated with a background picture to be displayed, wherein said background picture address control circuit calculates a video memory address in response to background picture character flipping data.

21. A video game system according to claim 19, wherein said background picture offset data is stored in said memory means in said game cartridge.

22. A video game system according to claim 20, wherein said background picture character flipping data is stored in said memory means in said game cartridge.

23. A video game system according to claim 11, further including timing means for generating a first set of timing signals defining a preliminary processing time period during which no video signal is output from the picture processing unit and a second set of timing signals defining a real-time processing period during which a video signal is displayed, wherein said background picture address control circuit is operable to perform rotation related address processing in response to said second set of timing signals.

24. A video game system according to claim 23, wherein said background picture address control circuit is operable to calculate rotation related constants in response to said first set of timing signals.

25. A video game system according to claim 11, wherein said memory means in said game cartridge includes means for storing program information defining the type of character to be displayed, the time the character is to be displayed, and the coordinate position at which the character is to be displayed.

26. A video game system according to claim 11, wherein said memory means in said game cartridge includes means for storing: character attribute data including character horizontal and vertical position data for designating character horizontal and vertical display positions, a character code for designating the type of character, character color data, a flip code for designating the display of a character reversed in the vertical and horizontal directions, and priority data for designating priority between a moving picture character and a background picture character.

27. A video game system according to claim 11 further including a video memory, wherein said memory means in said game cartridge includes means for storing character related data including color data, and a character code for designating which background character is to be written into said video memory and at which locations in the video memory that background character is to be written.

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FIELD OF THE INVENTION

The present invention generally relates to a video processing apparatus for use with a television set or the like which can process and display not only moving picture character symbols but also a background picture (or a still picture).

PRIOR ART

Techniques for rotating a moving picture character symbol are well known. For example, video games such as Space War and Computer Space providing rotation of moving character symbols have been widely played for decades. Japanese Patent Publication No. 45,225/1980 and Japanese Patent Laid-Open Gazette No. 113,529/1976 (counterpart to U.S. Pat. No. 4,026,555) also disclose moving picture symbol rotation.

Techniques for rotating a background picture are also known. An exemplary such prior art system may be represented by the block diagram shown in FIG. 17. In the block diagram shown in FIG. 17, a video RAM (referred to as "VRAM" hereinafter) 102 comprising a random access memory (referred to as "RAM" hereinafter) as well as a CPU 103 are connected to a picture processing unit 101. A main memory 104, storing image data for a background picture, moving picture character symbols, and control data for displaying and controlling the image data, is connected to the CPU 103. The image data stored in the main memory 104 are transferred to the VRAM 102 through the picture processing unit 101. On the basis of the control data from the CPU 103, the picture processing unit 101 reads data from the VRAM 102 and outputs the data as a video signal to a display device 105. Display device 105 displays an image according to the data. Addresses of the VRAM 102 correspond to positions in the horizontal and vertical directions of the image displayed on the display device 105. The above described moving picture character symbol image data and/or the background picture data are stored in respective addresses of the VRAM 102.

The above-described conventional television video game system is capable of rotating, enlarging or reducing background pictures for display. When a predetermined background picture is rotated, [or] enlarged, or reduced and displayed on the display device 105, the CPU 103 calculates (during a vertical blanking period), a new horizontal position and a new vertical position on the basis of an original position in the horizontal direction (referred to as "horizontal position" hereinafter) and an original position in the vertical direction (referred to as "vertical position" hereinafter) on a display screen of the image data of the original background picture stored in the VRAM 102. The CPU 103 then writes the image data of the original background picture into addresses of the VRAM 102 which corresponds to the new horizontal position and the new vertical position as calculated. Thereafter, during horizontal scanning, the picture processing unit 102 sequentially converts the data written in the VRAM 102 into a video signal and outputs the same to the display device 105.

Techniques for enlarging or reducing a background picture such as that disclosed in Japanese Patent Laid-Open Gazette No. 172088/1985 (counterpart to U.S. Pat. No. 4,754,270) are also known.

The technique disclosed in Japanese Patent Publication No. 45225/1980 or Japanese Patent Laid-Open Gazette No.113529/1976 for rotating a moving picture character symbol cannot be used for the rotation of a background picture.

The above-described prior art shown in FIG. 17 has the following disadvantage: When a background picture is to be rotated or enlarged or reduced and displayed, the CPU 103 must calculate the new horizontal and vertical positions. The rotation processing or the enlargement or reduction processing of the background picture typically takes a relatively long time. Accordingly, the throughput of the CPU 103 is reduced since the CPU 103 cannot perform very much other video processing.

Additionally, when the background picture is subjected to rotation processing or enlargement or reduction processing as described above, the image data of the background picture stored in the VRAM 102 is rewritten. Accordingly, the image data of the original background picture before rotation processing (or the enlargement or reduction processing) typically cannot be preserved. Therefore, for example, when the original background picture is repeatedly rotated through 30.degree. at a time and consequently, the original background picture is rotated through a total of 360.degree. (one rotation), any any computing errors at the time of respective rotations accumulate so that a background picture is displayed in coordinate positions different from that of the original background picture and may be displayed as a figure having a shape different from that of the original background picture. Since the original background picture is not preserved as described above, such prior art has the disadvantage in that a background picture having the same shape as that of the original background picture may not be displayed in the original exact position.

The technique disclosed in Japanese Patent Laid-Open Gazette No. 172088/1985 has disadvantages in that a background picture cannot be enlarged or reduced while being rotated. Moreover, rotation processing and enlargement or reduction processing cannot be achieved in a common circuit.

SUMMARY OF THE INVENTION

An important object of the present invention is to provide a video processing apparatus capable of displaying a background picture having the same shape as that of the original background picture without deformation after rotation.

Another object of the present invention is to provide a video processing apparatus capable of performing rotation, enlargement and/or reduction processing of a background picture at relatively high speed without burdening a CPU while reproducing the original background picture without deformation.

Still another object of the present invention is to provide a video processing apparatus capable of achieving enlargement or reduction processing while rotating a background picture.

The present invention provides a storage device for storing image data of a background picture in address locations corresponding to display positions of the background picture before rotation processing. An operation means operates, on the basis of rotation processing control data, on an address of the storage device corresponding to a display position of the background picture after performing background picture rotation processing. A reading arrangement reads image data stored in addresses of the storage device specified by the operation means. Video signal generating means generates a video signal on the basis of the image data read by the reading arrangement.

In accordance with another aspect of the present invention, there is provided a storage means for storing image data representing a background picture in address locations corresponding to display positions before rotation, enlargement and reduction processing. Operation means operate, on the basis of control data for rotation, enlargement, or reduction processing. The operating means operate on an address of the storage means corresponding to a display position of the background picture after rotation, enlargement or reduction processing of the background picture. A reading means reads the image data stored in the address of the storage means which is operated upon by the operation means. Video signal generating means generates a video signal on the basis of the image data read by the reading means.

By the above described construction, the storage means stores, before rotation (and/or enlargement or reduction) processing of a picture, image data representing the picture in an address corresponding to a display position of the picture before rotation (and/or enlargement or reduction) processing.

Then, in the rotation (and/or enlargement or reduction) processing of a picture, the operation means operates on an address of the storage means corresponding to a display position of the picture after performing the rotation (and/or enlargement or reduction) processing on the basis of the control data for the rotation (and/or enlargement or reduction) processing. The reading means then reads the image data stored in the address of the storage means which is operated on by the operation means, and the video signal generating means generates a video signal on the basis of the image data read by the reading means. Consequently, a video signal at the time of performing at least one of the rotation processing and the enlargement or reduction processing of the picture is obtained according to the image data stored in the storage means.

According to the present invention, a background picture having the same shape as that of the original background picture can be displayed without deformation before and after rotation. In addition, rotation and/or enlargement or reduction processing of the background picture can be achieved at high speed without burdening the CPU, and the original background picture is not deformed.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of an exemplary embodiment of the present invention when taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a block diagram of an exemplary presently preferred television gaming apparatus according to one embodiment provided by the present invention;

FIG. 2 illustrates an exemplary relation between a VRAM area and a display screen area of background picture data stored in a VRAM 7 shown in FIG. 1;

FIG. 3 is a schematic diagram showing an exemplary bit configuration of coordinates x and y indicating a position in the VRAM area shown in FIG. 2;

FIG. 4 is an exemplary memory map diagram of the VRAM shown in FIG. 1;

FIG. 5 is a schematic diagram showing exemplary storing conditions of color data of a background picture stored in the VRAM shown in FIG. 1;

FIG. 6 is a schematic diagram showing exemplary bit configurations of addresses and data in a background picture character area and a background picture screen area in the VRAM shown in FIG. 1;

FIG. 7 is a graphical diagram helpful in explaining the rotation processing and enlargement or reduction processing of a background picture;

FIGS. 8, 8A and 8B are a detailed circuit diagram showing an exemplary background picture address control circuit 2 as shown in FIG. 1;

FIGS. 9 and 10, 10A and 10B are timing charts showing an exemplary operation of the background picture address control circuit shown in FIGS. 8A-8B;

FIG. 11 is a schematic diagram showing an example of the display of an original background picture;

FIGS. 12 to 16 are schematic diagrams respectively showing examples of the display of a background picture in a case where the original background picture is enlarged, rotated and reduced or processed in these combinations; and

FIG. 17 is a block diagram showing an exemplary prior art television gaming apparatus.

DETAILED DESCRIPTION OF A PRESENTLY PREFERRED EXEMPLARY EMBODIMENT

Although in the following described exemplary embodiment, a television gaming machine is described, it should be noted that the present invention is also applicable to various video processing apparatus such as a personal computer or the like having as its object processing other than a game which is connected to a raster scan type CRT display.

FIG. 1 is a schematic block diagram of an exemplary television gaming apparatus 100 according to a presently preferred exemplary embodiment provided by the present invention.

This embodiment may generate video signals for display by a conventional raster scan type CRT display 8 such as an RGB monitor or a standard television receiving set. One screen or frame of such a display 8 is typically divided into 256.times.256 dots (pixels). However, since an image cannot be accurately displayed in portions of several lines on upper and lower sides due to a curved surface of the cathode-ray tube, 224 dots (excluding the lines from the number of dots in the vertical direction) are preferably actually utilized. Consequently, if one character--which is the minimum unit of a background picture (and/or a moving picture)--is composed of a 8.times.8 dots, 32.times.28=896 characters can be simultaneously displayed on one screen of the display 8.

The presently preferred embodiment television gaming apparatus independently controls background picture generation and moving picture generation. A background picture (or a still picture) forms a background which cannot be individually changed by an operation of a player. A moving picture can be moved by an operation of the player or by the control of a CPU 2. A picture processing unit 1 outputs a video signal for display by CRT display 8. The picture processing unit 1 composes (and generates video signals specifying) the background picture and the moving picture. The picture processing unit 1 includes a background picture address control circuit 24 which evaluates a read address of a VRAM 7 storing image data of the background picture by operation processing at the time of rotation and/or enlargement or reduction processing of the background picture; and changes the read address without changing the image data to perform rotation and/or enlargement or reduction processing.

Television gaming machine 100 includes a read-only memory (ROM) 3, a RAM 4 and a keyboard (user controls) 5 connected (through an address bus 11, a data bus 12 and a control bus 13) to a CPU 2 for carrying out a variety of television gaming machine control operations.

The ROM 3 in the preferred embodiment is used for storing program data for controlling the television gaming machine, data required to execute the program, and character data. The ROM 3 is contained in, for example, a cartridge 3a attachable to and detachable from the television gaming machine 100. This program data includes data for determining what type of moving character and/or background character is to be displayed, at what time the character is to be displayed, and in which coordinate position on a screen the character is to be displayed, as well as data for rotation, enlargement and reduction processing, etc. For each moving character to be displayed moving picture attribute data is associated with each character. Such moving picture attribute data includes: horizontal position data (Hc: 8 bits) for designating the character horizontal position, vertical position data (Vc: 8 bits) for designating the character vertical position, a character code (9 bits) for designating the type of character, a pallet code (3 bits) for designating a color pallet, a flip code (2 bits) for specifying display of a character reversed in the vertical and/or horizontal directions, a size code (1 bit) for designating the dot size of a character, and priority data (2 bits) for designating priority over a background picture. For each background character to be displayed the following data is associated with each character: a character code (8 bits) for designating the type of character, color data (8 bits) for each of pixels constituting a character, etc. Many background characters are displayed in combination to constitute a background picture (still picture), and a plurality of moving characters are typically displayed to constitute a moving picture. The background picture and the moving picture are composed and displayed on the same screen. A background character code corresponding to each address of the background picture is designated as data for displaying one background picture so as to determine which background character is to be written, in which address out of addresses in the vertical and horizontal directions in a VRAM area (as described later) the background character is to be written and consequently, whether or not the background character is to be displayed in a desired position (coordinates) on a screen corresponding to the address.

The RAM 4 is used as a working area by the above described CPU 2. The keyboard 4 is used for player input for controlling moving characters.

A CPU interface circuit 21 included in the picture processing unit 1 is connected to the CPU 2 through the address bus 11, the data bus 12 and the control bus 13. A reference signal generator 6, a VRAM 7 including two RAMS (7a, 7b), and a CRT display 8 such as an RGB monitor or a standard television receiving set are connected to the picture processing unit 1.

The picture processing unit 1, under the control of CPU 2, is used for transferring image data of moving picture character symbols and background picture character symbols to the VRAM 7 during a vertical blanking period or at a predetermined transfer time. The picture processing unit 1 is also used for reading the image data of the moving picture and/or the background picture stored in the VRAM 7. Such reading may be without any modification, or by outputting image data obtained by performing rotation, enlargement and reduction processing. PPU 1 converts the image data into an RGB signal and/or an NTSC color signal and outputs the same to display B.

Picture processing unit 1 includes the CPU interface 21, a moving picture address control circuit 22, a background picture address control circuit 24, a VRAM interface 27 and a color signal generating circuit 28 which are connected to the CPU interface 21 through a data bus 14. An address bus 15 is connected to the moving picture address control circuit 22. The address bus 15 and a further data bus 16 are connected to the background picture address control circuit 24 and the VRAM interface 27. The address bus 15 and the data bus 16 respectively comprise dual address buses 15a and 15b and dual data buses 16a and 16b respectively corresponding to the two VRAMs 7a and 7b. A moving picture data processing circuit 23 and a background picture data processing circuit 25 are together connected to the data bus 16. Video processing relating to the moving picture character symbols is performed by the moving picture address control circuit 22 and the moving picture data processing circuit 23. Video processing concerning the background picture character symbols is performed by the background picture address control circuit 24 and the background picture data processing circuit 25. Outputs of the moving picture data processing circuit 23 and the background picture data processing circuit 25 are applied to a priority control circuit 26. An output of the priority control circuit 26 is converted into an RGB signal by the color signal generator 28 and can be directly applied to the RGB monitor 8a. The priority control circuit 26 above is also converted into an NTSC color television signal by an NTSC encoded 29 and output to the standard television receiving set 8b from an output terminal 43.

The picture processing unit 1 also includes a timing signal generator 30 and an HV counter 31. The timing signal generator 30 generates various timing signals on the basis of a 21.447 MHz clock signal, a vertical synchronization signal and a horizontal synchronization signal output from the reference signal generator 6. The HV counter 31 generates count data H.sub.c and V.sub.c for respectively designating the display positions in the horizontal and vertical directions within a display screen area 41 shown in FIG. 2 in response to the clock signal, the vertical synchronization signal and the horizontal synchronization signal from the reference signal generator 6.

FIG. 2 is a diagram showing the relation between a display screen area of the CRT display 8 and a background picture storage area of the VRAM 7. A display screen area 41 of the CRT display 8 may be constituted by, for example, a rectangle comprising 32 characters in the horizontal direction (breadth; x) and 28 characters in the vertical direction (length; y). If a background picture storage area (referred to as "VRAM area" hereinafter) 40 has no image data of a background picture in a portion which is not visible on a screen when the screen is reduced and displayed, a portion other than the background picture which is actually visible is displayed in black so that a screen having no background appears. Furthermore, in a case where a background picture of the entire screen is scrolled up and down and displayed, if image data of a background picture must be rewritten in real time, smooth scrolling cannot be achieved. Accordingly, the VRAM area 40 is provided having an area several times the display screen area 41 in the vertical and horizontal directions.

In the embodiment shown, the VRAM area 40 has a storage area comprising 128 characters in both the x and y directions (128.times.128=16384) such that the horizontal position and the vertical position can be respectively designated by 7-bit address data. A background character code to be displayed is written in an address designated by respective coordinate data in the x and y directions. Herein, the origin of the VRAM area 40 is set in a left upper end of FIG. 2 and is represented by x=0 and y=0, and the display position of a certain dot on the VRAM area 40 is represented by P(x, y). Further, in order to indicate a position 53 in a left upper end of the display screen area 41, the distances in the x and y direc