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RELATED PATENT APPLICATIONS
Co-pending application U.S. Ser. No. 07/502,147 filed Mar. 30, 1990 and
entitled "FIFO Host Interface for a Logic Simulation Machine". Co-pending
application U.S. Ser. No. 07/502,088 filed Mar. 30, 1990 and entitled
"Broadcast Command for a Logic Simulation Machine". Co-pending application
U.S. Ser. No. 07/502,089 filed Mar. 30, 1990 and entitled "Logic
Simulation Machine, Method of Logic Simulation, and Method of Compiling a
Logic Model for the Machine". All of them are assigned to the same
assignee as the present application.
1. Technical Field
The present invention relates to a logic simulation machine for the
simulation of digital logic, and in particular, to an all events trace
gatherer for the logic simulation machine to generate an all events trace
(AET) which is a record of what has happened to all facilities being
simulated during the simulation.
2. Background of the Invention
Logic technologies such as very large scale integrated circuits provide
significant improvements in cost/performance and reliability. However,
they have disadvantages in that their fault diagnosis is more difficult
than previous technologies and their engineering rework cycles needed to
correct faults in logic design are greatly lengthened. These disadvantages
exact great economic penalties for design errors and omissions and place a
great emphasis on the goal of completely verifying designs in advance of
engineering models.
One technique for providing design verification is logic simulation by a
general purpose computer. Another technique is to use a special purpose
computer that is optimized for logic simulation. The special purpose
computer usually uses a multiple processor architecture by which a number
of processors, called simulation processors, may be interconnected to
improve simulation performance. The special purpose computer may operate
in combination with a host computer which is used to provide loading
functions and to analyze the results of the simulation. Such a special
purpose computer is called a logic simulation machine. The invention
relates to an AET gatherer for the logic simulation machine.
The prior art logic simulation machine is described in U.S. Pat. No.
4,306,286 issued Dec. 15, 1981, to Cocke et al. and assigned in common
with the present application. The logic simulation machine of the Cocke et
al. patent comprises a plurality of parallel basic processors which are
interconnected through an inter-processor switch. The inter-processor
switch provides communication not only among the basic processors which
are computing engines of the logic simulation machine, each simulating the
individual gates of a portion of a logic model in parallel, but also
between them and a control processor which provides overall control and
input/output facilities of the logic simulation machine through a host
computer to which the control processor is attached. Each basic processor
contains the current state information for only the set of gates that is
being simulated by that processor. When a basic processor simulates a gate
whose input includes a connection to the output of a gate being simulated
by a different processor, the state information for the gate in question
is transferred over the inter-processor switch.
An All Event Trace (AET) is a record of what has happened to all of the
facilities during a simulation. The acronym AET is also applied to all
traces including those including only a subset of all facilities. The AET
data is used by a host computer to analyze the simulation.
In the prior art, the AET data is normally collected by having the host
evaluate all of the nodes to be traced at the end of each simulation
cycle. Even with the efficiencies of a Broadcast command to send only
those nodes to the host from a logic simulation machine, two limitations
remain. First, all of the nodes to be traced are sent to the host from the
logic simulation machine, even those that did not change. Second, it
places a considerable time requirement on the host to evaluate the data
every cycle.
DISCLOSURE OF THE INVENTION
Accordingly, it is the primary object of the present invention to provide
an all events trace (AET) gatherer which generates an all events trace
(AET) record in parallel with the simulation without slowing down the
simulation.
It is another object of the invention to provide an AET gatherer which is
an auxiliary processor to be connected in parallel with simulation
processors to a logic simulation machine to provide an efficient means of
collecting an AET.
Also, it is an object of the invention to provide an AET gatherer which
allows any subset of facilities to be collected.
In accordance with these and other objects of the present invention, there
is provided an AET gatherer comprising, a current state array for storing
a complete copy of current states of a whole model being simulated, a
change record array for storing only changes in the current states of the
model at each simulation cycle, and control means for monitoring current
states of the model being simulated to detect a change in the current
states stored in the current state array and store the change into the
change record array at each simulation cycle.
The AET gatherer is connected to a simulation bus on which each of
simulation processors of a logic simulation machine puts a simulated
result in parallel at the end of each simulation cycle in order to monitor
the simulation.
The AET gatherer may contain a memory unit equal in size to the current
state array for tracing any subset of all facilities. The memory unit is
used as a mask to store a bit for indicating the node to be traced.
BRIEF DESCRIPTION OF THE DRAWING
For a more complete understanding of the present invention and further
objects and advantages thereof, reference is now made to the following
Description of the Preferred Embodiments taken in conjunction with the
accompanying Drawings, in which:
FIGS. 1A-1B are an entire schematic block diagram of a logic simulation
machine to which an AET gatherer according to a preferred embodiment of
the present invention is attached.
FIG. 2 is a schematic block diagram of the simulation processor plugged
into the slot 0 in FIG. 1.
FIG. 3 is a schematic diagram showing contents of a block description array
of the simulation processor of FIG. 2.
FIG. 4 is a schematic diagram showing the op-code field of instructions
stored in the block description array of FIG. 3.
FIG. 5 is a schematic block diagram of a simplified logic circuit model
used in explaining a block description instruction and operation of the
simulation processor shown in FIG. 2.
FIG. 6 is a schematic block diagram of a current state array of the
simulation processor of FIG. 2.
FIG. 7 is a detailed schematic block diagram of a part of the simulation
processor of FIG. 2.
FIG. 8 is a schematic block diagram of an outputting means of the
simulation processor of FIG. 2 for putting a result from the logic
function table on allocated data lines of the simulation bus.
FIG. 9 is a simplified illustration of the block description arrays of the
simulation processors in the machine of FIG. 1 to explain operation of the
machine.
FIG. 10 is a simplified illustration of the block description arrays of
another configuration of the logic simulation machine.
FIG. 11 is a schematic block diagram of an all events trace (AET) gatherer
according to a preferred embodiment of the invention, which is connected
by the simulation bus means in parallel with the simulation processors to
the logic simulation machine to generate an all events trace (AET) during
a simulation.
FIG. 12 is a schematic diagram of a 2-bit counter to be simulated by the
machine of FIG. 1 to explain operation of the all events trace (AET)
gatherer of FIG. 11.
FIG. 13 is a table to explain the current states of nodes in the counter of
FIG. 12 at each simulation cycle.
FIG. 14 is a table showing contents of a change record array to explain the
operation of the all events trace (AET) gatherer of FIG. 11.
FIG. 15 is a block diagram showing an all events trace (AET) gatherer
according to a second embodiment of the invention.
BEST MODE FOR CARRYING OUT THE INVENTION
Referring to the block diagram of FIGS. 1A-1B, a logic simulation machine 1
to which an all event trace (AET) gatherer of the invention is attached is
explained. The logic simulation machine 1 which is the subject of the
co-pending application U.S. Ser. No. 07/502,089 filed Mar. 30, 1990
includes plural simulation processors 2 connected to each other in
parallel through a simulation bus means 3. Although four simulation
processors 2 are shown in FIG. 1, the number of the simulation processors
2 connected to the simulation bus means 3 is sixteen and sixteen
processors are a maximum configuration for explanation purpose. However,
any number of simulation processors selected from a group consisting of 1,
2, 4, 8, and 16 is able to be used in the machine 1.
The simulation bus means 3 comprises three parts: data lines 3A through
which each simulation processor 2 transfers a simulated result and each
simulation processor 2 receives the results from all simulation processors
2 to update its own copy of current states when evaluating gates and
through which a host computer 5 transfers packet data to and from the
simulation processors 2 when not evaluating gates; control lines 3B
through which current contents on the data lines 3A are indicated and
arbitration for the bus 3 is done; and configuration lines 3C through
which a unique code is transferred to each of the simulation processors 2
to inform the configuration of the simulation processors. The simulation
bus means 3 further comprises slot means 0, 1, 2, . . . , 15 and n. Each
simulation processor 2 is plugged into the slot means 0, 1, 2, . . . , or
15 for connection with the simulation bus means 3. Each slot means 0, 1,
2, . . . , or 15 of the simulation bus means 3 has a hard wired means 3D
associated with the configuration lines 3C. The number of the
configuration lines 3C depends on how many simulation processors 2 the
logic simulation machine 1 can contain. In this embodiment, the number of
the lines 3C is four to convey a different 4-bit binary data to each of
the sixteen simulation processors. The hard wired means 3D of the slot
means 0 sets all lines of the configuration lines 3C OFF so that the
configuration lines 3C input 4-bit binary zero data 0000 into the
simulation processor 2 plugged into the slot means 0. The hard wired means
3D of the slot means 1 sets the least significant bit line ON and the
other three lines OFF so that the configuration lines 3C input binary data
0001 into the simulation processor 2 plugged into that slot means. The
hard wired means 3D of the slot means 2 sets the second least significant
bit line ON and the other three lines OFF so that the configuration lines
3C input binary data 0010 into the simulation processor 2 plugged into
that slot means and so on. The hard wired means 3D of the slot means 15
sets all lines ON so that the configuration lines 3C input binary data
1111 into the simulation processor 2 plugged into that slot means.
An all events trace (AET) gatherer 4 of the invention which is an auxiliary
processor in the machine 1 is plugged into the slot means n of the bus
means 3 for connection with the simulation bus means 3 in parallel with
the simulation processors 2.
The number of the data lines 3A depends on how many simulation processors 2
the logic simulation machine 1 can contain and how many bits each
simulation processor 2 needs to represent a calculated result. In this
example, the machine 1 can contain up to sixteen simulation processors 2
and each simulation processor 2 calculates a 2-bit result. Therefore, the
number of the data lines 3A is 16.times.2=32. Each of the simulation
processors 2 is allocated two data lines 3A to transfer a result
calculated by that processor to all of the simulation processors 2,
depending upon which slot means that processor 2 occupies as explained
later. The data lines 3A can also be used by the host computer 5 to load
data and instructions into each of the simulation processors 2 and the AET
gatherer 4 before simulation and to receive the results calculated by the
simulation processors 2 and the AET gatherer 4 during the simulation
through a host interface provided in one of the simulation processors 2 as
explained later.
The host computer 5 may be a conventional engineering workstation. The host
computer 5 includes a central processing unit 51, a main memory 52, a disk
file (direct access storage device) 53, a keyboard 54, a display 55, and a
host I/O bus means 56. Each of the simulation processors 2 and the AET
gatherer 4 are connected to the host computer 5 through the I/O bus means
56 by being plugged into slot means (not shown) of the I/O bus means 56.
If the number of the simulation processors 2 exceeds the number of the I/O
slot means provided within the host computer 5, an extension housing may
be used to connect the additional simulation processors to the host
computer 5.
The simulation processors 2 and the AET gatherer 4 are provided on
rectangular cards. Connector (not shown) for the slot (not shown) of the
host I/O bus means 56 is provided at one end of the card on which the
simulation processor 2 or the AET gatherer 4 is mounted. Connector (not
shown) for the slot means 0, 1, . . . , 15 or n of the simulation bus
means 3 is provided at the opposite end of the card. The simulation
processors 2 and the AET gatherer 4 are installed in the host 5 by
directly plugging the connector (not shown) at the one end of the card
into the slot (not shown) of the host I/O bus 56. The simulation bus means
3 connects the simulation processors 2 and the AET gatherer 4 by plugging
the slot means 0 thru n into the connectors (not shown) at the opposite
end of the cards.
Now, referring to FIG. 2, the structure of the simulation processor 2
plugged into the slot means 0 of the simulation bus means 3 is explained.
Other simulation processors 2 have the same structure except a host
interface 21. Each simulation processor 2 has seven primary elements: a
first memory unit, such as a block description array 22; a second memory
unit, such as a current state array 23; a logical function table 24; an
outputting means 25; a bus steering means 80; a program counter 26; and a
control logic means 27.
The block description array 22 is an instruction memory for the simulation
processor 2 which contains all of the information necessary to specify
operations of that simulation. FIG. 3 shows contents of the block
description array 22. An instruction stored at one address in the array 22
contains an op-code field (16 bits), A1, A2, A3, and A4 fields (each 24
bits in this embodiment). There are two kinds of instructions determined
by the op-code field as shown in FIG. 4, that is, a block description
instruction having a binary one at a first bit position of the op-code
field for evaluating a gate and a control instruction having a binary zero
at the first bit position of the op-code field for controlling operation
of that simulation processor.
As to the block description instruction, one instruction word corresponds
to each logical block or gate in a model to be simulated. The instruction
word's address represents a block or gate identifier. The instruction
contains the op-code fields to specify a logical function of the gate,
such as AND or OR, and four fields A1, A2, A3 and A4, to specify input
connections or input operands of the gate. Thus, a block description
instruction corresponds to a single 1-output, 4-input gate. The logical
function of the gate is determined by an 8-bit function pointer FFFFFFFF
in the op-code which is an index to the logical function table 24.
Input/output inversion can be done independent of the logical function
table 24 by inversion bits I1, I2, I3, I4, and I0 in the op-code. The
fields A1, A2, A3, and A4 represent addresses in the current state array
23 where the four input operands are stored. The block description
instruction's address in the block description array 22 implies its output
address in the current state array 23 where the calculated result is to be
stored. The size of the block description array 22 depends on a desired
capacity of the simulation processors 2. In this embodiment, the array 22
can store up to 512K block description instructions.
FIG. 5 shows an example of a gate to be simulated by the simulation
processor 2 in order to illustrate the block description instruction shown
at an address Z in FIG. 3. An AND gates is identified by a numeral Z which
corresponds to an address in the block description array 22 where the
block description instruction of the gate is stored. The AND function
pointer and the invert functions of the gate are stored in the op-code
field of the instruction. Input connections V, W, X, and Y of this gate
are stored in the fields A1, A2, A3 and A4 of the instruction. The current
state array 23 stores input operands of the gate Z at addresses V, W, X,
and Y designated by the fields A1, A2, A3, and A4.
As to control instructions, the op-code field specifies a control function
executed by the simulation processors. As shown in FIG. 4, Halt means to
stop the simulation to wait for host interaction. Broadcast means to send
any packet of data to the simulation bus means 3 for use by the host
and/or an auxiliary processor connected to the simulation bus 3. Branch
means to go to an instruction stored in the address designated by the
fields A2 and A3.
Referring to FIG. 6, the current state array 23 is explained. The current
state array 23 is a memory which stores a complete copy of current states
of a whole model being simulated. The state of each block or gate is
specified by 2 bits. The possible states are logical 0 (00), logical 1
(01), Undefined (10) and High Impedance (11). The current state array 23
stores such current states of all blocks or gates of the machine being
simulated. There are 512K possible blocks or gates in the machine being
simulated in this embodiment, so the state of the machine being simulated
is contained in 1M bits. The current state array 23 must have 1M bit
capacity at least. In this example, however, the current state array 23 is
larger to achieve maximum performance. In the computation for a given
block or gate, the contents of the current state array 23 are
simultaneously addressed by the four fields A1, A2, A3 and A4. It is
preferred to read the current states of four different blocks or gates
simultaneously. Therefore, the array 23 is replicated 4 times. When
reading the array 23, four different addresses can be read simultaneously.
When writing the array 23, the same addresses in all four arrays are
always written. That is, when the current state array 23 is read, the
multiplexors 62 are controlled through an address selection by the control
logic means 27 to output addresses A1, A2, A3, and A4 to each array. Then,
each array outputs a 2-bit operand to an operand invert logic means 63.
Each of the outputted operands may be inverted by the inversion bit of the
op-code in the means 63 before calculation in the logical function table
24. When the current state array 23 is written, the multiplexors 62 are
controlled through the address selection by the control logic means 27 to
output one address A0. Then, the same data is written into the four arrays
at the same address A0. Of course, this could been done using a single
array and time-slicing, but at the expense of roughly 4 times performance.
Furthermore, another 4 arrays are added in the example shown in FIG. 6.
For unit delay simulation, the state of the machine being simulated need
to be saved in a "master-slave" arrangement. That is, the complete next
state of the machine needs to be computed before this becomes the current
state of the machine. The simplest way to implement this is with two
memory (A and B) operating in a ping-pong arrangement. When A contains the
current state, B will be used to save the next state. When B contains the
current state, A is used to save the next state.
Referring to FIG. 7, the logical function table 24 is explained. The
logical function table 24 is a programmable logic block whose main element
is a memory 65, a 64K.times.2 bit static RAM, indexed by the 8-bit
function pointer in the op-code field plus the four 2-bit input operands
form the operand invert logic 63. The logical function table 24 generates
a 2-bit output, which is the next state of the gate being evaluated. The
RAM 65 is also accessible to the host computer 5 through a multiplexor 67,
which needs to load it with a set of logical functions prior to beginning
of the simulation. The logical function table 24 is in essence a look up
table which generates a 2-bit output with respect to a given gate function
and four input operands. The output of the logic function table 24 is
supplied to the outputting means 25 through an output invert logic means
66. The output from the table 24 may be inverted in the output invert
logic means 66 by the inversion bit of the op-code before being put on the
allocated lines of the data lines 3A through the outputting means 25. The
outputs from the operand invert logics 63 are also supplied to the bus
steering means 80. When the Broadcast command is executed by the control
logic 27, the bus steering means 80 receives four current states
designated by A1 thru A4 fields of the command from the current state
array 23 through the operand invert logics 63 and puts eight bit data on
the data lines 0 thru 7, 8 thru 15, 16 thru 23, or 24 thru 31 under the
control of the control logic 27. The data in the current state array 27
are sent to the host 5 by the Broadcast command from the simulation
processors 2 for use in the host 5. The Broadcast command is the subject
of the co-pending application U.S. Ser. No. filed and having internal
docket No. AT9-89-098.
Referring to FIG. 8, the outputting means 25 is explained. The outputting
means 25 comprises 16 AND gates E0, E1, . . . , and E15, 16 gates L0, L1,
. . . , and L15 whose outputs are connected to the even number lines 0, 2,
. . . , and 30 of the data lines 3A, respectively, and 16 gates H0, H1, .
. . , and H15 whose outputs are connected to the odd number lines 1, 3, .
. . , and 31 of the data lines 3A, respectively. The configuration lines
3C which are connected to the hard wired means 3D and the control logic
means 27 are connected to inputs of the AND gates E0, E1, . . . , and E15.
All inputs from the lines 3C to the gate E0 are inverted so that only the
4-bit binary data 0000 on the lines 3C can activate the gate E0. An input
from the least significant bit line of the lines 3C is directly connected
to the gate E1 and the other three inputs from the lines 3C to the gate E1
are inverted so that only the 4-bit binary data 0001 can activate the gate
E1 and so on. All inputs from the lines 3C are directly connected to the
gate E15 so that only the 4-bit binary data 1111 on the lines 3C can
activate the gate E15. A running mode signal from the control logic 27 is
also connected to input of each of the AND gates E0, E1, . . . , and E15
to activate the AND gates during running mode of the simulation processors
2. Outputs of the AND gates E0, E1, . . . , and E15 are connected to
enable terminals of the gates L0 and HO, L1 and H1, . . . , and L15 and
H15, respectively. The low bit line of the output from the output invert
logic means 66 is connected to inputs of the gates L0, L1, . . . , and
L15. The high bit line of the output from the output invert logic means 66
is connected to inputs of the gates H0, H1, . . . , and H15. Accordingly,
the simulation processors 2 plugged into the slot means 0, 1, 2, . . . ,
and 15 put their calculated results on the lines 0 and 1, lines 2 and 3,
lines 4 and 5, . . . , and lines 30 and 31 of the data lines 3A through
the outputting means 25, respectively. Thus, each simulation processor 2
is allocated two of the data lines 3A to put its result thereon, depending
on which slot means of the simulation bus 3 that processor 2 occupies.
Referring back to FIG. 2, the control logic means 27 controls a clock means
68 so that all of the simulation processors 2 connected with the
simulation bus means 3 synchronously execute their operations. The control
logic means 27 controls the program counter 26 so that the program counter
26 generates addresses to output instructions from the block description
array 22 and addresses to write the calculated results from all of the
simulation processors 2 back into the current state arrays 23. The control
logic means 27 control the control instructions, such as Branch,
Broadcast, and Halt. The control logic means 27 also controls the
simulation processor 2 to load the block description array 22 with
instructions and the current state array 23 with initial states from the
host computer 5 before simulation.
In addition, the simulation processor 2 occupying the slot 0 contains the
host interface 21 to transfer data and instructions between the host 5 and
the simulation processors 2. The host interface 21 is a First-In First-Out
buffer to buffer data between the simulation bus means 3 and the host I/O
bus means 56. When packet data comes from the host through the host
interface 21, each of the simulation processors 2 takes its data off the
simulation bus means 3. When packet data are sent to the host, control
logic in the host interface 21 determines, by the contents of the control
lines 3B, that the data on the data lines 3A is intended for the host and
transfers the data to the host 5. The host interface means 21 allows the
user to initialize the block description arrays 22 and the current state
arrays 23 at the beginning of the simulation and test results at the end
of the simulation. It may also allow the user to read and modify the
contents of the current state arrays 23 during the simulation for enhanced
simulation capability. The host interface is the subject of the co-pending
application U.S. Ser. No. 07/502,147 filed on Mar. 30, 1990.
Now, referring back to FIGS. 1 and 2, the operation of the logic machine 1
is explained. The host computer 5 is used to personalize the simulation
processors 2 on power-on operation, to load the simulation processors 2
with instructions and data before the simulation, to evaluate the results
during and/or after the simulation, and to interface with user. The host
computer 5 personalizes each of the simulation processors 2 directly
through the I/O bus means 56. On personalization, the host counts the
number of the simulation processors 2 plugged into the I/O slots and tells
the simulation processors 2 the number. After the personalization,
however, the host does not need to take care of the configuration of the
simulation processors 2 as explained later. After the personalization, the
host computer 5 communicates with the simulation processors 2 only through
the host interface 21 provided in the simulation processor 2 plugged into
the slot 0 of the simulation bus means 3 except power supply through the
I/O slot.
When loading the instructions into the block description array 22 of each
of the simulation processors 2, the host computer 5 sends instructions to
the simulation bus means 3 through the I/O bus 56 and the host interface
21. Each simulation processor 2 takes by turns the instructions and stores
them into the block description array 22. Thus, as shown in FIG. 9, the
simulation processors 2 plugged into the slot means 0, 1, . . . , and 15
store consecutively the block description instructions for gates 0, 16,
32, . . . , gates 1, 17, 33, . . . , and gates 15, 31, 47, . . . , in
their block description arrays 22, respectively, and store the same
control instructions at the same addresses in the block description arrays
22.
Referring back to FIGS. 1 and 2 again, the host computer 5 loads the same
initial states of a whole model to be simulated by the machine 1 into the
current state array 23 in each of the simulation processors 2. In the
embodiment, the current state array 23 in each simulation processor 2
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