Dual port semiconductor memory device with high speed data transfer during reading and writing modes

What is claimed is:

1. A semiconductor memory device comprising:

a first memory array having a plurality of first memory cells arranged in a plurality of columns,

a second memory array for temporarily storing a read out data signal from said first memory array and write data signal to be written into said first memory array, said second memory array including a plurality of second memory cells provided corresponding to said plurality of columns,

wherein each of said second memory cells includes

first and second complementary storage nodes,

bidirectional inverting means interconnecting said first and second storage nodes;

means for limiting magnitude of current flow within said inverting means in one direction to be less than that within said inverting means in the opposite direction,

data bus means for receiving a data signal read out from said second memory cell and an externally applied data signal,

read out means for reading out a data signal from one of said plurality of first memory cells,

amplifying means for reading and amplifying both a data signal read out by said read out means and a data signal temporarily stored in each second memory cell,

first connecting means for electrically connecting one node of said complementary storage nodes to said amplifying means at the time of data reading and data writing,

second connecting means, for electrically connecting the other one of said complementary storage nodes to said data bus means, after said one node is electrically connected to said amplifying means by said first connecting means, at the time of said data reading, and

third connecting means for electrically connecting said one node to said data bus means, before said one node is electrically connected to said amplifying means by said first connecting means, at the time of said data writing.

2. A semiconductor memory device comprising:

a first memory array having a plurality of first memory cells arranged in a plurality of columns,

a second memory array for temporarily storing a readout data signal from said first memory array and a write data signal to be written into said first memory array, said second memory array including a plurality of second memory cells provided corresponding to said plurality of columns,

wherein each second memory cell includes

a first node,

a second node,

first inverting means for inverting the potential of said first node to provide the same to said second node,

second inverting means for inverting the potential of said second node to provide the same to said first node, the drive capability of said first inverting means being greater than that of said second inverting means,

data bus means for receiving both a data signal readout from said second memory cell and an externally applied data signal,

readout means for reading out a data signal from one of said plurality of first memory cells,

amplifying means for sensing and amplifying both a data signal readout by said readout means and a data signal temporarily stored in said each second memory cell,

first connecting means for electrically connecting each first node to said amplifying means at the time of data reading and data writing,

second connecting means for electrically connecting and disconnecting said each second node to and from said data bus means during data reading and data writing, respectively,

third connecting means for electrically connecting and disconnecting said each first node to and from said data bus means during data writing and data reading respectively, and

first and second control signal generating means generating control signals for controlling said second and third connecting means,

said first control signal generating means generating a first control signal for controlling the second connecting means to connect the second node to said data bus means during data reading and to isolate the second node from said data bus during data writing,

said second control signal generating means generating a second control signal for controlling the third connecting means to connect the first node to said data bus means during data writing and to isolate the first node from said data bus means during data reading.

3. The semiconductor device according to claim 2, wherein

said first inverting means comprises first and second field effect semiconductor elements having complementary polarities connected in series between a high potential power supply and a low potential power supply,

said second inverting means comprises third and fourth field effect semiconductor elements connected in series between said high potential power supply and said low potential power supply, and having a polarity identical to that of said first field effect semiconductor element and a polarity identical to that of said second field effect semiconductor element, respectively,

the drive capability of said first field effect semiconductor element is greater than that of said third field effect semiconductor element,

the size of said second field effect semiconductor element is larger than that of said fourth field effect semiconductor element.

4. The semiconductor memory device according to claim 2, wherein

said first inverting means comprises a plurality of inverters connected between said first node and said second node in parallel to each other, and

said second inverting means comprises a single inverter connected between said first node and said second node in anti-parallel to said plurality of inverters.

5. The semiconductor memory device according to claim 2, wherein

said first memory array further comprises first and second bit lines provided corresponding to each of said plurality of columns,

said data signal stored in each first memory cell is read out by said readout means to said first and second bit lines corresponding to said columns in which it is arranged,

said amplifying means comprises a plurality of differential amplifying means provided corresponding to said plurality of columns.

6. The semiconductor memory device according to claim 5, wherein

each of said plurality of differential amplifying means comprises

first and second signal lines,

fifth and sixth field effect semiconductor elements of complementary polarity, provided between said first signal line and the corresponding said first bit line, and between said second signal line and the corresponding said first bit line, respectively, and controlled according to the potential of the corresponding said second bit line,

seventh and eight field effect semiconductor elements of complementary polarity, provided between the corresponding said second bit line and said first signal line and between the corresponding said second bit line and said second signal line, respectively, and controlled according to the potential of the corresponding said first bit line,

the polarity of said seventh field effect semiconductor element is identical to that of said fifth field effect semiconductor element,

the polarity of said eight field effect semiconductor element is identical to that of said sixth field effect semiconductor element,

said first and second signal lines are applied with a high potential and a low potential, respectively, after said first node and said amplifying means are electrically connected by said first connecting means, at the time of said data writing,

said first and second signal lines are applied with said high potential and said low potential, respectively, before said first node is electrically connected to said amplifying means, at the time of said data reading.

7. The semiconductor memory device according to claim 6, wherein

said first connecting means comprises a plurality of ninth field effect semiconductor elements provided corresponding to said plurality of columns,

each of said plurality of ninth field effect semiconductor elements are connected between the corresponding said differential amplifying means and said first node of the corresponding said second memory cell, and controlled to conduct only at the time of said data writing and said data reading.

8. The semiconductor memory device according to claim 7, wherein

said second connecting means comprises a plurality of tenth field effect semiconductor elements provided corresponding to said plurality of columns,

each of said plurality of tenth field effect semiconductor elements is provided between said second node of the corresponding said second memory cell and said data bus means, and controlled to conduct after the corresponding said ninth field effect semiconductor elements is conductive, at the time of said data reading.

9. The semiconductor memory device according to claim 8, wherein

said third connecting means comprises a plurality of eleventh field effect semiconductor elements provided corresponding to said plurality of columns, each of said plurality of eleventh field effect semiconductor elements is provided between said first node of the corresponding said second memory cell and said data bus means, and controlled to conduct before the corresponding said ninth field effect semiconductor element is conductive, at the time of said data writing.

10. The semiconductor memory device according to claim 7, wherein

said third connecting means comprises a plurality of eleventh field effect semiconductor elements provided corresponding to said plurality of columns, each of said plurality of eleventh field effect semiconductor elements is provided between said first node of the corresponding said second memory cell and said data bus means, and controlled to conduct before the corresponding said ninth field effect semiconductor element is conductive, at the time of said data writing.

11. The semiconductor memory device according to claim 7, wherein said plurality of ninth field effect semiconductor elements conduct simultaneously.

12. The semiconductor memory device according to claim 8, wherein each of said plurality of tenth field effect semiconductor elements conducts sequentially over time.

13. The semiconductor memory device according to claim 9, wherein each of said plurality of eleventh field effect semiconductor elements conducts sequentially over time.

14. The semiconductor memory device according to claim 10, wherein each of said plurality of eleventh field effect semiconductor elements conducts sequentially over time.

15. The semiconductor memory device according to claim 1, wherein said data bus means comprises a single signal line.

16. The semiconductor memory device according to claim 2, wherein said data bus means comprises a single signal line.

17. The semiconductor memory device according to claim 9, wherein said data bus means comprises a single signal line.

18. The semiconductor memory device according to claim 1, wherein

said plurality of first memory cells are arranged also in a plurality of rows in said first memory array,

said first memory array further comprises a plurality of word lines provided corresponding to said plurality of rows,

each of said first memory cells comprises a twelfth field effect semiconductor element and a capacitance coupling element, connected in series between one of said first and said second bit lines corresponding to said column in which it is arranged and the low potential power supply,

each of said twelfth field effect semiconductor element of said first memory cells arranged along the same said row is controlled by the potential of said word line corresponding to said same row.

19. The semiconductor memory device according to claim 2, wherein

said plurality of first memory cells are arranged also in a plurality of rows in said first memory array,

said first memory array further comprises a plurality of word lines provided corresponding to said plurality of rows,

each of said first memory cells comprises a twelfth field effect semiconductor element and a capacitance coupling element, connected in series between one of said first and said second bit lines corresponding to said column in which it is arranged and the low potential power supply,

each of said twelfth field effect semiconductor element of said first memory cells arranged along the same said row is controlled by the potential of said word line corresponding to said same row.

20. The semiconductor memory device according to claim 17, wherein

said plurality of first memory cells are arranged also in a plurality of rows in said first memory array,

said first memory array further comprises a plurality of word lines provided corresponding to said plurality of rows,

each of said first memory cells comprises a twelfth field effect semiconductor element and a capacitance coupling element, connected in series between one of said first and said second bit lines corresponding to said column in which it is arranged and the low potential power supply,

each of said twelfth field effect semiconductor element of said first memory cells arranged along the same said row is controlled by the potential of said word line corresponding to said same row.

21. A method of operating a semiconductor memory device comprising:

a first memory array having a plurality of first memory cells arranged in a plurality of columns,

a second memory array for temporarily storing a read out data signal from said first memory array and a write data signal to be written into said first memory array, said second memory array including a plurality of second memory cells provided corresponding to said plurality of columns,

wherein each second memory cell includes first and second mutually complementary storage nodes,

data bus means for receiving a data signal read out from said second memory cell and an externally applied data signal,

read out means for reading out a data signal from one of said plurality of first memory cells,

amplifying means for sensing and amplifying both a data signal read out by said read out means and a data signal temporarily stored in each of said second memory cell,

the method comprising the steps of:

electrically connecting each first node to said amplifying means during data reading and data writing,

electrically connecting each second node to said data bus means during data reading and electrically isolating said each second node from said data bus means during data writing, and

electrically connecting said each first node to said data bus means during data writing and electrically isolating said each first node from data bus means during data reading.

22. A semiconductor memory device comprising:

a first memory array having a plurality of first memory cells arranged in a plurality of columns;

a second memory array for temporarily storing a read out data signal from said first memory array and a write data signal to be written into said first memory array, said second memory array including a plurality of second memory cells provided corresponding to said plurality of columns,

wherein each of said second memory cells includes

first and second complementary storage nodes,

bidirectional inverting means interconnecting said first and second storage nodes,

means for limiting magnitude of current flow within said inverting means in one direction to be less than that within said inverting means in the opposite direction,

data bus means for receiving a data signal read out from said second memory cell and an externally applied data signal,

read out means for reading out a data signal from one of said plurality of first memory cells,

sense amplifier means for sensing and amplifying a data signal read out by said read out means and a data signal temporarily stored in each second memory cell,

first connecting means for electrically connecting one node of said complementary storage nodes to said sense amplifier means at the time of data reading and data writing,

second connecting means, for electrically connecting and disconnecting the other one of said complementary storage nodes to and from said data bus means during data reading and data writing, respectively,

third connecting means for electrically connecting and disconnecting said one node to and from said data bus means during data writing and data reading, respectively,

first and second control signal generating means for generating control signals for controlling said second and third connecting means,

said first control signal generating means generating a first control signal for controlling the second connecting means to connect said other node to said data bus means during data reading and to isolate said other node from said data bus during data writing,

said second control signal generating means generating a second control signal for controlling the third connecting means to connect said one node to said data bus means during data writing and to isolate said one node from said data bus means during data reading.

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BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to semiconductor memory devices, and more particularly, to a semiconductor memory device such as a dual port memory comprising two types of memory arrays carrying out data transmission/reception between each other.

2. Description of the Background Art

In accordance with the multifunction and high performance of video equipments, high performance is also required by semiconductor memory devices for storing video signals as digital data, i.e. required by semiconductor memory devices for video such as video RAMs (Random Access Memory). A dual port memory is a semiconductor memory device that has the function to read and write in parallel and in series a plurality of data, employed as the semiconductor memory device for video.

FIG. 6 is a block diagram schematically showing the entire structure of a conventional dual port memory. The structure and operation of the conventional dual port memory will be explained hereinafter with reference to FIG. 6. In the following description, H level and L level correspond to power potential and ground potential, respectively.

Referring to FIG. 6, a conventional dual port memory 1 comprises a memory array 2 having a plurality of memory cells MC each formed of one MOS transistor TR and one capacitor C arranged in a matrix of rows and columns; a sense amplifier portion 3, a serial register 4, a serial bus line 5, a serial decoder 6, a counter 7, a serial data output terminal SDO, and a serial data input terminal SDI all provided for writing to and reading from memory array 2 a plurality of data in series; a row address buffer 11, a column address buffer 12, a row decoder 13, a column decoder 14, a data bus line 15, a parallel data output terminal PDO, and a parallel data input terminal PDI all provided for writing to and reading from memory array 2 a plurality of data in parallel.

Row address buffer 11 buffers address data AX0=AX7 of 8 bits, for example, forming an external row address signal AX to provide the same to row decoder 13. Similarly, column address buffer 12 buffers address data AY0-AY7 of 8 bits, for example, forming an external column address signal AY to provide the same to row decoder 14. Row decoder 3 is connected to all word lines WL included in memory array 2. Column decoder 14 is connected to all bit lines BL included in memory array 2 via data bus line 15. In memory array 2, the gates of respective transistors TR of the memory cells MC arranged along one row are connected to the same word line WL. The drains of respective transistors TR of the memory cells MC arranged along one column are connected to the same bit line BL.

Row decoder 13 applies a potential of H level only to the word line WL corresponding to the row specified by row address signals AX0-AX7 from row address buffer 11 (referred to as the selected word line hereinafter), out of all the word lines WL in memory array 2. This causes transistor TR in each memory cell MC arranged in the row selected by external row address signal AX to conduct, whereby capacitor C is electrically connected to bit line BL corresponding to the relative memory cell MC. Column decoder 14 electrically connects a plurality of bit lines BL corresponding to the column selected by column address signals AY0-AY7 from column address buffer 12 (referred to as the selected bit line hereinafter), out of the bit lines BL in memory array 2, to parallel data output terminal PDO and parallel data input terminal PDI via data bus line 15. Parallel data input terminal PDI is applied with parallel data of a predetermined bit length as the write data from an external source at the time of data writing. Parallel data output terminal PDO provides the output of data bus line 15 in parallel to an external source as the read out data at the time of data reading.

By the above described operations of row decoder 13 and column decoder 14, each capacitor C of memory cell MC connected to the selected word line WL and the selected bit line BL is charged or discharged according to the write data provided in parallel to parallel data input terminal PDI, at the time of data writing. As a result, the potential of the node of transistor TR and capacitor C in each memory cell MC connected to the selected word line WL and the selected bit line BL attains a potential of H level or L level according to the write data. That is to say, data is written simultaneously to all the memory cells MC of one row connected to the selected word like WL.

At the time of data reading, the potential of parallel data output terminal PDO is determined according to the potential of the node of transistor TR and capacitor C of each memory cell MC connected to the selected word line WL and selected bit line BL. That is to say, the stored data in the memory cells MC connected to the selected bit line BL and the selected word line WL appears at parallel data output terminal PDO via the corresponding bit line BL and data bus line 15. Thus, at the time of data reading, the stored data of the memory cells MC of one row connected to the selected word line WL are provided simultaneously from parallel data output terminal PDO.

The foregoing is the operation for writing and reading parallel data in the dual port memory. The operation of reading and writing serial data in a dual port memory will be explained hereinafter.

Row address buffer 11 and row decoder 13 operate in a manner similar to the case of parallel data writing and reading. Accordingly, the potential of only one word line WL selected from word lines WL in memory array 2 attains an H level. Column address buffer 12 responds to external column address signals AY0-AY7 for providing serial address signals SA0-SA7 of 8 bits, for example, for specifying each of the plurality of columns specified by column address signals AY0-AY7. Then, counter 7 responds to serial address signals SA0-SA7 for providing to serial decoder 6 serial column address signals SY0-SY7 of 8 bits, for example, for specifying sequentially one by one the columns of the address specified by external column address signal AY.

At the time of data reading, sense amplifier portion 3 amplifies the potential change generated at each bit line BL in memory array 2 and provides the same simultaneously to serial register 4. Serial register 4 temporarily stores the amplified output of sense amplifier portion 3 at the time of data reading. Serial decoder 6 controls electrical connection between serial bus line 5 and serial register 4 so that serial bus line 5 is provided with only the amplified output of the potential change generated at the bit lines BL corresponding to the columns selected by serial column address signals SY0-SY7 from counter 7, out of the temporarily stored amplified output in serial register 4. Serial column address signals SY0-SY7 provided from counter 7 specifies in time sequence the columns in memory array 2 one by one. This causes the amplified output of sense amplifier portion 3, temporarily stored in serial register 4, to be transferred one at a time to serial data output terminal SDO via serial bus line 5, at the time of data reading. At the time of data reading, a potential change corresponding to the potential of the node between transistor TR and capacitor C in each memory cell MC connected to the selected word line WL and the selected bit line BL is generated at the corresponding bit line BL. Accordingly, the stored data in memory cells MC along one row connected to the selected word line WL are provided one by one from serial data output terminal SDO sequentially to an external source.

At the time of data reading, a plurality of data to be written into all the memory cells MC connected to one word line WL in memory array 2 are applied serially from an external source as an H or L voltage signal to serial data input terminal SDI. These plurality of data are provided to serial bus line 5 one by one in time sequence. Serial decoder 6 controls the electrical connection between serial bus line 5 and respective bit lines BL in memory array 2, so that each data provided to serial bus line 5 is applied only to one bit line BL specified by serial column address signals SY0-SY7 from counter 7 via serial register 4 and sense amplifier portion 3, at the time of data writing. Serial column address signals SY0-SY7 provided from counter 7 specify the columns in memory array 2 one by one in time sequence. At the time of data writing, a plurality of data applied to serial data input terminal SDI from an external source are provided to bit line BL to which memory cells MC that will store the data are connected. As a result, external data are written into memory cells MC of one row connected to selected word line.

In addition to the above described functional components, the dual port memory comprises a clock generating circuit 16. Clock generating circuit 16 generates various clock signals controlling the operation timing of the above described components so that the above described circuit operations for reading and writing parallel data and serial data are implemented correctly, according to external control signals RAS, CAS, SC, DT. For example, the circuit operation for reading and writing serial data is controlled by an internal serial clock signal SC generated from clock generating circuit 16 in response to an external serial clock signal SC.

FIG. 7 indicates the circuit configuration of memory array 2, sense amplifier portion 3, serial register 4, and serial bus line 5.

Referring to FIG. 7, sense amplifier portion 3 comprises differential amplification type sense amplifiers 30. The number of sense amplifiers 30 is a half of the numbers of bit lines BL in memory array 2. Each sense amplifier 30 has two bit lines BL of memory array 2 connected. In memory array 2, the two bit lines BL connected to each sense amplifier 30 form one bit line pair attaining complementary potentials at the time of data reading and writing. The memory cells MC connected to one bit line BIT out of the two bit lines forming one bit line pair and the memory cells MC connected to the other bit line BIT are connected to different word lines WL. At the time of serial data reading, sense amplifier 30 amplifies the potential difference between one bit line BIT and the other bit line BIT.

FIG. 8 is a circuit showing a structure of sense amplifier 30. Referring to FIG. 8, sense amplifier 30 comprises a P channel MOS transistor 310 and an N channel MOS transistor 320 having the gates thereof connected to bit line BIT; and a P channel MOS transistor 330 and an N channel MOS transistor 340 having the gates thereof connected to bit line BIT. Transistor 310 and 320 are connected in series between signal lines 350 and 360. Similarly, transistors 330 and 340 are connected in series between signal lines 350 and 360. At the time of serial data reading and writing, power potential and ground potential are applied to signal lines 350 and 360, respectively. Therefore, at the time of serial data reading, if memory cell MC connected to the selected word line WL is connected to bit line BIT, and the potential of the node of transistor TR and capacitor C in this memory cell MC attains an H level, a slight charge is applied from capacitor C to bit line BIT, whereby the potential of bit line BIT rises according to this slight charge. In initiating data reading, bit line BIT and bit line BIT are equalized so that the potentials of bit line BIT and bit line BIT are identical. The potential rise in bit line BIT causes the generation of slight potential difference between bit line BIT and bit line BIT. Sense amplifier 30 operates to increase this potential difference between bit lines BIT and BIT.

More specifically, the potential rise of bit line BIT causes transistor 320 to become slightly conductive. As a result, there are potential drops in the gate node of transistors 330 and 340 and node d. In response to this potential drop, transistor 330 also becomes slightly conductive to generate potential rise in the gate node of transistors 310 and 320 and node c. Transistor 320 becomes heavily conductive by this potential rise to pull down the potentials of the gate node of transistors 330 and 340 and node d to the ground potential applied to signal line 360. Because transistor 330 also becomes heavily conductive in response, the potential of nodes c rises to the power potential applied to signal line 350. The potential of node d of transistors 310 and 320 and the potential of node c of transistors 330 and 340 are the output of sense amplifier 30. Thus, the potential of bit line BIT is pulled down to the power potential by sense amplifier 30 and applied to serial register 4. The potential of bit line BIT is pulled down to the ground potential by sense amplifier 30 and applied to serial register 4.

On the contrary, if memory cell MC connected to the selected word line WL is connected to bit line BIT, and the potential of the node of transistor TR and capacitor C of this memory cell MC attains an L level, slight charge is provided to this capacitor C from bit line BIT. Accordingly, the potential of bit line BIT drops according this slight charge. This causes transistor 310 to become slightly conductive in sense amplifier 30 to raise the potential of the gate node of transistors 330 and 340. In response, transistor 340 also becomes slightly conductive to drop the potential of the gate node of transistor 310 and 320. As a result, transistors 310 and 340 become heavily conductive, whereby the potential of node c is pulled down to the ground potential and the potential of node d is pulled up to the power potential.

Hence, the slight potential difference between bit lines BIT and BIT is amplified to the differential voltage between the power potential and the ground potential by sense amplifier 30. When memory cells MC connected to the selected word line WL are connected to bit lines BIT, the potential difference between bit lines BIT and BIT is amplified by either transistor 330 or 340 rendered conductive in each sense amplifier 30 since there is slight potential rise or drop in bit line BIT.

Referring to FIG. 7 again, serial register 4 comprises a plurality of flipflops 40 each provided corresponding to each sense amplifier 30. Flipflop 40 is connected to the corresponding sense amplifier 30 via two N channel MOS transistors 150 and 160. Flipflop 40 comprises two inverters 410 and 420 having each input and output terminal thereof connected to each other. As shown in FIG. 8, sense amplifier 30 comprises an output end (node c) of the bit line BIT side and an output end (node d) of the bit line BIT side. The output end of the bit line BIT side is connected to the input end of inverter 420 via transistor 150, and the output end of bit line BIT side is connected to the input end of inverter 410 via transistor 160. The gates of transistors 150 and 160 connected to all flipflops 40 in serial register 4 have the same activation signal applied. At the time of serial data reading and writing, this activation signal attains an H level to conduct transistors 150 and 160.

At the time of serial data reading, the outputs of the bit line BIT side and the bit line BIT side of sense amplifier 30 are latched at node a of the input end of inverter 420 and the output end of inverter 410, and node b of the input end of inverter 410 and the output end of inverter 420, respectively, in the corresponding latch circuit 40.

Serial bus line 5 comprises two data lines 100 and 110. Serial register 4 is connected to serial bus line 5 via separate N channel MOS transistors 120 and 130 for each flipflop 40. Data line 100 is connected to the input end of inverter 420 via transistor 120. Data line 110 is connected to the input end of inverter 410 via transistor 130. The gates of transistors 120 and 130 provided corresponding to each flipflop 40 are connected to serial decoder 6 via a common serial memory cell activation signal line 140. At the time of serial data reading and writing, serial decoder 6 provides a potential of the H level sequentially to each serial memory cell activation signal line 140. Therefore, at the time of serial data reading, the potential latched at node a and the potential latched at node b are transferred to data lines 100 and 110, respectively, for every flipflop 40 in serial register 4. The circuit operation of this transfer will be explained more specifically with reference to FIG. 9. FIG. 9 is a circuit diagram specifically showing the structure of flipflop 40.

Referring to FIG. 9, inverter 410 in flipflop 40 comprises a P channel MOS transistor 410a and an N channel MOS transistor 410b connected in series between power supply VC and ground GND. Similarly, inverter 420 comprises a P channel MOS transistor 420a and an N channel MOS transistor 420b connected in series between power supply VC and ground GND. At the time of serial data reading, transistors 120 and 130 are conductive when potential of an H level is applied to signal line 140. Data lines 100 and 110 are equalized to have identical potential to each other until a potential of the H level is applied to signal line 140. Data lines 100 and 110 are unequalized when potential of an H level is applied to signal line 140.

Therefore, if an H level potential and an L level potential are latched at nodes a and b, respectively, discharge is initiated from data line 110 towards ground GND via transistors 130 and 420b. This reduces the potential of data line 110 from the equalized potential (the H level). The potential of data line 110 is held at the potential (the H level) by potential of H level of node a. Thus, there is potential difference between data lines 100 and 110.

If an L level potential and an H level potential are latched at nodes a and b, respectively, discharge is initiated in data line 100 towards ground GND via transistors 120 and 410b. There is no discharge in data line 100. Therefore, the potential of data line 100 is held at the H level and the potential of data line 110 drops from the H level to generate potential difference between data lines 100 and 110.

Thus, at the time of serial data reading, there is potential difference between data lines 100 and 110 according to the latched data of flipflop 40. At the time of serial data reading, potential difference is sequentially generated between data lines 100 and 110 according to data temporarily stored in respective flipflops 40 in serial register 4. This potential difference is sensed and amplified by a sense amplifier not shown. The sensed and amplified signal of this sense amplifier is provided from serial data output terminal SDO in FIG. 6 as the readout data.

The description of operation of