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Description  |
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TECHNICAL FIELD OF THE INVENTION
The invention relates generally to electronic testing, and more
particularly to in-circuit, at-speed testing of electronic systems that
use ASICs (Application Specific Integrated Circuits).
BACKGROUND OF THE INVENTION
Many of today's electronic systems are designed with highly complicated
integrated circuits (ICs) such as: (1) high-level microprocessors, and (2)
"intelligent" peripheral devices. Such electronic systems may be called
the "target environment" for these integrated circuits. These highly
complicated ICs offer a great deal of functionality in a very small space,
and at very low cost. Often such highly complicated ICs contain the
equivalent of hundreds of thousands of logic gates, or millions of
transistors. Because so much of the functionality of these highly
complicated ICs is hidden from the user, it is often difficult to be
certain at the time an electronic system incorporating them is designed
that the final implementation of the electronic system (target
environment) will function properly when it is put together; in other
words, to validate the performance of the electronic system.
Recently, semi-custom integrated circuit devices known generally as ASICs
(Application Specific Integrated Circuits) have become popular with
electronic system designers. These devices (highly complicated integrated
circuits themselves) allow some degree of customization of the circuitry
contained thereupon. Using one or more ASICs specially designed for an
application, a system designer can dramatically reduce the number of
components (integrated circuit devices and other electronic parts)
required to build an electronic system.
ASICs are available in a number of different technologies and in a variety
of forms. Generally, ASICs are available from an ASIC manufacturer who has
provided a number of "template" circuits which may be incorporated onto
the ASIC by an ASIC user, and a number of design guidelines and
restrictions which arise from the nature of the specific ASIC technology
to be used.
Two primary forms of ASIC are widely available: gate-arrays and standard
cell ASICs. Gate-arrays are basically an array of pre-integrated
transistors ("sea of gates") and input/output pads (I/O pads) on an
integrated circuit chip without interconnecting conductors. The ASIC
manufacturer supplies the ASIC user with a set of standard circuits blocks
(typically gates, flip-flops, multiplexers, decoders, counters,
shift-registers, etc.) which may be constructed from these transistors and
I/O pads and which the user employs to specify the circuitry to be
contained on the ASIC in the form of a circuit diagram. Only those circuit
blocks which may be readily built from "standard" transistors in the array
can be offered. These circuit blocks represent the interconnections
required between a set of transistors and/or I/O pad required to construct
the circuit which will perform their respective functions. The
interconnection of these transistors and I/O pads is accomplished by the
ASIC manufacturer according to the user's circuit diagrams. After
interconnecting conductors have been applied to the ASIC, the ASIC is
packaged, tested, and shipped to the user.
Standard-cell ASICs are similar to gate-arrays, from the user's point of
view, except that a wider variety of circuit blocks is available. The user
employs a set of standard pre-defined circuit blocks to specify the
circuity to be incorporated into a standard-cell ASIC in the form of the
circuit diagram. In the case of standard-cell ASICs, however, no
pre-integrated structures typically exist. The pre-defined circuit blocks
used by the user to define his circuitry represent complete circuit
modules to be integrated onto an integrated circuit chip. Since "standard"
transistors are not a limiting factor, as they are for gate-arrays,
circuit geometries may be optimized for each circuit module represented by
a circuit block, allowing a much wider variety of circuit blocks to be
offered to the user. These circuit blocks are arranged onto a "blank"
integrated circuit chip in "cookie cutter" fashion by the ASIC
manufacturer according to the circuit diagram supplied by the ASIC user.
As for gate-arrays, after the standard cell integration process is
completed, the chips are packaged, tested and shipped to the user.
In a variation on the standard-cell theme, many ASIC manufacturers offer
"core-cells", typically very large and complicated circuits (e.g.,
microprocessors, peripheral controllers, etc.) which may be incorporated
into an ASIC design as yet another circuit block, albeit a very large one.
These core-cells are typically used in conjunction with other "surrounding
logic" on an ASIC to perform an application-specific function. ASICs
incorporating a core-cell and surrounding logic are called
"core-cell-based ASICs".
Some very large gate-based circuit blocks similar to core cells are offered
for gate-arrays, as well. While core-cells for gate arrays do not
generally offer the same range of function, they can be extremely
complicated gate-based designs. Gate-arrays making use of such core-cell
type functions are also termed "core-cell-based ASICs."
The creation (design process) of these core-cell-based ASICs and electronic
systems follow similar tracks from concept to reality, typically beginning
with a high-level design of the electronic system and its major
components. These high-level designs may be modelled in various high-level
software description languages, e.g. "VHDL" (VHSIC Hardware Description
Language), which allow partial design and verification of the overall
behavior of the electronic system and/or its components. The ultimate goal
is to implement the electronic system and its components in physical
reality. Between these two extremes, concept and implementation, various
incarnations of the design are realized. For example, the following terms
and definitions apply to the electronic system design process:
Component (electronic component or device): any physical electronic circuit
element (such as an IC, ASIC, resistor, capacitor, diode) which is
designed into an electronic system.
At-speed: operating at normal operating speeds and faithfully representing
actual performance.
Logical equivalent: a circuit, component, or technique which performs the
same function as something else, not necessarily at-speed.
Core-cell: a large, pre-defined circuit block to be incorporated onto an
ASIC, typically in conjunction with additional surrounding logic.
Core-cells functions typically include general-purpose microprocessor,
disk drive controller, communications controllers, etc..
Surrounding logic: logic used in conjunction with a core-cell on an ASIC to
perform an application-specific function.
ASIC: Application Specific Integrated Circuit, as described hereinabove.
Core-cell-based ASIC: an ASIC incorporating at least one core-cell and
surrounding logic.
ASIC manufacturer (or ASIC provider): a manufacturer (vendor) that designs
ASIC technology and provides the service of ASIC fabrication to ASIC users
(see below).
ASIC user: a customer of an ASIC manufacturer, usually an electronic
designer, who specifies the circuitry to be incorporated onto an ASIC
according to the ASIC manufacturer's guidelines, restrictions, and
methodology.
Electronic system: an electronic circuit comprising other components such
as ICs, ASICs, etc..
Electronic System Designer: a designer (usually an electrical engineer),
who designs electronic systems. May also be an ASIC designer, but not
necessarily.
ICE or In-Circuit Emulator: test apparatus specifically designed to replace
an IC for test purposes, and which allows greater controllability and
observability of the test process than would otherwise be available.
Target: a destination for or final form of a design. Examples:
Target ASIC: an ASIC into which a core cell, circuit block or surrounding
logic is incorporated, in its final manufactured form.
Target system: an electronic system into which an ASIC or electronic
component is designed.
Target environment: the "standard" operating environment of an electronic
component or system in its final form. For example: a circuit board may be
the target environment for an ASIC; a computer may be the target
environment for a circuit board, etc..
Interim: intermediate or temporary. Usually provided for test purposes.
Interim ASIC: a functional equivalent of an ASIC.
Interim Component: a functionally equivalent substitute for a component,
typically used for testing and verification purposes.
Interim system: an electronic system functionally equivalent to a target
system which is built prior to construction of and which closely resembles
a target system or which incorporates interim components; and which may
have minor modifications made (e.g., test points, sockets, etc.) to
facilitate verification and testing.
The use of the term "target" is largely a matter of perspective. For
example: a system breadboard may be an interim system from the point of
view of a manufacturer, but may simultaneously be a "target system" for a
logical equivalent, interim component, ASIC, or ICE.
Inchoate: designed, but not yet fabricated.
Inchoate ASIC: an ASIC which has been designed but which has not yet been
fabricated.
Because of the extreme internal complexity of many modern electronic
systems, particularly those incorporating ASICs, and of the highly
complicated ICs, the design process itself has given rise to a great many
techniques for verifying that an electronic system will perform as
planned. One technique commonly used to verify the performance of an
electronic system is to build a "breadboard", or quick test circuit,
incorporating the components in question and to run it in an environment
similar to the environment of its final application to verify that the
electronic system does indeed function as planned. If the breadboard does
not function correctly, there is an early warning that the design of the
electronic system must be modified.
Breadboarding of an electronic system, however, assumes the availability of
all components (or the functional equivalents thereof) necessary to build
the electronic system. Often, it is not possible or practical to acquire
all of the requisite components early in the design process, particularly
if custom designed components have been employed in the design of the
electronic system.
As integrated circuit (and ASIC) complexities have grown, and electronic
system complexities have grown with them (particularly in programmable,
microprocessor-based systems where software governs a great deal of system
functionality), it has become increasingly difficult to troubleshoot
electronic systems, even when a breadboard is available. In response to
this problem, at least for microprocessor-based systems, numerous
manufacturers have produced in-circuit emulators (ICE).
In circuit emulation systems (ICE systems) are intended to plug into a
target system in place of an IC, usually a microprocessor, and to emulate
the function of the IC exactly. The ICE system interfaces with the target
system via a "pod" which has a plug identical in shape and pin
configuration to that of the microprocessor to be emulated. However, ICE
systems also add a few capabilities, such as the ability to: halt
execution upon a specified set of conditions (e.g., execution of a
particular instruction, modification of a memory location, access of a
particular I/O port, etc.); examine/modify processor registers;
examine/modify memory; record (trace) a series of processor operations;
among many other capabilities. This is usually accomplished by selectively
monitoring and/or intercepting signals from the target system before
passing them back to the target system. ICE systems are well known and in
wide use in the present art. Intel Corporation manufactures ICE systems
having these capabilities, among others, for most of its microprocessor
products.
Most ICE systems employ either a specially designed variation of the
microprocessor they are designed to emulate, or a microprocessor identical
to the one they are designed to emulate. Usually, the purpose of using a
special variation of a microprocessor is to gain access to signals on-chip
which would otherwise be unavailable. This is particularly true for
microprocessors which have on-chip bus cache units. These units are
designed to anticipate the needs of the microprocessor's execution unit by
buffering memory locations beyond the address of the instruction being
executed, the assumption being that since most programs instructions
follow one another, there is a high probability that the next instruction
will already be buffered (cached) when the execution unit needs it. While
this is very efficient for the microprocessor, it makes it very difficult
to tell what is going on inside the microprocessor by looking at the
external signals. A great deal of the internal function of the
microprocessor is hidden from the outside world. As a result, special
variations on this kind of microprocessor are required by in-circuit
emulators (ICE's) so that the ICE may gain information about and control
over the internal operation of the microprocessor. Without theses special
variations, it would be difficult to stop the microprocessor at exactly a
particular point in a program. ICE systems for simpler microprocessors
(particularly non-cached microprocessors) can often employ standard
microprocessor chips.
One of the greatest advantages of the ICE system is its in-situ emulation
(emulation or simulation in the actual target environment). The user plugs
in a pod that replaces his microprocessor and, without modification to his
system, he has much greater controllability and observability over his
system, due to the ICE.
Many designs of electronic systems today, however, also incorporate
semi-custom integrated circuits called ASICs. The term ASIC is a generic
term that covers a great number of technologies and a great range of
complexities, but ASICs are all semi-custom integrated circuits, usually
based upon a gate-array or standard-cell product. The system incorporating
an ASIC may be called the "target environment" of the ASIC.
Modern ASICs may incorporate the equivalent of tens of thousands of gates.
Some standard cell offerings permit densities as high as 100,000 gates and
above. Many of these ASICs incorporate a "core-cell", such as a "Core
Microprocessor" or similar function. A core-cell is a predefined
functional equivalent of a functional block generally contained on a
commercial integrated circuit. For example, core-cells are available for
microprocessors, UARTs (Universal Asynchronous Receiver/Transmitters),
microprocessor support components, peripheral interfaces, disk
controllers, network interfaces, etc.. Basically, a "core microprocessor"
is a large pre-defined functional equivalent of a microprocessor which can
be embedded into a design on an ASIC, and surrounded by other logic
(surrounding logic). The use of core-cells permits rapid design of
"systems on a chip", which can be extremely sophisticated and complex.
Core-cells (also referred to as macrocell or "megacells") differ slightly
from their commercially available counterparts, in that they are designed
specifically to become a part of a larger design. As such, the signals at
their boundaries (interface signals, I/O signals) are likely to be
unbuffered, internal logic signal, and are generally not "tri-state"
capable (capable of bidirectional or shared operation by virtue of drivers
which can be turned off), as are some of the interface signals on typical
commercially available microprocessors.
FIG. 1a illustrates the difference between a typical "core" microprocessor
104 and a typical "commercial" microprocessor 102. As an example, a
typical 8-bit core microprocessor 104 is shown having a data bus driver
control signal "DBDC" 110, an 8-bit data output bus "DO<7..0>" 112, an
8-bit data input bus "DI<7..0>" 114, a control bus driver control signal
"CBDC" 120, a control output bus "CO" 122 comprising a plurality of
control output signals, a control input bus "CI" 124 comprising a
plurality of control input signals, an address bus driver control signal
"ABDC" 130, a 16-bit address output bus "AO<15..0>" 132, miscellaneous
output signals "MSCO" 142, and miscellaneous input signals "MSCI" 154.
The interface signals of the core microprocessor 104 are unbuffered and
unprotected (from static electricity, etc.). Also, the output signals on
the core microprocessor 104 (e.g., 112, 122, 124, etc.) do not have
drivers that can be disabled and placed in a high impedance state. This is
because the core microprocessor is intended to be used on an ASIC as a
part of a larger design, and does not incorporate the driver and
protection circuits necessary for interfacing with the outside world. In
order to make a "commercial" type microprocessor (e.g. 102 in FIG. 1) out
of a core microprocessor, it is necessary to add these driver and
protection circuits.
Dashed box 102 in FIG. 1a represents the functional equivalent of a typical
commercial-type microprocessor. This is made from core microprocessor 104
by adding drivers and receivers as shown. An 8-bit wide driver/receiver
circuit 116 is provided (having eight driver circuits connected in common
to a driver enable signal, and eight receiver circuits) to interface with
an 8-bit external bi-directional data bus 118, by connecting it such that:
data input bus 114 is driven by the outputs of the receivers of
driver/receiver circuit 116 the inputs of which are connected to external
data bus 118; data output bus 112 is applied to the inputs of the driver
circuits of driver/receiver circuit 116, the outputs of which drive
external data bus 118; and data bus driver control signal "DBDC" 110 is
connected to the driver control input of driver/receiver circuit 116, such
that it controls the enabled/disabled condition of the drivers of
driver/receiver circuit 116.
Similarly, a multi-bit bidirectional external control bus 128 is interfaced
to core microprocessor via a multi-bit driver/receiver circuit 126 (having
multiple driver circuits connected in common to a driver enable signal,
and multiple receiver circuits), by connecting it such that: control input
bus 124 is driven by the outputs of the receivers of driver/receiver
circuit 126 the inputs of which are connected to external control bus 128;
control output bus 124 is applied to the inputs of the driver circuits of
driver/receiver circuit 126, the outputs of which drive external control
bus 128; and control bus driver control signal "CBDC" 120 is connected to
the driver control input of driver/receiver circuit 126, such that it
controls the enabled/disabled condition of the drivers of driver/receiver
circuit 126.
The data and control busses of the core microprocessor are arranged to
allow for data or control input and output. In the core microprocessor
shown, however, there is no address input bus, but certain modes of
operation of the commercial device dictate that the external address bus
"BA<15..0>" 138 must be left undriven by the microprocessor 102 so that
other devices may drive it (for example, for DMA, or Direct Memory Access
transfers, whereby external devices may access memory directly by stealing
borrowing time cycles from the microprocessor and generating their own
control and address signals). As a result, tri-state drivers (drivers
which can be disabled) are required. To this end, a 16 bit wide tri-state
driver circuit 136 having a common enable signal is connected such that
the drivers receive their inputs from internal address bus 132 and drive
their outputs onto external address bus 138. The enable input of tri-state
driver circuit 136 is connected to address bus driver control signal 130.
Miscellaneous outputs "MSCO" 142 on the core microprocessor which are
permanently driven (e.g., a DMA request acknowledge signal) are buffered
by drivers 146 and placed on buffered external outputs "BMSCO" 148.
Similarly, external inputs 158 are buffered by receivers 156 and place
onto internal miscellaneous input bus 154.
FIG. 1b illustrates the relationship of a core part (such as 104 with
respect to FIG. 1a) to an ASIC into which it is incorporated. A core part
180 is incorporated into a semiconductor die 184 by placing it on the die
and connecting it to surrounding logic 182. Typically, semiconductor die
184 is an ASIC whose function includes the function of the core part 180.
Surrounding logic 182 interfaces with the signals of the core part 180,
providing the remainder of the functions of the ASIC.
Industry trends are toward increasing pressure for rapid turnaround of
designs. Technology changes quickly and delays may mean the loss of a
market. As a result, system designs must work both quickly and accurately.
Accuracy is extremely important because an error discovered late in a
design cycle can cause large parts of the design cycle to be repeated,
causing delays.
This is especially true for system designs which incorporate ASICs. After
an ASIC design is completed, various layout and simulation steps must be
performed, and the ASICs must be fabricated. This process often requires a
great deal of time. If an error is discovered in an ASIC design after the
ASIC has been manufactured, then any remaining ASICs must be scrapped
(usually), a new (possibly shorter) design cycle must be started, and a
new fabrication cycle is required. This is almost as bad as having to
start all over again, in terms of delays. Evidently, then, it is highly
desirable for a system designer to take any and all steps necessary to
ensure that his ASIC design will work before the ASIC is manufactured.
There are actually two complementary problems that are inherent in ASIC
validation:
1) determining that the ASIC, as designed, will function properly in its
target environment; and
2) determining that the target environment, as designed, will function
properly with the ASIC.
By way of analogy, a musician may practice (and presumably perfect) his
part separately from an ensemble, and the ensemble may rehearse without
the musician, but there is no certainty that there will be total harmony
until musician and ensemble rehearse together.
It is in these areas that late discoveries of problems often occur. This is
because most simulations are directed to ensuring that the ASIC vendor
will produce exactly the ASIC that the designer designed. The ASIC user
and electronic system designer have few choices for validating that an
electronic system will function correctly with an ASIC, other than waiting
for a completed ASIC and trying it in his system.
A number of software-based "system simulation" tools, have been in use for
a number of years, among them "N.2".
Typically these tools operate at a behavioral level, and require the system
designer to describe his system design in the form of a behavioral model.
Since the behavior of a system and its components is accomplished in a
manner largely unrelated to the details of the system design (behavioral
descriptions tend to "paraphrase" the designs of the items being
described), this constitutes a second, redundant design activity.
Typically, these system simulators provide only an overview of system
performance and do not give a great deal of insight into problems which
may occur at the lowest levels of the design. Further, behavioral models
often over-simplify low-level behavior of hardware and software systems,
and do not necessarily produce completely accurate simulations,
particularly if the system designer is responsible for the modelling of
his own system. Since the design, in this case, is being done twice (once
at a detailed level and once for the behavioral models), there is a good
chance for differences to occur between the original system design and the
behavioral description thereof. Some behavioral models have been made
commercially available for certain widely used integrated circuits (such
as microprocessors, etc.), and give very good approximations of the
function of the modelled part, even to the point of being able to run code
on microprocessor models. However, software models (behavioral or other)
for custom-designed components (e.g., ASICs) must usually be generated by
the designer of the custom-designed components.
It is also possible to perform software-based gate-level simulations of a
system design, provided that gate-level models are available for all of
the system components, but for such large, complex integrated circuits as
microprocessors and peripheral controllers, these models are difficult or
impossible to acquire, and if they can be acquired they are often
extremely expensive. Gate-level models tend to run very slowly
(potentially many orders of magnitude slower) compared to the systems they
model.
Hardware-based simulation accelerators have been designed to accommodate
simulations at a number of levels (including gate-level, transistor-level,
behavioral level, etc.) As with software-based simulations, the more
detailed and accurate the simulation required (a gate-level simulation is
more detailed and accurate than a behavioral simulation) the slower the
simulation runs. Even with a hardware-based simulation accelerator, all
but the most trivial of simulations run many times slower than the systems
they model.
Some recent advances in automatic model generation have provided for highly
accurate automatically generated models. In modern systems, this is almost
a pre-requisite. It is even possible to "plug" these simulation models
into other simulated circuits and to attempt to exercise the modelled
(simulated) circuits together as a system. But the more detailed and
accurate the model (the more complicated the model description), the
slower it runs on any simulator, software-based or accelerator-based. At
present, (except for the simulation of relatively trivial, small
functions, or of very slow systems), simulations of systems run orders of
magnitude slower than the systems they model, and do not necessarily model
low-level behavior accurately.
A good deal of the pressure for real-time simulation, which is not possible
by any method except ICE methods, is due to the fact that in
software-based systems, the conditions which cause systems to fail may
occur only infrequently, and may be timing-based problems which can only
be simulated at-speed, or which would take too long to detect at a lower
speed. Such problems often include interrupt overrun conditions, bus
contention problems, errors in the handling of asynchronous events, etc.,
which may be difficult or impossible to detect except in the actual target
environment. For this reason, most electronic system designers employ an
ICE (in-circuit emulator) for in-situ simulation (simulation in the target
hardware, at-speed).
ASIC users, especially those who use such embedded functions as "core
microprocessors" surrounded by logic, are unable to take advantage of
in-circuit emulation, because no emulator exists which is compatible with
their specialized design. While one of the ultimate goals of systems that
use this type of ASIC is to provide near-optimal packaging and
cost-effectiveness, the design cycle can be particularly troublesome since
it is difficult, at best, to determine whether a target system will
function correctly when the ASIC is plugged in. In fact, it is sometimes
considered risky to build the system at all or to commit to purchasing
production quantities of components until the function of the ASIC can be
verified in a breadboard.
The cost-effectiveness of an ASIC design can rapidly be destroyed if it
becomes necessary to go through second and third passes at the design. NRE
charges (non-recurring engineering charges by the ASIC manufacturer for
the service of building the ASICs) are usually computed into the cost of
the system being designed. If a serious over-run should occur in NRE, then
the cost of the system may be driven up, negating at least part of the
benefit of using the ASIC in the first place.
In response to the problem of simulation of ASICs and programmable logic,
systems such as "Quick Turn" have been designed. This system is based
essentially upon a computer controlled box of programmable logic which can
be configured to create a functional equivalent of an ASIC. However, since
it is necessary to use moderately long cables with this system, among
other reasons, emulation speeds are relatively slow, providing a
simulation at significantly less than full-speed, especially for fast
systems.
Other systems have been built which allow pre-existing integrated circuits
to be "plugged into" software-based simulations by providing an interface
which can be accessed by the software simulation. This interface accepts
descriptions from the software simulation about the various states,
signals and drive levels that should be presented at selected pins of the
pre-existing integrated circuit. The interface then appropriately
exercises these pins and reports the pre-existing integrated circuit's
responses back to the software simulation, which then uses this
information to complete its function. Such hardware simulation interfaces
include systems such as: "RealCHIP" by Valid Logic Systems, Inc. and LMSI
(Logic Modelling Systems, Inc.).
None of the aforementioned simulation or testing techniques permits in-situ
(meaning "physically in the target environment"), at-speed testing of a
system with an inchoate ASIC (defined hereinabove). The term "inchoate
ASIC" is further defined for the purposes of this specification to be an
ASIC incorporating a core-cell, which has been designed but has not yet
been fabricated. The closest physical approximation to testing a system
with an inchoate ASIC is provided by in-circuit emulators, which provide
in-situ, at-speed testing of systems incorporating standard
microprocessors (arguably "inchoate" microprocessors, if they are not
readily available).
As a result, there is little certainty of the success of any system design
incorporating an inchoate ASIC until the physical parts have been received
and tested in-situ. Until the physical ASIC parts have been received and
tested, there is a great deal of uncertainty about both the design of the
inchoate ASIC and the design of the system to which the inchoate ASIC is
applied.
Reference is made to commonly-owned U.S. Pat. No. 4,901,259, entitled ASIC
EMULATOR, incorporated by reference herein, which is discussed
hereinbelow.
DISCLOSURE OF THE INVENTION
It is therefore an object of the present invention to provide a technique
for in-situ, at-speed testing of the final implementation of an electronic
system incorporating an inchoate ASIC by providing means for emulating the
inchoate ASIC.
It is a further object of the present invention to p | | |
