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Claims  |
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I claim:
1. A communication interface for use in a communication system
interconnecting a computer with at least one other device, said interface
comprising:
(a) output circuitry for outputting messages, said output circuitry
including control circuitry and encoding circuitry for providing two
parallel outputs,
(i) one of said parallel outputs being in the form of an outgoing data
signal representing data and including a serial bit pattern forming at
least part of an output message, said serial bit pattern providing a
sequence of signal transitions between two levels with said transitions
occurring only when said data changes, and
(ii) another one of said parallel being in the form of an outgoing strobe
signal which, when data is output in the data signal, has signal
transitions only at bit boundaries where there is no transition on the
data signal, and
(b) input circuitry for inputting messages, said input circuitry including
decoding circuitry having a first input to receive an incoming data signal
and a second input to receive an incoming strobe signal, said decoding
circuitry being arranged to respond both to incoming data and incoming
strobe signals to decode data encoded in said incoming data signal.
2. A communication interface for use in a communication system
interconnecting a computer with at least one other device, said interface
comprising:
(a) output circuitry for outputting messages, said output circuitry
including
(i) control circuitry and encoding circuitry for encoding and outputting a
succession of encoded serial tokens each including a serial bit string,
and
(ii) a parity bit generator responsive to successive bits in an encoded
serial token and arranged to generate a parity bit after encoding of each
serial token, said parity bit being included in a next serial token to
provide a parity check responsive to the bits in the preceding serial
token, and
(b) input circuitry for inputting messages, said input circuitry including
decoding circuitry for inputting and decoding data in each serial token
received and a parity checking circuit to detect a parity bit in each
serial token and compare said parity bit with a bit pattern including bits
from said preceding serial token.
3. A communication interface for use in a communication system
interconnecting a computer with at least one other device, said interface
comprising:
(a) output circuitry for outputting messages, said output circuitry
including
(i) control circuitry and encoding circuitry for encoding and outputting a
succession of variable bit length tokens each including a serial bit
string including at least one parity bit and other bits including at least
one bit forming a bit length indicator for the token, and
(ii) a parity bit generator responsive to successive said other bits after
a bit length indicator in a first token up to and including a bit length
indicator in a second token and arranged to generate a parity bit for
inclusion in each token, and
(b) input circuitry for inputting messages, said input circuitry including
decoding circuitry for inputting and decoding data in each token received
and a parity checking circuit to detect a parity bit in each token and
compare said parity bit with a bit pattern after a bit length indicator in
one token up to and including the next bit length indicator.
4. A communication interface according to claim 1 in which said control
circuitry is arranged to output data in said data signal in tokens of
predetermined bit length.
5. A communication interface according to claim 2 in which the control
circuitry is operable to output tokens of more than one predetermined bit
length.
6. A communication interface according to claim 4 wherein each token
includes a flag to indicate the token bit length.
7. A communication interface according to claim 1 in which said control
circuitry includes a parity bit generator to generate a parity bit for
inclusion in each token.
8. A communication interface according to claim 3 in which said control
circuitry includes a flag bit generator to generate a flag bit for
inclusion in each token to identify each token as a data token or a
control token.
9. A communication interface according to claim 8 in which said flag bit
provides an indication of the token length.
10. A communication interface according to claim 1 in which the control
circuitry is arranged to provide control tokens and data tokens each
having a respective predetermined bit length, each data token having a
greater bit length than a control token.
11. A communication interface according to claim 1 in which the input
circuitry includes delay circuitry connected between each of said two
inputs and said decoder and means for varying the delay on one or both of
said inputs prior to decoding.
12. A communication interface according to claim 1 in which the output
circuitry includes flow control means for generating flow control tokens
for outputting to a connected communication interface and said input
circuitry includes means responsive to input of a flow control token to
control operation of the output circuitry in outputting further data
signals.
13. A communication interface according to claim 12 in which said input
circuitry includes store means for holding a plurality of data signals and
said flow control means is responsive to the contents of said store means.
14. A communication interface according to claim 8 in which said encoding
circuitry is arranged to provide said parity bit and said flag bit at the
start of each token.
15. A communication interface according to claim 8 in which said parity bit
generator is coupled to said encoder so as to respond to the number of
bits encoded in a first token after a flag bit in said first token and to
supply a parity bit in a first location of a second token indicating an
aggregate of said number of bits from said first token together with the
parity and flag bits of said second token.
16. A method of effecting communication between at least two interconnected
devices, at least one of which devices comprises a computer device, said
method comprising the steps of:
(a) establishing parallel data signal and strobe signal communication paths
between two link interfaces each connected to a respective one of said
devices,
(b) encoding a serial bit pattern to form a data signal representing data
as at least part of an output message, said serial bit pattern providing a
sequence of signal transitions between two levels with said transitions
occurring only when said data changes,
(c) outputting said data signal on the data signal path from one link
interface,
(d) outputting on the strobe signal path from the said one link interface a
strobe signal which, when data is output in the data signal transitions
only at bit boundaries where there is no transition on the data signal,
and
(e) inputting said data and strobe signals in parallel at the other link
interface and responding to both said data and strobe signals to decode
data encoded in said data signal.
17. A method of effecting communication between at least two interconnected
devices, at least one of which devices comprises a computer device, said
method comprising the steps of:
(a) establishing unidirectional communication paths between two link
interfaces each connected to a respective one of said devices,
(b) encoding a succession of tokens each including a serial bit string,
(c) generating a parity bit in response to successive bits of a first
token,
(d) including said parity bit in the serial bit string of a second token
following said first token to provide a check on the number of bits in
said first token,
(e) transmitting said first and second tokens serially from one said link
interface to the other link interface,
(f) decoding said first and second tokens at said other link interface, and
(g) detecting said parity bit in said second token and comparing said
parity bit with the decoded bit pattern.
18. A method of effecting communication between at least two interconnected
devices, at least one of which devices comprises a computer device, said
method comprising the steps of:
(a) establishing unidirectional communication paths between two link
interfaces each connected to a respective one of said devices,
(b) encoding a succession of variable length tokens each including a serial
bit string including at least one parity bit and other bits including a
token bit length indicator,
(c) generating a parity bit in response to successive bits of a first token
following a bit length indicator for said first token up to and including
a bit length indicator for a next token,
(d) including said parity bit in the serial bit string of said next token
to provide a check on bits in said first token and the bit length
indicator of said next token,
(e) transmitting said first and second tokens serially from one said link
interface to the other link interface,
(f) decoding said first and next tokens at said other link interface to
provide a decoded bit pattern, and
(g) detecting said parity bit and comparing said parity bit with the
decoded bit pattern.
19. A method according to claim 18 in the said parity bit is located in
said next token.
20. A method according to claim 18 in which each said parity bit forms a
first bit in a token and said bit length indicator forms a second bit.
21. A method according to claim 16 further comprising establishing four
unidirectional communication paths between each pair of link interfaces,
said four paths comprising a first parallel pair of data and signal paths
in one direction and a second parallel pair of data and signal paths in
the opposite direction.
22. A method according to claim 16 wherein data is output by a link
interface in tokens of predetermined bit length.
23. A method according to claim 22 wherein data is output by a link
interface in tokens of more than one predetermined bit length.
24. A method according to claim 18 further including generating a flag bit
for inclusion in each token to identify the token as a data token or a
control token.
25. A method according to claim 24 wherein said parity bit and flag bit are
located at first and second bit positions respectively in each token.
26. A method according to claim 25 further comprising forming two
successive control tokens to form a compound token, the first of said
control tokens having a bit pattern indicating that a further token is
required to determine a control indicated by the compound token.
27. A method according to claim 16 wherein messages are transmitted between
connected link interfaces in variable length packets, each packet
comprising a multiple number of tokens, each token being of a
predetermined bit length and providing an end of packet token at the end
of each packet.
28. A method according to claim 27 further comprising including an end of
message token at the end of a last packet in a message.
29. A method according to claim 16 including providing an alignment token
to cause simultaneous transitions in said data and strobe paths when no
data is transmitted on the data path and using said simultaneous
transitions to effect alignment of the signals on the data and strobe
paths when input by a link interface.
30. A method according to claim 16 including forming flow control tokens
for outputting by a link interface, outputting data from a first interface
to a second interface, outputting a flow control token from said second
interface to said first interface to indicate to the first interface that
further data tokens may be output to the second interface.
31. A method according to claim 30 further comprising maintaining a count
which is adjusted by output of tokens by an outputting link interface,
inhibiting further output of data tokens from said link interface when the
count reaches a predetermined number and adjusting said count in response
to input of a flow control token from a connected interface to permit
output of further data tokens.
32. A method according to claims 16 wherein each link interface is arranged
to output data tokens of a predetermined bit length longer than a second
predetermined bit length for control tokens.
33. A method according to claim 16 wherein each link interface is arranged
to output control tokens of two types, a first type for controlling
operation of a connected link interface and a second type for use by said
device connected to the second link interface.
34. A method according to claim 33 wherein each link interface is arranged
in its input circuitry to store data tokens and control tokens of said
second type.
35. A method according to claim 34 including transferring data tokens and
control tokens of said second type from a store in the link interface to a
said device connected to the link interface by use of a synchronised
handshake.
36. A method according to claim 16 wherein a link interface is arranged to
output a packet which includes in one or more data tokens an address of a
communication channel to be used in a said device connected to a link
interface arranged to receive said packet.
37. A method according to claim 16 or claim 18 comprising effecting
bidirectional communication between a plurality of devices included in a
network having a plurality of microcomputers and at least one routing
switch. |
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Claims |
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Description |
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The invention relates to communication interfaces and is particularly
applicable to communication interfaces for use with computer apparatus and
the transmission of messages between computers or computers and other
devices connected thereto.
BACKGROUND OF THE INVENTION
Computer devices and other integrated circuit devices may need to transmit
messages or to receive messages from other devices. In some cases, the
message transmission may occur between two interconnected devices or
between a large number of devices forming a network. In such a network,
one or more of the devices may be in the form of computer apparatus and
other devices may comprise a variety of peripheral equipment. Such
networks may include routing switches to permit a wide range of
interconnections throughout the network. The transmission of data between
such connected devices can be accomplished by using parallel data buses or
serial communication wires. Complications arise in controlling buses in
such network connections and furthermore the speed of operation is
particularly limited where two or more devices are connected in the
network.
It is an object of the present invention to provide a simple high speed
interface between such communicating devices. It is an object to permit
high speed operation without loss of data and to permit messages of
variable length to be transmitted in multiple packet form. This is
advantageous in permitting any interface to handle packets of different
messages in succession before completing transmission of all packets of
any one message.
It is an object of the invention to provide an improved bidirectional
communication interface using four unidirectional signal wires.
SUMMARY OF THE INVENTION
The invention provides a communication interface for use in a communication
system interconnecting a computer with at least one other device, said
interface comprising output circuitry for outputting messages and input
circuitry for inputting messages, said output circuitry including control
circuitry and encoding circuitry for providing two parallel outputs one in
the form of a data signal comprising a serial bit pattern forming at least
part of an output message and the other in the form of a strobe signal
which, when data is output in the data signal, has signal transitions only
at bit boundaries where there is no transition on the parallel data
signal, and said input circuitry including decoding circuitry having two
inputs, a first input to receive a data signal and a second input to
receive a strobe signal, said decoding circuitry being arranged to respond
both to data and strobe signals to decode data encoded in said data
signal.
The invention also provides a communication interface for use in a
communication system interconnecting a computer with at least one other
device, said interface comprising output circuitry for outputting messages
and input circuitry for inputting messages, said output circuitry
comprising control circuitry and encoding circuitry for encoding and
outputting a succession of tokens each comprising a serial bit string, and
a parity bit generator responsive to successive bits in an encoded token
and arranged to generate a parity bit after encoding of each token, said
parity bit being included in a next token to provide a parity check
responsive to the bits in the preceding token, said input circuitry
comprising decoding circuitry for inputting and decoding data in each
token received and a parity checking circuit to detect a parity bit in
each token and compare said parity bit with a bit pattern including bits
from the previous token.
The invention also provides a communication interface for use in a
communication system interconnecting a computer with at least one other
device, said interface comprising output circuitry for outputting messages
and input circuitry for inputting messages, said output circuitry
comprising control circuitry and encoding circuitry for encoding and
outputting a succession of variable bit length tokens each comprising a
serial bit string including at least one bit forming a bit length
indicator for the token, and a parity bit generator responsive to
successive bits after a bit length indicator in a first token up to and
including a bit length indicator in a second token and arranged to
generate a parity bit for inclusion in each token, said input circuitry
comprising decoding circuitry for inputting and decoding data in each
token received and a parity checking circuit to detect a parity bit in
each token and compare said parity bit with a bit pattern after a bit
length indicator in one token up to and including the next bit length
indicator.
Preferably said control circuitry is arranged to output data in said data
signal in tokens of predetermined bit length.
Preferably the control circuitry is operable to output tokens of more than
one predetermined bit length.
Preferably said control circuitry includes a parity bit generator to
generate a parity bit for inclusion in each token.
Preferably said control circuitry includes a flag bit generator to generate
a flag bit for inclusion in each token to identify each token as a data
token or a control token.
Preferably said flag bit provides an indication of token length in said
preceding token up to and including the flag bit of said one token.
Preferably the control circuitry is arranged to provide control tokens and
data tokens each having a respective predetermined bit length, each data
token having a greater bit length than a control token.
Preferably the input circuitry includes delay circuitry connected between
each of said two inputs and said decoder and means for varying the delay
on one or both of said inputs prior to decoding.
Preferably the output circuitry includes flow control means for generating
flow control tokens for outputting to a connected communication interface
and said input circuitry includes means responsive to input of a flow
control token to control operation of the output circuitry in outputting
further data signals.
Preferably said input circuitry includes store means for holding a
plurality of data signals and said flow control means is responsive to the
contents of said register means.
Preferably said encoding circuitry is arranged to provide a header for each
token encoded, said header comprising both said parity bit and said flag
bit.
Preferably said parity bit generator is coupled to said encoder so as to
respond to the number of bits encoded in a first token after a flag bit in
said first token and to supply a parity bit in a first location of a
second token indicating an aggregate of said number of bits from said
first token together with the parity and flag bits of said second token.
The invention also provides a method of effecting bidirectional
communication between at least two interconnected devices, at least one of
which devices comprises a computer, said method comprising establishing
parallel data signal and strobe signal communication paths between two
link interfaces each connected to a respective one of said devices,
encoding a serial bit pattern to form a data signal as at least part of an
output message and outputting said data signal on the data signal path
from one link interface and outputting on the strobe signal path from the
said one link interface a strobe signal which, when data is output in the
data signal, has signal transitions only at bit boundaries where there is
no transition on the parallel data signal, inputting said data and strobe
signals in parallel at the other link interface and responding to both
said data and strobe signals to decode data encoded in the data signal.
The invention also provides a method of effecting bidirectional
communication between at least two interconnected devices, at least one of
which devices comprises a computer, said method comprising establishing
unidirectional communication paths between two link interfaces each
connected to a respective one of said devices, encoding a succession of
tokens each comprising a serial bit string, generating a parity bit in
response to successive bits of a first token, including said parity bit in
a second token following said first token to provide a check on the number
of bits in the first token, transmitting said first and second tokens
serially from one said link interface to the other link interface,
decoding said tokens at said other link interface, detecting said parity
bit in the second token and comparing said parity bit with the decoded bit
pattern of said first token.
The invention also provides a method of effecting communication between at
least two interconnected devices, at least one of which devices comprises
a computer, said method comprising establishing unidirectional
communication paths between two link interfaces each connected to a
respective one of said devices, encoding a succession of variable length
tokens each comprising a serial bit string including a bit length
indicator for the token, generating a parity bit in response to successive
bits of a first token following a bit length indicator for the first token
up to and including a bit length indicator for a next token, including
said parity bit in a token to provide a check on bits in the first token
and the bit length indicator of the said next token, transmitting said
tokens serially from one said link interface to the other link interface,
decoding said tokens at said other link interface, detecting said parity
bit and comparing said parity bit with the decoded bit pattern.
Preferably the method includes establishing four unidirectional
communication paths between each pair of link interfaces, said four paths
comprising a first parallel pair of data and signal paths in one direction
and a second parallel pair of data and signal paths in the opposite
direction.
Preferably data is output by a link interface in tokens of predetermined
bit length.
Preferably data is output by a link interface in tokens of more than one
predetermined bit length.
Preferably the method includes generating a flag bit for inclusion in each
token to identify the token as a data token or a control token.
Preferably said parity bit and flag bit are located at first and second bit
positions respectively in each token.
Preferably the method includes forming two successive control tokens to
form a compound token, the first of said control tokens having a bit
pattern indicating that a further token is required to determine the
control indicated by the compound token.
Preferably messages are transmitted between connected link interfaces in
variable length packets, each packet comprising a multiple number of
tokens, each token being of a predetermined bit length and providing an
end of packet token at the end of each packet.
Preferably an end of message token is included at the end of a last packet
in a message.
Preferably the method includes providing an alignment token to cause
simultaneous transitions in said data and strobe paths when no data is
transmitted on the data path and using said simultaneous transitions to
effect alignment of the signals on the data and strobe paths when input by
a link interface.
Preferably the method includes forming flow control tokens for outputting
by a link interface, outputting data from a first interface to a second
interface, outputting a flow control token from said second interface to
said first interface to indicate to the first interface that further data
tokens may be output to the second interface.
Preferably the method includes maintaining a count which is adjusted by
output of tokens by an outputting link interface, inhibiting further
output of data tokens from said link interface when the count reaches a
predetermined number and adjusting said count in response to input of a
flow control token from a connected interface to permit output of further
data tokens.
Preferably each link interface is arranged to output data tokens of a
predetermined bit length longer than a second predetermined bit length for
control tokens.
Preferably each link interface is arranged to output control tokens of two
types, one for controlling operation of a connected link interface and a
second for use by said device connected to the second link interface.
Preferably each link interface is arranged in its input circuitry to store
data tokens and control tokens of said second type.
Preferably the method includes transferring data tokens and control tokens
of said second type from a store in the link interface to a said device
connected to the link interface by use of a synchronised handshake.
Preferably a link interface is arranged to output a packet which includes
in one or more data tokens an address of a communication channel to be
used in a said device connected to a link interface arranged to receive
said packet.
The method may include effecting bidirectional communication between a
plurality of devices included in a network having a plurality of
microcomputers and at least one routing switch.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of a network having a plurality of link
interfaces in accordance with the present invention,
FIG. 2 is a schematic view of one link interface in accordance with the
invention,
FIG. 3 shows in more detail the link output of the arrangement shown in
FIG. 2,
FIG. 4 shows in more detail the link input of the arrangement shown in FIG.
2,
FIG. 5 shows the bit pattern on data and strobe lines for two successive
tokens obtained by use of the apparatus shown in FIG. 2,
FIG. 6 shows an output on the data and strobe lines during the last four
bits of a Data Alignment Token,
FIG. 7 shows an input on the data and strobe lines following an output as
shown in FIG. 6, and
FIG. 8 shows an alternative input on the data and strobe lines following an
output as shown in FIG. 6.
DESCRIPTION OF THE PREFERRED EMBODIMENT
The network shown in FIG. 1 comprises a plurality of microcomputers 11, 12,
13 and 14 which may each comprise a single integrated circuit
microcomputer such as that shown in our U.S. Pat. No. 4,680,698. The
network may also include other equipment such as a microprocessor 15,
peripheral units 16 and 17 and a disk controller 18 controlling a disk 19.
The network also includes a routing switch 20 which may be as described in
our U.S. patent application Ser. No. 07/546402 now U.S. Pat. No. 5,140,583
entitled "Message Ring". Each of the microcomputers 11-14 has a plurality
of link units 21 each providing a communication interface connected by
four unidirectional signal wires 23 forming a bidirectional communication
with a connected link unit 21 on another device in the network. In the
example shown, the microprocessor 15 is connected to a bus 22 connected to
a link unit 21. Some of the devices such as microcomputer 12 and disk
controller 18 are connected directly by four signal wires 23 whereas other
devices are connected through the routing switch 20. Each of the
microcomputers 11, 12, 13, 14, microprocessor 15 and peripheral units 16
and 17 and disk controller 18 acts as a host device in relation to the
link unit 21 which enables input to and output from the host device. Each
of the link units 21 is similar and their construction and operation will
be described in more detail below. Each is arranged to enable
bidirectional communication between pairs of devices in the network. The
communication is such as to transmit variable length messages which may be
divided into a succession of packets.
Each set of signal wires 23 includes a first parallel pair of wires 25 and
26 forming respectively a data signal path and a parallel strobe signal
path in one direction between a pair of connected link units 21. The
second pair of wires forms a data signal path and parallel strobe signal
path in the opposite direction between the same pair of link units 21.
Messages are passed between connected link units 21 by serial bit strings
which are encoded on the data signal paths 25, and parallel signals on the
strobe signal path 26 are used in decoding the messages received on the
data signal path 25. The bit strings are transmitted in tokens, each token
being of a predetermined bit length. In this particular example, two
different token lengths are used. The first, called "data tokens," are
each 10 bits long, and the second type are control tokens each 4 bits
long.
Examples of each are shown in FIG. 5 where token N is an example of a data
token and the next successive token N+1 is a example of a control token.
For both types of token, the first bit location shown at the left hand
side of the token in FIG. 5 is a parity bit for the token. The second bit
location is a flag to indicate whether the token is a data token or a
control token. In the case of a data token, the next 8 bit locations may
contain any data required in the message. In the case of control tokens,
the first two bits are the same as already described for a data token, and
the last two bits contain a control indication. The strobe signal which is
transmitted in parallel with the data signal is also shown in FIG. 5, and
this is arranged so that when tokens are transmitted on the data line 25
forming part of a message, the strobe line 26 has signal transitions only
at bit boundaries where there is no transition on the parallel data
signal. Although both types of token are each of a predetermined bit
length, any desired number of tokens may be transmitted in succession to
form a single packet. The end of a packet can be marked by transmission of
a control token indicating the end of the packet.
It may be desirable in some cases for a link or a routing switch to handle
packets of a different message (possibly transmitted between a different
pair of devices) before completing transmission of a first message. By
arranging for the message to be transmitted in packets it is possible to
stop transmission of one message at the end of a packet and to resume
transmission of that message at a later time by one or more subsequent
packets ending with an end of message token when the message is complete.
This permits the multiplexing of a plurality of messages through a single
link.
The protocol used for the output of tokens on the data signal path 25 in
accordance with this example are as follows:
______________________________________
Function Abbreviation
Bit Pattern
______________________________________
Data byte POXXXXXXXX
Flow control Token
FCT P100
End of Packet EOP P101
End of message EOM P110
Escape ESC P111
Data Alignment DAT ESC P011
Null NULL ESC P100
Spare ESC P1xx
______________________________________
The above Table indicates the bit patterns for a data token in order to
transmit a data byte and subsequently four control tokens in the form of a
flow control token, an end of packet token, an end of message token and an
escape token. P indicates a parity bit in each token. The data token has
the second bit location with the flag set at 0 whereas the control tokens
have the second bit flag set to 1. The purpose of the escape token is to
form a compound control token consisting of two successive four bit
tokens. The escape token is clearly marked by its flag as a control token
and the third and fourth bit locations of the escape token indicate that
the token which follows will be a four bit token used for control purposes
and not data. The subsequent token which is used to form a compound token
with the escape token may either be a data alignment token or a null token
or a spare token.
In the above Table, the control tokens form two different types. Flow
control tokens and compound tokens formed by use of the escape token each
form a first type. These control tokens of the first type are only used by
the link interface itself for control purposes. The flow control token is
used to control the rate of outputting of tokens by one link to ensure
that a store in a receiving link is not overfilled. The data alignment
tokens are used to adjust the alignment of the data and strobe signals
when input by a link. Null tokens are normally transmitted when no other
tokens are being sent. Control tokens of the second type consist of the
end of packet token and end of message token. These together with data
tokens, are required by the host device which is connected to the link
interface, and these are consequently stored in a store in the link until
transferred with a synchronized handshake system to the host. Similarly,
control tokens of the first type are generated by the link interface
itself whereas data tokens and control tokens of the second type are
generated by the host device and transmitted to the link through a
synchronised handshake system.
When any of the tokens (except the DAT token) listed in the above table are
output on the data signal path 25, the strobe signal path 26 will output a
signal consisting of signal transitions at each bit boundary in the data
signal where there is no change in signal level in the data signal. When a
DAT token is output, the strobe signal follows the normal procedure for
bit boundaries after bit positions 1, 2, 3, 4, and 5 of the DAT token, but
at the bit boundaries after bit positions 6 and 7 it follows the inverse
of normal in that it causes simultaneous transitions 140a and 140h on both
the data and strobe paths after bit 6 and no transition on either path
after bit 7. This provides a single indentifiable edge on both signal
paths after bit 6 which is used for alignment purposes. This is shown in
FIG. 6 which illustrates the last four bit positions of a compound token
forming a DAT token.
The arrangement of the link interfaces will now be described with reference
to FIGS. 2, 3 and 4.
Each link unit 21 has an output unit 30, an input unit 31, a flow control
unit 32 and control circuitry 33. The output unit 30 is shown in more
detail in FIG. 3. A host interface 34 is provided to connect the output
unit to the host device such as the microcomputer 11 in FIG. 1. The
interface 34 is connected to the host by a data bus 35 arranged to provide
eight parallel bits of data. To permit synchronized handshake
communication with the host, the interface 34 also has an input 36 to
receive a data valid signal from the host and an output 37 to provide an
acknowledgement signal when it has received a byte of data from the host.
The interface 34 has a clock signal input 38 and a reset input 39. The
interface 34 also has an input 40 from the flow control unit 32 to inhibit
data output if sufficient tokens have already been output without
receiving a flow control token at the corresponding input. The interface
34 also provides a Token Sent output 41 to the flow control unit 32. Data
is presented to the interface 34 along with a data valid signal from the
host. When the output logic 30 is ready to accept that data, it signals by
means of an acknowledgement signal on line 37 to the host. If the host and
the output unit 30 are operating in different clock regimes, it is
necessary to synchronize the data valid signal 36 and acknowledgement
signal 37. Data received by the interface 34 is loaded into a parallel
register 42 and it will be understood that the data in this register will
either be a data token of the type previously described or a control token
EOP or EOM. In order to output a token, one of a plurality of Token
Request latches 43 must be set and to send any of the tokens which are
received through the interface 34, an input is provided on line 44 as an
input to the Token Request latches 43. The latches 43 also provide an
output on line 43a to the interface 34 to indicate when a data token has
been sent. The Token Request latches 43 also have three inputs 45, 46 and
47 for sending respectively a DAT, FCT and NULL token. Inputs 45 and 47
come from the control circuitry 33 whereas input 46 comes from the flow
control unit 32. The latches 43 also provide an output 48 to the flow
control unit 32 to indicate when an FCT has been sent.
To send a token, the appropriate input to the latches 43 is asserted, and
if the signal is valid on the falling edge of the clock signal which is
also fed to the latches, then the appropriate latch is set, and it is
reset by an input 49 when the token has been sent. The NULL request 47 is
held high during normal operation so that a NULL token is sent if no other
token is required to be sent.
The latch circuitry 43 is connected by eight lines, (four Token Request to
the Prioritiser 50 and four Token Prioritised to the Latches 43), to a
token prioritizer 50 and it also provides a signal on line 51 to a token
sequencer 52 whenever a latch is set. The token prioritiser 50 receives
the outputs from the Token Request latches 43 and contains logic circuitry
to prioritize the requests from the latches 43 in the order DAT, FCT,
DATA, NULL. This allows control when more than one latch request is made
at the same time. The token prioritizer 50 provides four separate outputs
(Token Prioritised) depending on which latch has been set, and these are
connected to a control code ROM 53 which also acts as a data multiplexor.
The ROM 53 is programmed with bit patterns for the control codes ESC,
DAT,-FCT and NULL. These are the control tokens which are generated solely
within the link logic whereas all other tokens are input from the host
through the interface 34. If the latch 43 has been set to indicate that a
data token (that is a token fed through the interface 34) is to be sent,
then the contents of the data register 43 are gated to the output of the
ROM circuit 53 which is connected to an output shift register 54. The
output consists of eight bits (only two of which are used for the tokens
EOP and EOM) and a control or data flag signal on line 55. This is also
fed as an input 56 to a sequencer 57. The register 54 receives the data in
parallel and outputs it in serial form with the control or data flag
preceding the eight data bits. The output is fed on line 58 to a parity
generator 59.
The parity generator contains a resettable latch with an output fed back to
the input via an exclusive OR gate. | | |
