Computer system configuration via test bus

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BACKGROUND OF THE INVENTION

The present invention relates generally to computer systems and, more particularly, to a method and apparatus for operating a computer system to configure the system via a serial test bus included within the system. The present invention not only permits system configuration via a serial test bus but also permits status monitoring, error logging and comparable operations to be performed via a serial test bus during system operation. The present invention is generally applicable to computer systems and components and, in its broadest aspects, can be utilized within a single integrated circuit.

Historically, initial system configuration has been implemented by physical devices on circuit boards making up the system. For example, switches, plugs, jumpers, connectors and the like were used for configuration. Accordingly, configuration or reconfiguration of a computer system required significant time and the resulting configuration often included errors which required still more time to correct. In addition, the reliability of the computer system was reduced due to the possible failures of the physical configuration devices.

An improved computer system configuration arrangement is provided by using integrated circuit (IC) devices to store system configuration data. The IC devices are initialized by entering configuration data into the devices from an interactive controller which usually retains the configuration data between periods of time when the system is active or until system reinitialization is requested.

In systems with high levels of integration, IC system configuration devices are implemented as application specific integrated circuits or ASICs. The ASICs often do not interface with a system or processor bus and therefore cannot be accessed directly under program control. Therefore, a separate configuration port or bus is needed to interface with the ASICs for configuration purposes. Unfortunately, the provision of a separate configuration bus adds to the cost and complexity of a computer system and also tends to increase the connection points or pin counts required for the ICs or ASICs used to construct a computer system.

Accordingly, there is a need for simple and effective way of accessing the ICs or ASICs of a computer system for system configuration without the requirement of a separate configuration bus. Preferably, the system configuration access arrangement would also provide for other system operations such as status monitoring, error logging and comparable operations within the computer system.

SUMMARY OF THE INVENTION

This need is met by the method and apparatus of the present invention wherein system configuration as well as other monitoring and control functions are performed in a computer system by means of a serial test bus which is commonly incorporated into the computer system for testing components, for example integrated circuits, used to construct modules of the computer system. The conventional serial test bus is modified to include register circuitry on modules of the computer system and/or within integrated circuits which are interconnected to construct the modules. The registers thus included within the computer system are written and read by the serial test bus for configuring the computer system as well as performing other operations such as monitoring and error logging within the computer system. To extend the amount of information which can be contained within these registers, preferably memory devices such as EEPROM, RAM, and the like, are associated with the registers.

The introduction of memory into the serial test bus permits configuration information to be stored in the modules and/or integrated circuits making up the computer system. For this arrangement of the present invention, the serial bus is able to access the configuration information stored within modules or other components of the computer system and then configure the system by utilizing the retrieved configuration information to derive necessary settings for the registers. When memory and/or other devices external to the serial test bus are included on modules or other components of the system, the time required to access these devices may exceed a default access time defined by the operating speed of the serial test bus. To ensure proper operation with such devices, a pacing or ready signal is generated in accordance with the present invention such that access is delayed until the ready signal is active. Thus, when such a device is accessed, it deactivates the ready signal until the requested access can be successfully completed.

In accordance with one aspect of the present invention, a method of operating a computer system test bus to configure a computer system including the test bus comprises the steps of: maintaining configuration information for the computer system; providing configuration register means for receiving the configuration information; interfacing the configuration register means with the test bus; defining a write operation for the test bus to write the configuration register means via the test bus; and, performing the write operation to transfer the configuration information to the configuration means to thereby configure the computer system.

In accordance with another aspect of the present invention, a method of operating a computer system test bus to configure and monitor a computer system including the test bus comprises the steps of: maintaining configuration information for the computer system; providing register means for receiving the configuration information and information representative of operation of the computer system; interfacing the register means with the test bus; defining a write operation for the test bus to write the register means via the test bus; performing the write operation to transfer the configuration information to the register means to thereby configure the computer system; defining a read operation for the test bus to read the register means via the test bus; and, performing the read operation to retrieve information representative of operation of the computer system from the register means.

This method may further comprise the steps of: generating a ready signal indicating that the register means is ready to be read and written; inactivating the ready signal in response to initiation of performance of read and write operations in response to the read and write signals if the register means is not ready to be read and written; and, reactivating the ready signal when the register means is ready to be read and written. To expand the capabilities of the method it may also further comprise the steps of: providing memory means for storing information defining the computer system; and, interfacing the register means with the memory means. Preferably, the step of maintaining configuration information for the computer system is performed by storing the configuration information in the memory means.

In accordance with still another aspect of the present invention, a serial test bus for a computer system comprises test bus controller means for generating timing, data and control signals for operation of the test bus. Test access means operable in response to signals from the test bus controller means is provided for testing the computer system. The test access means includes register means for receiving data from the test bus controller means for operation of the computer system.

In accordance with yet another aspect of the present invention, a serial test bus for a computer system comprises test bus controller means for generating timing, data and control signals for operation of the test bus. Test access means operable in response to signals from the test bus controller means is provided for testing and configuring the computer system. The test access means comprises configuration register means for receiving data from the test bus controller means for configuring the computer system.

To extend the capabilities of the present invention, the configuration register means may further provide for receiving status and error data from the computer system. For this arrangement, the test bus controller means further provides for reading the configuration register means for monitoring and error logging operations for the computer system. If the configuration register means cannot respond within a defined test bus access time, pacing means are provided for delaying operation of the test bus controller means when performing read and write operations on the configuration register means. Preferably, the serial test bus further comprises memory means associated with the configuration register means and accessible therefrom for storing information defining the computer system.

It is thus an object of the present invention to provide an improved method and apparatus for a serial test bus for a computer system through which system configuration can be performed; to provide an improved method and apparatus for a serial test bus for a computer system through which system configuration can be performed by means of registers which are associated with components of the computer system and receive configuration information for the system; and, to provide an improved method and apparatus for a serial test bus for a completer system through which system configuration can be performed by means of registers which are provided on components of the computer system and interface with memory used to store the system configuration information as well as other information relating to system operation.

Other objects and advantages of the invention will be apparent from the following description, the accompanying drawings and the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram schematically illustrating the connections and signals for a standard serial test bus (IEEE Std 1149.1) adapted to operate with an additional pacing or ready RDY signal, of the present application;

FIG. 2 is a state diagram for a test access port (TAP) controller of an IEEE 1149.1 serial test bus adapted to operate with the RDY signal of the present application;

FIG. 3 is a schematic block diagram illustrating an architecture for an IEEE 1149.1 serial test bus modified in accordance with one of the broadest aspects of the present application to include a plurality of registers designated in FIG. 3 as configuration registers which are accessible through the serial test bus;

FIG. 4 is a schematic diagram of an exemplary circuit for generating the RDY signal;

FIG. 5 comprised of FIGS. 5A and 5B, is a schematic block diagram of an IEEE1149.1 serial test bus modified in accordance with the present application illustrating the configuration registers of FIG. 3 in more detail and including memory accessible from the test bus;

FIG. 6 illustrates a sixteen register organization for the configuration registers of FIG. 5, each register having 8 bits with the contents of two memory registers being concatenated to address a memory having a 64K subaddress space;

FIGS. 7 and 8 are timing diagrams for write and read operations, respectively, for the memory of FIGS. 5 and 6 and for registers external to the bus;

FIG. 9 is a schematic block diagram of a configuration and test (CAT) bus architecture in accordance with the present application for a computer system having a plurality of modules;

FIGS. 10 and 11 are schematic block diagrams of configurations of a CAT bus in accordance with the present application for use with a computer system module;

FIGS. 12-14 illustrate instruction error detection for a CAT bus in accordance with one aspect of the present application;

FIGS. 15-18 is a schematic illustration of the relationship of devices within a boundary scan path and the corresponding tables in accordance with the present application;

FIG. 19 illustrates an output test vector, a signal map entry and drive determinations for output test vectors in terms of vector classes;

FIG. 20 is a schematic block diagram of an EXTEST table constructed for intermodule testing of a multiple module computer system;

FIG. 21-25 when interconnected as shown in FIG. 26 form a flow chart for performing intermodule testing using JTAG EXTEST procedures; and

FIG. 26 illustrates proper interconnection of FIGS. 21-25.

DETAILED DESCRIPTION OF THE INVENTION

The present application discloses a number of structural and operational modifications to a serial test bus which has been standardized by the Institute of Electrical and Electronics Engineers, IEEE, and is designated as the IEEE Std 1149.1. This serial test bus was developed by a Joint Test Action Group, JTAG, composed of members from both Europe and North America and is often referred to as a JTAG bus. Herein, the standard serial test bus is referred to interchangeably as an IEEE 1149.1 bus, a JTAG bus and/or, once modified in accordance with the disclosures of the present application, as a configuration and test (CAT) bus. The later name, CAT bus, reflects one of the purposes of the modifications of the JTAG bus which is to permit configuration of a computer system including a serial test bus by means of the serial test bus. While portions of the standard JTAG bus will be described herein, the structure and operation of the standard JTAG bus are well known to those skilled in the art. Those desiring additional knowledge or details of the standard JTAG bus are referred to the above noted IEEE Std 1149.1.

FIG. 1 schematically illustrates the connections and signals for a JTAG bus adapted to operate with an additional pacing or ready RDY signal to form a CAT bus system 100. The CAT bus system 100 includes a bus system controller 102 which will also be referred to herein as a CAT controller and, as illustrated in FIG. 1, generates the following signals: test data input, TDI; test clock, TCK; test mode select, TMS; and, an optional test reset, TRST. The test data output, TDO, and ready, RDY, signals are generated by the devices 104, 106 and 108 referred to as JTAG devices #1, #2 and #n in FIG. 1 which are connected to the bus system controller 102. The generation and use of the RDY signal, the only nonstandard JTAG bus signal of FIG. 1, will be fully described hereinafter.

FIG. 2 is a state diagram 110 for a test access port (TAP) controller of an IEEE 1149.1 serial test bus adapted to operate with the RDY signal of the present application. A TAP controller 114 is shown in FIG. 3 which illustrates the architecture of an IEEE 1149.1 serial test bus modified in accordance with one of the broadest aspects of the present application to include a plurality of registers designated in FIG. 3 as configuration registers 116 which are accessible through the serial-test bus. The configuration registers 116 are included along with a number of other standard JTAG registers collectively identified as test data registers and shown within a circuit block 118.

The standard JTAG registers include a boundary scan register 120 which is associated with each input and output connection for an integrated circuit, module or other entity which is to be tested by the JTAG bus. The boundary scan register 120 permits control and observation of signals at the input and output connections of an entity by means of standard JTAG bus operations well known in the art. A BYPASS register 122 and an optional identification, ID, register 124 are also shown within the block 118. The outputs of the registers 116, 120, 122 and 124 are selectively connected to an output multiplexer 126 through a register selector multiplexer 128. The output multiplexer 126 is connected to a D-flip-flop 130 having a Q output terminal which is connected to a buffer circuit 132 which ultimately passes the test data output, TDO, signal back to the bus system controller 102. The TDO signal is indicated as a CAT.sub.-- TDO in FIG. 3 since a configuration and test bus architecture is illustrated. Thus, each of the registers 116, 120, 122 and 124 can be selectively connected into the TDI-TDO JTAG bus serial scan path.

The TAP controller 114 is controlled by the bus system controller 102 via the control signals: test clock, TCK; test mode select, TMS; and, test reset, TRST, to generate control signals for the output multiplexer 126, the D-flip-flop 130, the buffer circuit 132, an instruction register 134 and an instruction decoder circuit 136 which is connected to receive instructions from the instruction register 134 and in turn generate control signals for the registers 116, 120, 122 and 124 and corresponding select signals for the register selector multiplexer 128. The states of the state diagram 110 of FIG. 2 for operation of the TAP controller 114 are as follows:

in the Test-Logic-Reset (TLR) state, the test logic is disabled so that normal operation of the circuit or module logic can operate unhindered by the JTAG test bus;

the Run-Test-Idle (RTI) state is a state between scan operations which allows idling or pacing of instruction execution;

the Select-DR (SDR) state is a temporary state in which all test data registers selected by a current instruction retain their previous state;

the Select-IR (SIR) state is a temporary controller state in which all test data registers selected by the current instruction retain their previous state;

in the Capture-DR (CDR) state, data may be parallel loaded into test data registers selected by the current instruction or the previous register state remains unchanged if the test data register selected does not have a parallel input;

in the Shift-DR (SDR) state, the test data register connected between TDI and TDO as a result of the current instruction shifts data one stage towards its serial output on each rising edge of TCK;

the Exit1-DR (E1DR) state is a temporary controller state from which the controller scanning process can be terminated or paused;

in the Pause-DR (PDR) state shifting of test data register in the serial path between TDI and TDO is temporarily halted;

the Exit2-DR (E2DR) state is a temporary state from which the controller can enter the Shift-DR state or an Update-DR state;

in the Update-DR (UDR) state, data is latched onto the parallel output of test data registers from the shift register path on the falling edge of TCK;

in the Capture-IR (CIR) state, the shift register contained in the instruction register of the controller loads data on the rising edge of TCK;

in the Shift-IR (SIR) state the shift register contained in the instruction register is connected between TDI and TDO and shifts data one stage towards its serial output on each rising edge of TCK;

the Exit1-IR (E1IR) state is a temporary controller state from which the controller scanning process can be terminated or paused;

the Pause-IR (PIR) state allows shifting of the instruction register to be halted temporarily;

the Exit2-IR (E2IR) state is a temporary state from which the controller can enter the Shift-IR state or an Update-IR state; and,

for the Update-IR (UIR) state the instruction shifted into the instruction register is latched onto the parallel output from the shift register path to become the current instruction.

The state diagram 110 for the TAP controller 114 is identical to the standard JTAG TAP controller state diagram shown in the IEEE Std 1149.1; however, in FIG. 2 it is shown to depict the operation of the RDY signal. The logic state values (0 and 1) shown adjacent to each state transition in the state diagram 110 of FIG. 2 represent the logic values of the TMS signal at the time of a rising edge of the TCK signal. Since the bus system controller 102 is the source of the TMS signal, it is adapted for operation with the RDY signal such that the RDY signal must be active before the bus system controller 102 will cause transition of the TAP controller 114 from the RTI state. Note that the bus system controller 102 can operate with standard JTAG devices since such standard devices will never deactivate the RDY signal.

Reference will now be made to FIG. 5 which illustrates the configuration registers 116 of FIG. 3 in more detail. In addition, the configuration registers 116 are shown as being able to access a nonvolatile memory 138 and an external configuration register, i.e., a register external to the test bus, from the test bus. Timing diagrams for reading and writing the memory 138 and external registers are shown in FIGS. 7 and 8 and will be referred to hereinafter for clarification of those operations.

The memory 138 may comprise any form of nonvolatile memory such as EEPROM, RAM or other memory devices and may be either internal or external to the test bus structure. In FIG. 5, the configuration registers 116 are illustrated as comprising n internal configuration registers 116.sub.a through 116.sub.n with internal configuration registers 116.sub.c, 116.sub.f and 116.sub.g interfacing with the memory 138 and internal configuration register 116.sub.n being identified as either an internal configuration register and receiving an update signal or an external configuration register and receiving a read/write RD/WR signal and generating a ready signal. Control signals for the configuration registers 116 are generated by a configuration register control circuit 116C.

To enable the JTAG bus to operate with additional test data registers, such as the configuration registers 116, two groups of JTAG user definable instructions, one for reads and one for writes, are provided for the CAT bus of the present application. The illustrated embodiment is implemented to provide sixteen configuration registers using an eight bit instruction field such that the following instructions are defined.

______________________________________ INSTRUCTION (binary) COMMAND DEFINITION ______________________________________ p0nnnn01 Read Configuration Register (nnnn = register number) p0nnnn10 Write Configuration Register (nnnn = register number) ______________________________________

Where p=is an instruction parity bit. For example, to read the status of the sixth configuration register CR6, 116.sub.f, a JTAG instruction would be issued with the binary value of "10011001", using even parity.

To expand the number of configuration addresses, three ports of the configuration address space, i.e., three of the configuration registers 116.sub.c, 116.sub.f and 116.sub.g, are arranged to provide a subaddress extension space within the memory 138. Two of these ports, configuration registers 116.sub.f and 116.sub.g, are concatenated to define the subaddress and the third port, configuration registers 116.sub.c, is used to write or read data to the subaddress within the memory 138 addressed by the concatenated contents of the configuration registers 116.sub.f and 116.sub.g. To facilitate sequential accesses of the subaddress space, a subaddress auto-increment function is provided to increment either one of the ports or configuration registers 116.sub.f and 116.sub.g which define the address for the memory 138. The auto-increment function is enabled and disabled via a bit in the configuration register 0010 labeled "control" in FIG. 6.

It is noted that the subaddress range depends on the number of bits per configuration register. For example, an eight bit register size results in a 16 bit subaddress if the two configuration registers 116.sub.f and 116.sub.g are concatenated as illustrated to provide a 64k subaddress range. An illustration of this 16 register arrangement with subaddress extension into the memory 138 is shown in FIG. 6. The subaddress extension concept is particularly useful for interfacing with memory devices such as EEPROM and RAM which may contain status and/or configuration information for the computer system including the CAT bus.

To enable the JTAG bus to operate with devices which may not be able to respond within a default access time defined for the JTAG bus, such as the memory 138 and external registers exemplified by the configuration register 116.sub.n, a mechanism for pacing or handshaking accesses to such devices is provided. The pacing function is accomplished by means of the ready, RDY, signal added to the JTAG interface as shown in FIGS. 1, 2, 4, 5 and 9-11. The ready RDY signal is deactivated by a JTAG device upon selection if it cannot respond to a data read or write access within a default access time which is dependent on the frequency of the JTAG clock, TCK.

FIG. 4 illustrates how the ready RDY signal can be implemented in a register or memory device which requires additional time to respond to read and write commands. As shown in FIG. 4, a read signal RD.sub.-- L is activated during a read command of an external register or a memory device such as the memory 138 and a write signal WR.sub.-- L is activated during a write command of an external register or memory device. At the beginning of a read or write operation, the RDY signal is deactivated by means of NAND gates 140, 142 until a number of pulses of the JTAG clock TCK are received and passed through D-flip-flops 144, 146 and 148 to reactivate the ready RDY signal. The number of D-flip-flops provided corresponds to the number of clock pulses and therefore the time required for access of a corresponding device including the ready RDY signal generating circuitry. Of course a large variety of arrangements will be apparent to those skilled in the art for generating the pacing or ready signal as described herein.

Prior to describing operation of the CAT bus of the present application for reading and writing the memory 138 and any external registers exemplified by the configuration register 116.sub.n, inclusion of the CAT bus within a computer system will be described with reference to FIGS. 9-11. In FIG. 9, the CAT bus is shown as being incorporated into a computer system 150 having a plurality of modules 152 which make up the system 150. Each of the modules 152 typically will in turn be made up by a plurality of integrated circuit devices which can be any off-the-shelf devices; however, in the illustrated embodiment, application specific integrated circuits or ASICs are used and thus will be indicated herein. In accordance with the present application, the CAT bus provides a convenient arrangement for not only testing the ASICs which are interconnected to form one of the modules 152 but also permits testing of the modules 152 and the system interconnections of the modules 152.

For ASIC level testing, the CAT bus architecture of FIGS. 3 and 5 is incorporated into each of the ASICs and is operated to test the ASICs operation at the chip level. The CAT bus architecture of FIGS. 3 and 5 is also incorporated into each of the system modules 152 to permit testing of the computer system 150 on the module level. Finally, the CAT bus of the present application is used to test at the system level by generating test signals from each of the modules 152 onto a parallel or common bus, for example a system bus 153 shown in FIG. 9, and monitoring the resulting signals