A surface stepped portion of the top interlayer insulating layer is reduced. An insulating layer is formed on the entire surface of a silicon substrate. A silicon layer is formed on and in contact with an upper surface of insulating layer. A pair of source/drain regions are formed in silicon layer with a predetermined space. A gate electrode is formed on a region sandwiched by the pair of source/drain regions with a gate insulating layer interposed therebetween. A bit line is formed in connection with source/drain region, and extending in contact with an upper surface of insulating layer. A capacitor configured of a lower electrode layer, a capacitor insulating layer, and an upper electrode layer is formed in contact with source/drain region through a contact hole formed in an interlayer insulating layer.

A memory cell of a DRAM comprises one MOS transistor and one capacitor. The MOS transistor includes a pair of source/drain regions and a gate electrode formed on the channel region. A bit line is formed so as to be connected to the source/drain region. A conductive layer is formed so as to be connected to the source/drain region. The gate electrode includes a first part formed on the channel region with an oxide film interposed and second and third parts extending from the first part, respectively, and formed on the bit line and the conductive layer with an interlayer oxide film interposed. The capacitor includes a lower electrode formed so as to be connected to the conductive layer and an upper electrode formed so as to be opposed to the surface of the lower electrode with a dielectric film interposed. The upper electrode is placed above the bit line. A word line is placed above the upper electrode and connected to the gate electrode. It is possible to provide a field effect transistor in which increase in speed can be realized and to provide a semiconductor memory device in which capacitance of the capacitor can be sufficiently secured in case of making miniaturization of the memory cell. It is also possible to prevent decrease in reliability caused by disconnection of the bit line.

A field-effect transistor and a method for its fabrication are described. The transistor includes a monocrystalline channel region extending from a monocrystalline body region of a semiconductor substrate. First and second source/drain regions laterally adjoin opposite sides of the channel region and are electrically isolated from the body region by an underlying first dielectric layer. The source/drain regions include both polycrystalline and monocrystalline semiconductor regions. A conductive gate electrode is formed over a second dielectric layer overlying the channel region. The transistor is formed by selectively oxidizing portions of a monocrystalline semiconductor substrate and then removing portions of the oxidized substrate. The resulting structure includes a body region of the substrate having overlying first and second oxide regions, with a protruding channel region extending from the body region between the oxide regions. Polycrystalline semiconductor material is then deposited under conditions conducive to partial epitaxial growth. A planarizing process then exposes a surface structure in which the first and second part-polycrystalline, part-moncrystalline semiconductor source/drain regions laterally adjoin opposite sides of the monocrystalline channel region. Additional process steps then provide the gate dielectric and gate electrode regions, desired doping levels, an interlevel covering dielectric, metallization contacts, etc.

A field-effect transistor and a method for its fabrication are described. The transistor includes a monocrystalline channel region extending from a monocrystalline body region of a semiconductor substrate. First and second source/drain regions laterally adjoin opposite sides of the channel region and are electrically isolated from the body region by an underlying first dielectric layer. The source/drain regions include both polycrystalline and monocrystalline semiconductor regions. A conductive gate electrode is formed over a second dielectric layer overlying the channel region. The transistor is formed by selectively oxidizing portions of a monocrystalline semiconductor substrate and then removing portions of the oxidized substrate. The resulting structure includes a body region of the substrate having overlying first and second oxide regions, with a protruding channel region extending from the body region between the oxide regions. Polycrystalline semiconductor material is then deposited under conditions conducive to partial epitaxial growth. A planarizing process then exposes a surface structure in which the first and second part-polycrystalline, part-monocrystalline semiconductor source/drain regions laterally adjoin opposite sides of the monocrystalline channel region. Additional process steps then provide the gate dielectric and gate electrode regions, desired doping levels, an interlevel covering dielectric, metallization contacts, etc.

A field-effect transistor and a method for its fabrication is described. The transistor includes a monocrystalline semiconductor channel region overlying and epitaxially continuous with a body region of a semiconductor substrate. First and second semiconductor source/drain regions laterally adjoin opposite sides of the channel region and are electrically isolated from the body region by an underlying first dielectric layer. The source/drain regions include both polycrystalline and monocrystalline semiconductor material. A conductive gate electrode is formed over a second dielectric layer overlying the channel region. The transistor is formed by patterning the first dielectric layer to selectively cover a portion of the substrate and leave an exposed portion of the substrate. An additional semiconductor layer is then formed under conditions such that the monocrystalline semiconductor channel region forms on the exposed portion of the substrate and the part monocrystalline, part polycrystalline source/drain regions form on the first dielectric layer.