In an information processing apparatus composed of two or more processor units each including a cache memory and a processor which accesses stored data via the cache memory, and a main storage, a cache memory control method in which, using information concerning control object data, such as identification of a storage area and whether or not the data are program data, a judgment is made as to whether or not the data has a high possibility of being used by another processor. If the data has a high possibility of being used by another processor, the cache memory is controlled by the store-through system. If the data has a low possibility of being used by another processor, the cache memory is controlled by the store-in system.
The present invention provides a multiprocessor which can decrease a required waiting time of access to improve the processing time thereof. There is provided a multiprocessor apparatus having a plurality of processor units in which each of processor units is arranged to include a processor, a local memory unit utilized for storing therein a copy of the whole data of a shared memory, and a copy circuit for controlling the local memory unit in the update processing when the contents of the shared memory are updated by the processor unit, wherein when the processor requests a piece of data that shall be stored in the shared memory with a data reading command, then the local memory unit reads the corresponding piece of data from the copied data stored therein and supplies it to the processor. The apparatus is applicable to a multiprocessing of a real time system, for example.
A non-uniform memory access (NUMA) data processing system includes a plurality of nodes coupled to a node interconnect. The plurality of nodes contain a plurality of processing units and at least one system memory having a table (e.g., a page table) resident therein. The table includes at least one entry for translating a group of non-physical addresses to physical addresses that individually specifies control information pertaining to the group of non-physical addresses for each of the plurality of nodes. The control information may include one or more data storage control fields, which may include a plurality of write through indicators that are each associated with a respective one of the plurality of nodes. When a write through indicator is set, processing units in the associated node write modified data back to system memory in a home node rather than caching the data. The control information may further include a data storage control field comprising a plurality of non-cacheable indicators that are each associated with a respective one of the plurality of nodes. When a non-cacheable indicator is set, processing units in the associated node are instructed to not cache data associated with non-physical addresses within the group translated by reference to the table entry. The control information may also include coherency control information that individually indicates for each node whether or not inter-node coherency for data associated with the table entry will be maintained with software support.
A data transfer interface is provided which enables a plurality of data processing devices to access a single data storage drive. The data processing device includes a switch connected to the plurality of data processing devices and the data storage drive. A control device drives the switch so that only one of the data processing devices accesses the data storage drive at a time.
A system for controlling memory accesses in a memory device in a multi-processor computer system comprises a memory controller and a data storage. The data storage comprises a plurality of memory lines. Each memory line has a check field for storing a GONE code that indicates that the data is held in a cache, a g bit field for storing a G bit for confirming the code in the check field, a tag field for storing an identification of the processor in whose cache the data is held, and a d bit field for storing the true value of the G bit in rare situations. The memory controller comprises a data buffer, an address buffer, and a memory sequencer. The memory sequencer is a state machine for controlling the functions of the memory device. The method includes the steps of reading a memory line; determining if the data contained in a check field portion of the memory line matches a GONE code generated from the address of the memory line; if the check field and GONE code values do not match, reading the data as data; if the check field and GONE match, checking the G bit; if the G bit is 1, outputting the address of the processor that holds the data in its cache; and if the G bit is 0, reconstructing the data from a D bit and outputting the data as data.
A cache access control system for dynamically conducting specification of dedicated and common regions and thereby always conducting optimum cache coherency control. In a processor, an L1 cache including an L1 data array and a directory is provided. A plurality of L2 caches are connected to each L1 cache. The L2 caches are connected to a main memory L3. An L2 cache history manager is supplied with L2 cache status information and an L2 cache access request from L2 caches. The L2 cache history manager judges an attribute (a dedicated region or a common region) of each line of L2. On the basis of the attribute, a cache coherency manager conducts coherency control of each L2 cache by using an invalidation type protocol or an update type protocol. The attribute is judged to be the common region, only in the case where a line shared by a plurality of L2 caches in the past is canceled once by the invalidation type protocol and then accessed again.
