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CROSS-REFERENCE TO RELATED APPLICATION
This application is related to the applications of:
Thomas L. Hiller, James J. Phelan, and Meyer J. Zola Ser. No. 07/972,789,
entitled "Establishing Telecommunications Call Paths In Broadband
Communication Networks";
Thomas L. Hiller, James J. Phelan, and Meyer J. Zola Ser. No. 07/972,786,
now U.S. Pat. No. 5,327,421, entitled "Apparatus For Interfacing Between
Telecommunications Call Signals And Broadband Signals"; and
Thomas L. Hiller, James J. Phelan, and Meyer J. Zola Ser. No. 07/972,788
entitled "Establishing Telecommunications Calls In A Broadband Network"
which applications are assigned to the assignee of the present
application, and filed concurrently therewith on Nov. 6, 1992
TECHNICAL FIELD
This invention relates to arrangements for establishing digital
telecommunications connections, and more specifically, for establishing
such connections using broadband networks and switching systems.
PROBLEM
In recent years, especially with the growth of telecommunications traffic
among businesses in large cities, there has been an increasing need for a
very large telecommunications switching system or its equivalent. In the
past, this need has partially been met by the use of smaller switching
systems interconnected by moderate capacity tandem switching systems. In
the case of a switching system such as AT&T's 5ESS.RTM. switch, a fairly
large system has been devised using switching modules of substantial
capacity interconnected by a time multiplexed switch. None of the
available solutions, however, have resulted in an economically
satisfactory solution to the need for a very large switching system or
cluster of systems for handling substantial quantities of telephone
traffic, low speed telecommunications data traffic, and high speed
telecommunications data traffic.
A new standard has been implemented for transmitting combinations of
broadband and narrower band, packet and circuit signals over broadband
facilities. This standard, the Asynchronous Transfer Mode (ATM) standard
packs communication signals into a plurality of cells, each cell being 53
bytes long, the 53 bytes consisting of a 5 byte header and a 48 byte
payload. When an ATM signal is transmitted, each of the cells of a segment
of the signal may be headed for a separate destination, the destination
being identified in the header. No sound economic proposal has been made
for the economic use of ATM for achieving a very high capacity large
switching system or a large highly interconnected cluster of smaller
switching systems.
SOLUTION
The above problem is solved and an advance is made over the prior art in
accordance with our invention wherein signals from a plurality of pulse
code modulated (PCM) channels, each channel for one telecommunications
call, each of the calls destined for a common switching module or
independent switching system are packed into a single consolidated ATM or
ATM-like cell, and wherein voice signals are transmitted, to and from a
common broadband platform (CBP) for switching ATM cells, using such cells
transmitted at a repetition rate that is the same or a sub-multiple of the
repetition rate of the PCM signals that represent the voice signals; the
cells are transmitted over constant bit rate (CBR) permanent virtual
circuits (PVC) from an ingress switching module or system to the CBP, to
an egress switching module or switching system. Permanent virtual circuits
are provisioned as the traffic between a particular ingress and egress
switch or module changes, but such circuits need to be activated or
deactivated only when an additional group (the group size being determined
by the number of voice channels that are transmitted in each cell) is
needed or can be released. Advantageously, using this kind of an
arrangement, an ATM crossconnect system, CBP, can be used to interconnect
the links of a permanent virtual circuit between an ingress and an egress
switching system or module.
In accordance with one specific embodiment, each consolidated ATM cell
carries one byte of each of 46 or 48 voice communications, and the
consolidated cells of the CBR PVCs are transmitted at a rate of one cell
per 125 microseconds (.mu.s). Advantageously, such an arrangement
simplifies the interface to existing PCM systems.
BRIEF DESCRIPTION OF THE DRAWING
FIG. 1 is a block diagram showing a network of interconnected access
switching networks;
FIG. 2 illustrates the connections to the access switches of such a
network;
FIG. 3 illustrates one 125 .mu.s frame of ATM cells (a glossary of
abbreviations is found at the end of the Detailed Description); the
constant bit rate (CBR) cells carrying voice channels are sent every 125
.mu.s;
FIG. 4 illustrates an ATM segment including a CBR cell and a variable bit
rate (VBR) cell;
FIG. 5 illustrates a CBR cell for carrying two-way traffic;
FIG. 6 illustrates the Synchronous Optical Network (SONET)/ATM signal
transmission network of FIG. 1;
FIG. 7 is a block diagram of an access switch of FIG. 1;
FIG. 8 is a block diagram of an Asynchronous Transfer Mode Interface Unit
(ATMU) for interfacing between PCM signals and ATM signals;
FIGS. 9-13 illustrate various blocks of the ATMU;
FIG. 14 illustrates the control complex of a common broadband platform
(CBP) unit for switching ATM cells; and
FIGS. 15-17 are flow diagrams illustrating the processes of selecting a
channel for a communication activating permanent virtual circuits and
combining traffic of partially loaded permanent virtual circuits.
GENERAL DESCRIPTION
This General Description first presents an overview of all of the diagrams
and is followed by a detailed description of special characteristics of
elements of these diagrams for implementing applicants' invention.
FIG. 1 is a block diagram showing a plurality of interconnected access
switching systems of a network. A group of access switches 1 access a
common crossconnect network 10 in accordance with the principles of this
invention. A crossconnect network is an ATM crossconnect network
comprising a plurality of interconnected ATM crossconnect nodes. Each ATM
crossconnect node has the ability to switch each incoming cell on any
incoming line to any outgoing line. Constant bit rate (CBR) cells are used
to carry PCM voice traffic, and variable bit rate (VBR) cells are used to
carry packetized data. Much of the traffic carried through the ATM
crossconnect network when used as a toll network is CBR traffic wherein
the individual CBR cells in each 125 .mu.s frame are switched to a
destination. An ATM crossconnect node can be used for a Common Broadband
Platform (CBP) because of the provision of PVCs and the relatively low
rate of activation and deactivation of these PVCs. The routing pattern for
a particular permanent virtual circuit (PVC) does not change as long as
the PVC is provisioned; the CBR can route according to a PVC as long as
that PVC remains active. The dynamic portion of the switching of the ATM
nodes is primarily associated with the switching of VBR cells whose
headers may be different with each 125 .mu.s frame and which must be
switched accordingly.
The term PCM as used herein refers both to voice signals transmitted by PCM
and to data (including FAX and video) transmitted over PCM channels.
Node as defined herein is the entity which gathers outgoing traffic and
which distributes incoming traffic. The Asynchronous Transfer Mode
Interface Unit (ATMU), described further below, is one example of such a
node, which may distribute traffic to a plurality of switch modules of one
or more 5ESS.RTM. switches or which may distribute traffic to one or more
stand-alone switches. The node is the access to a network for
interconnecting such nodes or is an intermediate switch point in such a
network.
FIG. 1 shows the exchange of messages required to complete the selection of
a CBR PVC channel. The ingress node signals to the egress node (message 3)
the identity of the source and destination parties, and the identification
of the PVC. The destination node returns with an acknowledgment (message
4) properly identifying the path.
FIG. 1 also shows links directly interconnecting the access switches. The
access switches are interconnected by interaccess switch links 5 which
carry SONET/ATM signals and are connected to a central SONET/ATM signal
transmission network 10 by SONET/ATM access links 6. The term SONET
(Synchronous Optical Network) is used herein to refer to either or both of
the U.S. standard (SONET) or the European standard SDH (Synchronous
Digital Hierarchy). SONET/ATM means SONET or SDH signals used to transport
ATM cells.
The access switches themselves are accessed by a plurality of local
switches and, as indicated in FIG. 2, the local switches are connected to
the access switches through digital facilities, such as the U.S. 24
channel conventional T carrier facilities or the European 32 channel
systems for carrying PCM signals, which signals are convened in the access
switches to CBR cells of ATM signals. When the digital facilities
themselves carry packetized data, then this packetized data is processed
by a Packet Switch Unit within an SM, sent via the TSIU of that SM to the
ATMU where it is converted to VBR ATM cells and transmitted over VBR PVCs
to the CBP. In addition, signaling channels are treated as CBR or VBR
channels and are transported, accordingly, in CBR cell channels or single
channel VBR cells of the type described below. Significantly, by
transporting signaling channels through the ATM network, the necessity for
a separate signaling network, using Signal Transfer Points (STP), is
avoided.
FIG. 3 illustrates one 125 .mu.s frame of a typical ATM signal that appears
at the output of an Asynchronous Transfer Mode Interface Unit (ATMU) (FIG.
8). A 125 .mu.s frame consists of a number of CBR cells and a number of
VBR cells. For convenience, these are shown as being grouped at the
beginning and end of each frame, but it is also possible to intersperse
VBR cells among groups of CBR cells. The advantage of grouping the CBR
cells in this manner is that priority of CBR cells can be assured and the
design of the cell list processor (FIG. 11, block 630) is simplified.
Signals coming into an ATMU are interspersed CBR and VBR cells. CBR cells
are transmitted from a common broadband platform (CBP) (block 550, FIG. 8)
as soon after they are received as possible, thus giving them priority
over VBR cells; the output of a CBP connected to an ATMU therefore has CBR
and VBR cells interspersed.
FIG. 4 illustrates the content of a CBR cell and a VBR cell. The content of
a CBR cell includes signals for a plurality of channels. Since an ATM cell
comprises a 5 byte header and a 48 byte payload, one attractive
arrangement is to have the 5 byte header identify the particular permanent
virtual circuit represented by the CBR cell, and to have the CBR cell
contain the individual bytes (PCM samples) of 48 voice channels (DSO
signals).
Alternatively, 46 DSOs are carried and a two byte index is used to identify
which group of 46 DSOs on a given virtual path is carried in a particular
cell. In this alternative, a plurality of ATM cells for one virtual path
are transmitted every 125 .mu.s, but cells with a particular index are
sent only once every 125 .mu.s. The alternative arrangement serves to
decrease the number of virtual paths a network must support.
The VBR cell illustrated in FIG. 4 comprises a header and a payload,
wherein the payload is associated with a single channel and a single
destination in accordance with CCITT standards for ATM. In effect, a VBR
cell represents part of a packet of data being transmitted from a source
access switch to a destination access switch of the toll network.
It is, of course, also possible to have a CBR cell all of whose entire
contents are devoted to a single communication, if the communication is a
communication such as the 1.5 megabit/sec. signal required for a
compressed television signal. For broadband signals, such as High
Definition TV (HDTV) signals, it is more convenient to connect these
signals directly to the CBP. Based on the use selected for the CBR PVC as
selected by the originating access switch, the payload in each cell is
used as selected, with the same disposition being made for all cells
transmitted over the CBR PVC for the duration of the existence of that
PVC.
FIG. 5 illustrates one CBR cell carrying two-way traffic, the first n bytes
carry up to n channels of outgoing traffic, and bytes (n plus 1) to 48,
carry up to (48 minus n) channels of incoming traffic. Since an egress
node assigns a channel, the bytes for outgoing traffic are seized by one
node, those for incoming traffic by the other node. Since assignment of
idle channels is upward from 1 for outgoing traffic and downward from 48
for incoming traffic, if many fewer than all of the channels are active
then it will generally be possible to move the dividing point, set in this
case between channel n and channel n plus 1 in the direction of additional
requests for channels. The two-way traffic CBR cells are particularly
useful for carrying traffic between a source and a destination when there
is relatively little such traffic being offered.
FIG. 6 shows the composition of the SONET/ATM signal transmission network.
This network comprises a group of CBPs 550 interconnected partly or fully
by inter-CBP SONET/ATM links. Each CBP has an associated ATM management
module (AMM) 535 for recording and controlling the virtual connections
established within the connected CBP. Each of the CBPs 550 in network 10
perform only a crossconnect function carried out under the control of the
connected AMM. The CBPs 550 are connected to access switches 1 by access
links 6.
In order to take full advantage of the desirable attributes of the real
time network routing arrangement, it may be desirable to provision virtual
circuits as 1- or 2-link virtual circuits, one or both of whose links may
require the use of a permanently assigned intermediate CBP. This
simplifies the process of selecting a near optimum provisioned circuit for
activation when this becomes necessary, although the provisioning of
active circuits may not be optimum.
FIG. 7 is a block diagram of an access switch 1. The 5ESS.RTM. switch,
manufactured by AT&T, and extensively described in AT&T Technical Journal,
Vol. 64, No. 6, Part 2, July-August 1985, pages 1303-1564, is the switch
described for use with applicants' invention. It includes a plurality of
switching modules. The input from the local switches 2 (FIG. 1) are
terminated on switching module 510. This switching module comprises both
circuit and packet switching units, such a module is described in M. W.
Beckner, J. A. Davis, E. J. Gausmann, T. L. Hiller, P. D. Olson and G. A.
VanDine: "Integrated Packet Switching and Circuit Switching System", U.S.
Pat. No. 4,592,048. This module is controlled by a switching module
processor 511 which communicates with a message handler 513 for receiving
and transmitting messages. The T-carrier inputs from local switches 2 are
terminated on digital interface 515 and are switched by time slot
interchange 517. Since the signals arriving at the digital interface also
contain packet switched signals (for example, signals from the D-channels
of Integrated Services Digital Network (ISDN) sources) a packet switching
unit 519 is also provided. The outputs of this packet switching unit are
sent to the time slot interchange unit for further switching onto output
digital links of the SM 510. In addition, a SONET interface unit 521 is
provided for interfacing with PCM signals carried over SONET facilities
from the local switches. The outputs of the switching module 510 are a
group of network control and timing links (NCT 523, . . . , 524)
(typically, up to 20). The NCT link signals are carried over optic fiber
links and can readily be made long enough to allow a SM to be remotely
located. A subgroup of these 20 links is then terminated in an
Asynchronous Transfer Mode interface Unit, (ATMU) 540. Other subgroups are
connected to other ATMUs, the latter also being connected to CBP 550. The
output of the ATMU is a plurality of SONET/ATM signals to the common
broadband platform (CBP) 550. The AMM, an extension of the administrative
module (AM) 530, is used to control switching connections in the common
broadband platform 550 and to carry out common functions for a plurality
of switching modules connected to a particular common broadband platform
(CBP) 550. The CBP is also used to switch signals between different
switching modules 510 connected to CBP 550 in order to handle tandem calls
between local switches 2 that are not connected to a common switch module.
FIG. 7 shows a configuration wherein the ATMU can be separated physically
from both the CBP and the SM; both the NCT link and the SONET/ATM link are
arranged to transmit signals over longer distances. Clearly, if the ATMU
abuts or is part of either the SM or the CBR, these facilities can be
simplified.
As an ATM crossconnect unit, the CBP is able to perform the function of
connecting ATM cells between ATM inlets and ATM outlets. To ensure that
the composite CBR cells that carry voice traffic are not delayed or lost,
the CBR cells are given high priority. They are sent on facilities that
are selected to have sufficient bandwidth to support their transport, and
buffering is always able to accommodate these cells. Simulations have
demonstrated that the probability of a delay across a CBP in excess of 50
.mu.s for a CBR cell, even when facilities are fully loaded, is less that
1.times.10.sup.-11. Narrowband VBR signaling and other priority cells are
guaranteed transport via margins of bandwidth in the facilities that are
reserved for this purpose. Those VBR cells use buffers that are separate
from the CBR cells, even though they are on the same facility. Broadband
connections use separate facilities coming directly into the CBP. These
broadband signals use different buffers in the CBP that are separate from
the narrowband CBR and VBR buffers.
The CBP is connectable to a network, as illustrated in FIG. 1, or can
simply be used to interconnect a group of ATMUs and their connected SMs to
form a single giant switching system or switching system cluster, the
giant system or cluster being connected to other switching systems via a
network connected to the SMs. During a transitional period, the existing
time multiplexed switch (described in the AT&T Technical Journal
reference, for example, on pages 1425-1426) can continue to carry part of
the inter-SM traffic and the ATMUs and CBP can carry the rest.
While in this specific embodiment, the inputs to ATMUs are from a group of
switching modules of a single switching system, such as the modules of a
5ESS switch, the teachings of applicants' invention are equally applicable
if separate switching systems, instead of switching modules, are connected
to ATMUs.
FIG. 8 is a block diagram of an asynchronous transfer mode interface unit
(ATMU) 540. The ATMU is under the overall control of an ATMU Central
Controller (ATMU CC). The inputs are from a time slot interchange unit 517
of one or more switching modules 510. The outputs are to the common
broadband platform (CBP) 550. The ATMU is considered an ingress and egress
node of the network and a PVC interconnects two ATMUs. This allows traffic
from several SMs to be collected for transmission over one PVC from one
ATMU to one ATMU. The outputs of time slot interchange units 517, which
are groups of NCT links, enter space switch 610 which has 48 outputs
leading to cell wide buffer 620 (CWB). Each NCT link carries 512 16-bit
time slots every 125 .mu.s. The 16 bits include 8 PCM or user data bits, 7
internal control bits, and one parity bit. All but the 8 PCM bits are
discarded before an ATM cell is formed. CWB 620 includes 48 separate
byte-organized memories whose outputs can then be used in parallel to form
the 48-byte payload of an ATM cell. The space switch is used to switch the
outputs of the NCT links to the appropriate one of the 48 virtual path
memories 621, . . . , 625. The 48-byte parallel output and a 5-byte
output, representing a header, from the cell list processor 630 enter one
of 8 shift registers 651, .... , 652. The particular shift is selected by
one of the select units 653, . . . , 654 under the control of cell list
processor 630. The output of each of these shift registers goes via one of
the CBR/VBR selectors 663, . . . , 664 to a Line Processing Unit 661, . .
. , 662 (LPU), each LPU generates a SONET/ATM data stream. These 8 data
streams are then switched in common broadband platform (CBP) 550. The term
CBP as used herein refers to an ATM crossconnect switch, having, in this
case, ATM/SONET inputs and outputs. The treatment of VBR cells is
discussed further below. Details of the treatment of packets for VBR cells
are provided in Section 4.4 of the Detailed Description.
The number of NCT links which can be terminated on one space switch is
limited by the speed of the CWB memories and the CLP. If several SMs are
terminated on one ATMU it is desirable to maximize the quantity; in the
preferred embodiment 20 NCT links are used, but a larger number, such as
60, appears feasible with present technology.
FIG. 9 illustrates the space switch 610. 48 selectors 701, . . . ,702, each
controlled by a control memory 703, . . . , 704 are used to switch the
outputs of the incoming NCT links to the appropriate one of the 48 virtual
path memories that form a cell wide buffer. Each byte in each of the NCT
links may go to any one of the 48 positions in the cell wide buffer. In
addition, selector 7 10, under the control of control memory 711, is used
to steer (packetized) variable bit rate data including signaling and other
messages to Message Layer Device 670 (MLD) (FIG. 8). The MLD converts
messages into ATM cells which are transmitted by the cell list processor
630 a CBR/VBR selector 663, . . ., 664 into one of the LPUs 661, . . . ,
662 into the CBP after the CBR cells have been transmitted for a given 125
.mu.s.
FIG. 10 illustrates the cell wide buffer 620. It comprises 48 8-byte
memories, 48 units, 621, 622, . . . , 623 each comprising an 8-bit by N
byte buffer 801 and a control memory 802, where N represents the depth
(i.e., number of cells that can be stored) of the buffer. In accordance
with well-known principles of the prior art, in order to preserve frame
integrity, the transmit cell wide buffer is a duplex buffer, one part
being loaded while the other is unloaded; the receive cell wide buffer is
triplex to solve jitter and frame integrity problems. The control memory
steers bytes from the incoming NCT bus to the appropriate position in the
buffer. In addition, the system is arranged to transmit a pseudo random
code to test continuity of DSO channels over ATM facilities; in one
embodiment, the control memory of a CWB is arranged to insert and to
detect the presence of the code under the control of the ATMU CC.
Alternatively, tones from tone sources in the SM can be transmitted over
DS0 channels and detected at the far end.
FIG. 11 illustrates the Cell List Processor (CLP) 630, Facility Shift
Register (FSR) 651, and Line Processor Unit (LPU) 661. The CLP 630
simultaneously reads the CWB 620 while controlling the Selector 653. This
causes one 48 byte CBR cell to be written into the SR 651. In addition,
the CLP outputs the 5 byte header into the SR at the same time. Thus a
full 53 byte cell is loaded into the SR. The cell is now shifted into the
LPU 661 via CBR/VBR selector 663. The LPU 661 transmits the cell onto the
SONET facility to the CBP.
FIG. 12 shows the Message Layer Device 620. The MLD 620 receives messages
on NCT time slots from the Space Switch 610 into Interworking Units 1020,
1022, . . . , 1024. These messages could be inter-SM messages, SS7
messages, or user generated messages such as CCITT X.25 messages. The IWUs
determine the correct pre-provisional ATM Virtual Circuits identifier, and
segments the message into ATM cells per CCITT specifications using the
determined VC identifier and other header fields as described by CCITT ATM
Adaptation Layer specifications. These cells are subsequently shifted out
of the Interworking Unit into the CBR/VBR selector and LPU 661 shown in
FIG. 11, under the control of the CLP. In the preferred embodiment, the
outputs are joined and sent to one or more of the CBR/VBR selectors.
FIG. 13 shows an Interworking Unit 1020. NCT time slots are connected via
the selector 1110 to the data link controller 1120. A Data Link Controller
1120 processes bit level protocol that includes flags, bit insertion, and
CRC. A second controller 1140 processes SS7 or link access protocol within
the messages. A processor 1130 determines the Virtual Circuit to be used
for the message, and commands the ATM Adaptation Layer (AAL) Processor
1160 to segment the message into ATM cells. The ATM cells are placed,
under the control of AALP 1160, into the Cell Buffer 1170 (not to be
confused with Cell Wide Buffer 620 (FIG. 8)) where they are later
transmitted under control of the CLP 630 (FIG. 11) into the CBR/NBR
selector 663 (FIG. 11). High priority cells are inserted into Cell Buffer
1170 before low priority cells. Cells from the cell buffer 1170 (FIG. 13)
constitute the VBR cells shown in FIG. 3 (the 125 .mu.s frame). The cell
buffer may have to be several cells deep to take care of VBR cell bunching
from the CBP.
The AM serves to support the entire 5ESS switch and CBP (including ATMUs)
OAMP needs. These include download and control of the CBP, craft graphical
display, and communication via ATM with SMs. FIG. 14 shows the AM/CBP
system architecture as comprising the following components:
ATM Management Module (AMM) including directly connected terminal. This is
an adjunct fault tolerant processor that connects to the existing 5ESS
switch AM, and serves to provided added processing throughput for new CBP
and ATMU capabilities.
Ethernet.RTM. Bus to interconnect AM/AMM with Graphical User Interface
(GUI), ATM Packet Handler (APH), and CBP.
Small Computer System Interface (SCSI, an industry standard) peripherals
for disk, tape, and CD ROM on-line documentation: These augment the
existing AM non-volatile peripherals.
GUI workstation terminals that supports existing 5ESS switch equipment,
CBP, and ATMUs.
ATM Packet Handler provides the AM/AMM with the ability to communicate via
ATM over SONET to the SMs. The SMs terminate the APH's ATM in their ATMU
MLDs. To communicate with SMs, the AM/AMM sends messages via Ethernet to
the APH which performs the message to cell conversion and transmittal to
CBP over SONET.
The GUI and non-volatile memory are commercial components whose control
resides in AMM software. The design of the AMM and APH components are
expanded in Section 5 of the Detailed Description.
FIG. 15 illustrates the path hunt which is performed by a switching module
processor 511, or other processor having data about the status of PVCs
from the connected ATMU to the destination of the call. This processor
receives a path request (action block 1200) and determines (test 1202) if
there are any available paths (channels) on direct active virtual CBR
circuits to the destination of the path request. If so, then an available
path is selected (action block 1204) and a message is sent to the node
(typically, a processor for another ATMU) at the other end to notify that
node that a path has been established on a particular slot of a particular
active CBR PVC.
If no available paths on direct active CBR PVCs are found in test 1202,
then test 1202 is used to determine if there are any available paths on
alternate active CBR PVCs. If so, then an available path from one of these
alternate active virtual circuits is selected (action block 1210) and the
node at the other end is notified (action block 1206). (An alternate
active virtual circuit is an active virtual circuit using an alternate
route which is a route that uses at least two links instead of the single
link direct route.) If no paths are available on active virtual circuits
for this path request, then a request is made to allocate an additional
virtual circuit (action block 1212). This request is sent to the
administration module 530 (FIG. 7) which activates an additional virtual
circuit as described in FIG. 16. Eventually, the administrative module
responds to SMP 511 with a success or failure indication and, in the case
of a success indication, the identity of the allocated virtual circuit.
Test 1214 is used to determine that success or failure. If the allocation
request has been successfully responded to (positive output of test 1214),
then test 1202 is reentered in order to perform the process of selecting
an available path. If the allocation process was unsuccessful (negative
output of test 1214) then an all circuits busy treatment is given to the
call for which the path request was originally received in block 1200.
It is assumed in this discussion that the controlling processor, such as
the switching module processor maintains a list of active CBR virtual
circuits for carrying traffic outgoing from its associated switching
module and maintains an activity state for each channel of such a virtual
circuit. It is, of course, also possible to maintain this information
elsewhere such as in the administrative module, but the suggested
arrangement minimizes the time required for establishing most calls.
Further, it is possible to use virtual CBR circuits with two-way channels
but such an arrangement, while it allows for more efficient use of the
virtual channels, requires negotiation between the two endpoints in order
to prevent 37 glare" (i.e., a situation wherein the same channel is seized
concurrently by the two end nodes connected to the channel).
FIG. 16 describes the process of activating a virtual CBR circuit. Many
more virtual CBR circuits are provisioned (i.e., stored in memories of the
network) than can be active at any one time. Basically, virtual CBR
circuits are provisioned to handle the peak traffic between any pair of
nodes (in this case switching modules). Virtual CBR circuits are
considered activated when they are available for carrying traffic. The
process of activation is designed to ensure that the physical ATM circuits
carrying the virtual CBR circuits are not overloaded and that no defective
physical ATM circuits are used to carry traffic. In case of a failure, for
example, all virtual CBR circuits that use the failed facility must be
deactivated.
In this specific embodiment, the process of activating virtual CBR circuits
is analogous to the process of seizing individual trunks in accordance
with the teachings of the real time routing arrangement as described in G.
R. Ash et al.: U.S. Pat. No. 5,101,451, by routing additional traffic over
less heavily loaded transmission facilities, in this case, SONET/ATM
facilities. One special characteristic of the arrangement described herein
which is not analogous to a situation encountered in routing traffic over
individual trunks is the use of split groups, illustrated in FIG. 5, i.e.,
active virtual CBR circuits a portion of whose channels are used for
outgoing traffic in one direction and another portion of whose channels
are used for outgoing traffic in the other direction. Such split groups
are especially efficient for use in carrying traffic between two nodes for
which the level of traffic is relatively low. Another difference is that
more links may be required for alternate routed traffic so that the load
of several links may have to be considered in selecting an alternate route
PVC for activation.
An administrative module receives an allocate request from a switching
module processor 511 (action block 1300). The administrative module first
determines (test 1302) if there any virtual CBR circuits carrying split
traffic (i.e., outgoing from the two end nodes). If so, the administrative
module determines how many circuits are currently busy in each direction
and checks if there is adequate margin in the split group to allow for an
additional few channels to be allocated in the direction associated with
the allocate request. The channels of split groups are arranged so that
the first n channels are hunted in one direction and the remainder in the
other direction and that the hunt for a channel is performed in such a way
as to keep the middle channels available whenever possible. If middle
channels are available and if the number of these available channels is
sufficiently large to allow for a movement of the division point (positive
result of test 1304) then the split point is moved (block 1306) and the
two end nodes are so informed (action block 1308). The requesting node is
informed of a success in response to the allocate request and when the
requesting SMP retries test 1202 and 1208, one of these will now pass. In
this embodiment split groups are checked first; simulation studies may
show that the alternative of checking for available additional PVCs first,
is more optimum.
If no split groups are available (negative result of test 1302) or if there
is inadequate margin in the split group(s) (negative result of test 1304)
then test 1320 determines if there is an available idle provisioned direct
virtual CBR circuit. If so, it is necessary to check whether activation of
an additional CBR PVC will cause congestion on any link carrying that PVC.
If such congestion is found, that idle provisioned direct virtual CBR
circuit is rejected and not activated, and test 1324 is tried; if no
congestion is caused, that circuit is activated (action block 1322) and
the two end nodes of that circuit are informed of this activation (action
block 1308). Otherwise, test 1324 is used to determine if there are any
alternate available virtual CBR circuits. In making the choice among
available alternate CBR circuits, the principles of real time network
routing are used by preferably selecting available alternate virtual CBR
circuits that use relatively lightly or less heavily loaded ATM
facilities. In making the determination of which facilities are less
heavily loaded, since two link circuits are preferred over 3-link
circuits, the loading of the potential 2-link circuits can be ascertained
by requesting the administrative module connected to the CBP that is
connected to the destination switching module to report on the loading of
its ATM circuits. Since each activation of a virtual CBR circuit
represents a larger utilization of resources (48 channels versus 1
channel) than is the case for the selection of a single trunk for real
time network routing, a loading threshold limit beyond which virtual CBR
circuits should not be activated should be applied for any facility that
is used by a candidate CBR PVC. The limit is also affected by the amount
of VBR traffic supported by the ATM facilities. Clearly, this limit is a
parameter which should be under control of the network administrators,
which may be different for different ATM facilities, and which should be
adjusted as field experience is obtained.
Note that in the preferred embodiment, all provisioned PVCs have a
predetermined path traversing two end nodes and a variable number of
intermediate nodes. Alternatively, partly provisioned 37 PVCs" could be
provided having a variable path selected at activate time.
If no available alternate CBR virtual circuits are available for
assignment, then the allocate system returns a failure indication to the
requesting SMP (action block 1326). If an available alternate circuit has
been chosen (action block 1328) (the available circuit is selected among
alternate circuits with relatively low load) then the alternate circuit is
activated (action block 1330) and the end node and intermediate CBP
switches are notified of the activation of the CBR virtual circuit.
The active CBR PVC consolidation process will now be discussed. In the
course of normal toll call activity, it usually happens that different
composite cells between two end nodes are not completely filled.
Furthermore, it is a frequent occurrence that the total number of DSOs in
two or more active composite cells is less than or equal to the total
number of DSOs supported by one composite cell (48/46). In that case it is
desirable to consolidate the PVCs carrying these cells to form one more
fully utilized cell that carries the DSOs. The PVC for composite cells
which no longer have active DSOs can then be made inactive, thus freeing
bandwidth on one or more ATM facilities. That freed bandwidth can then be
used for composite cells between other sources and destinations. Thus,
more efficient utilization of the network is achieved. The consolidation
process is described in FIG. 17.
In the discussion that follows the composite cells being consolidated will
be discussed as being between SMs, and the processing of consolidation is
performed by the SMPs of the two SMs. Alternatively, and especially for
the architecture wherein several SMs are connected to | | |
